Attachment K-418-XO-RPT-0045-FPGA 1.0.pdf

Effective Date: August 10, 2022 418-XO-RPT-0045

Expiration Date: Five years from date of last signature Version 1.0

Responsible Organization: GeoXO Flight Project/Code 418

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Geostationary Extended Observations (GeoXO)

Flight Project Technical Report

Field Programmable Gate Array (FPGA)

Design Review Methodology Signature page

Prepared by:

Email approved by:

08/11/2022

Michael Roza Date

GeoXO Flight Project, Electrical Systems Engineer

NASA GSFC, Code 517

Reviewed by:

Electronically approved by:

08/10/2022

Steven W. Bidwell Date

GeoXO Flight Project, Mission Systems Engineer

NASA GSFC, Code 418

Approved by:

Electronically approved by:

08/10/2022

Monica Todirita Date

GeoXO Flight Project, Deputy Project Manager (DPM)

NASA GSFC, Code 418

Effective Date: August 10, 2022 418-XO-RPT-0045

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Table of Contents

1. PURPOSE

2. APPLICABLE DOCUMENTS

3. INDEPENDENT REVIEW AND ACCEPTANCE OF FPGA DESIGN DATA PACKAGE

3.1 OFF-SITE INDEPENDENT REVIEW

3.2 ON-SITE INDEPENDENT REVIEW BOARD

APPENDIX A – GeoXO FPGA DESIGN REVIEW CHECKLIST

Effective Date: August 10, 2022 418-XO-RPT-0045

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1. PURPOSE

This technical report briefly describes the review methodology adopted by the Geostationary

Extended Observations (GeoXO) Flight Project to assure that the design, implementation and testing of Flight FPGA devices utilized in the GeoXO spacecraft and instruments are developed in accordance with the 500-PG-8700.2.8 NASA Procedures and Guidelines - Field Programmable

Gate Array (FPGA) Development Methodology and the 500-PG-8700.2.7 NASA Procedures and

Guidelines - FPGA Design Guidelines.

It also establishes a Checklist for use by GeoXO Flight Project Personnel in performing a detailed review of a flight FPGA using the information supplied by the vendor in the FPGA Design Data

Package. The Checklist is based on NASA GSFC 500-PG-8700.2.7, Procedures and Guidelines

(PG) for Design of Space Flight Field Programmable Gate Arrays, and is augmented with lessons learned from several Goddard Space Flight Center (GSFC) and other programs within and outside of National Aeronautics and Space Administration (NASA).

The Checklist looks for questionable/problematic circuits both internal and external to FPGAs in space applications and reflects a preference for fully synchronous design methods. The Checklist provides items that are applicable to any FPGA as well as specific items for Actel RTSX and

RTAX FPGAs, as these are the typical types of FPGAs that have been used. The Checklist does not specifically assess whether the FPGA meets its requirements, as requirements flow-down and compliance should be assessed in other reviews. Also, FPGA designs should not necessarily

“comply” with this checklist. Deviations from checklist items should be justified and may be acceptable.

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2. APPLICABLE DOCUMENTS

• 500-PG-8700.2.7, NASA Procedures and Guidelines, FPGA Design Guidelines

• 500-PG-8700.2.8, NASA Procedures and Guidelines, Field Programmable Gate Array

(FPGA) Development Methodology

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3. INDEPENDENT REVIEW AND ACCEPTANCE OF FPGA DESIGN

DATA PACKAGE

The GeoXO Project performs an independent assessment of all FPGA designs against the design guidelines contained in 500-PG-8700.2.7, Design of Space Flight Field Programmable Gate

Arrays, using the information in the FPGA Design Data Package Contract Data Requirement List

(CDRL).

At a point established by the vendor in the approved FPGA Development Plan, the vendor supplies the government with a complete FPGA Design Data Package. This normally occurs after place and route, timing analysis, and signal integrity analysis have been completed and before testing has begun.

There are two acceptable formats (Off-site and On-site) for conducting the independent assessment, which are depicted in the following sub-sections. The particular format used is at the option of the vendor.

The advantage of using the On-Site method is that it still accomplishes an independent review while:

1) Allowing the vendor to immediately answer any reviewer questions and clarify points of design,

2) Providing instant feedback and comment on the FPGA Design to the vendor, and

3) Eliminating the schedule uncertainty involved with sending potentially multiple iterations of questions and comments between the vendor and an off-site reviewer.

3.1 OFF-SITE INDEPENDENT REVIEW

An FPGA Expert chosen by the GeoXO Flight Project performs an independent assessment of the vendor submitted FPGA Design Data Package against the design guidelines contained in 500-PG-

8700.2.7, Design of Space Flight Field Programmable Gate Arrays. The Independent Reviewer is someone who supports the GeoXO Project Office, but not responsible for the oversight of the development of that FPGA.

The Independent Reviewer utilizes the GeoXO FPGA Design Review Checklist provided in

Appendix A to perform the analysis of the FPGA design. The checklist is provided to the vendors as a guide for them to prepare their designs for independent review. The review is conducted following Lab testing and prior to FPGA burn.

Using the checklist, the Independent Reviewer generates questions and comments on the material contained in the FPGA Design Data Package. The vendor reviews and assesses all questions and

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The independent review is complete when the reviewer is satisfied that all questions and comments in the GeoXO FPGA Design Review Checklist have been addressed. The reviewer notifies the

GeoXO Flight Project of any instances where the vendor decided not to take the recommended action(s). A report is then prepared which includes all the vendor responses to any reviewer questions, any perceived risks associated with the FPGA Design, and the final version of the checklist with reviewer comments and vendor responses.

3.2 ON-SITE INDEPENDENT REVIEW BOARD

At the vendor’s option, an alternate method to independently review the FPGA Design is via an

Independent Review Board at the vendor’s facility. An FPGA Expert chosen by the GeoXO Flight

Project serves as the Lead Reviewer for the independent review effort. The review board meeting need not be a separate, formal review; it can be combined with an appropriate existing vendor review and is conducted following Lab testing and prior to FPGA burn.

The vendor provides an agenda, a completed GeoXO FPGA Design Review Checklist (Appendix

A), and the complete FPGA Design Data Package at least one week prior to the review board meeting (two weeks preferred). In order to utilize this option, the review agenda must include an item by item review of the submitted checklist. The Lead Reviewer is someone who supports the

GeoXO Project Office, but not responsible for the oversight of the development of that FPGA.

The Lead Reviewer and other FPGA Experts assess the FPGA Design Data Package prior to the

Review Board Meeting. The Lead Reviewer is responsible for recording action items against the

GeoXO FPGA Design Review Checklist, documenting them in the format appropriate to the contract, reviewing action item responses, and determining which items can be closed. For any items where the vendor and the Lead Reviewer cannot reach closure, the GeoXO Flight Project participates in resolving these items.

The work of the Independent Review Board is complete when all action items are closed and the

Lead Reviewer is satisfied that all questions and comments in the GeoXO FPGA Design Review

Checklist have been addressed. The reviewer notifies the GeoXO Flight Project of any instances where the vendor decided not to take the recommended action(s). A report is then prepared which includes all action item responses, any perceived risks associated with the FPGA Design, and the final version of the checklist with reviewer comments and vendor responses.

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7.4.

7.5.

7.6.

7.7.

9. Asynchronous Reset and Preset Driver(s) Ref: 12 Name Purpose and scope within and outside of the

FPGA

Assertion and/or Negation Method

Timing margin relative to oscillator, PLL, clock tree, etc.

start-up times, min operational vs.

min needed pulse widths and/or clock edge(s)

Verified by test, sim, other analysis, etc.

Comments/Actions

Example_Discrete_Reset Only resets SpW interface

Synchronous assertion if >= 1 msec for 8 clocks

Simulation

Example_CPU_Wdog Only resets CPU interface (and

CPU)

1 clock wide synchronous pulse if watchdog not petted

Simulation/Test

9.1.

9.2.

9.3.

13. State Machines Ref: 16 Name Qt y Encodin g (ex:

compact

Number of defined states

Undefi ned states after

Error detection and/or correction method (ex: none, TMR FFs, TMR FFs

Error notification (ex: none, status bit

System consequence(s) and response(s)

Comments/Actions

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, one-hot) synthe sis (Y/N)

+ Hamming) asserted, interrupt asserted) to an upset [PG 2-7 (4.4)]

Example_arbi ter

1 Compac t

8 N TMR FFs + Hamming

Interrupt asserted

None or 1 data word corruption

Example_Bul k_RAM_RW

3 One-hot 7 Y TMR FFs None Data corruption until ground intervention

13.1.

13.2.

13.3.

13.4.

13.5.

13.6.

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APPENDIX B – ACRONYMS

AX/RTAX version of FPGA

CDC Clock Domain Crossing

CDRL Contract Data Requirement List

CLKA/B Clock A or B

CQFP Columnar Quad Flat Pack

DEDA Engineering Design Assist

DLL Digital Logic Loop

DPM Deputy Project Manager

FF Flip-Flop

FIFO First in First Out

FPGA Field Programmable Gate Array

GeoXO Geostationary Extended Observations

GSFC Goddard Space Flight Center

JTAG Joint Test Action Group

LVDS Low Voltage Differential Signalling

MHz Megahertz

MIL Military

NASA National Aeronautics and Space Administration

PG Procedures and Guidelines

PLL Phase Lock Loop

POR Power On Reset

PRA, PRB, PRC, PRD Test Probe outputs

PWA Printed Wiring Assembly

PWB Printed Wiring Board

QCLK Q-type register clock

QCLKBUF Buffer for QCLK

RAM Random Access Memory

RCLK Register clock

ROM Read Only Memory

RTAX version of FPGA

RTSX version of FPGA

SDRAM Synchronous Dynamic RAM

SET Single Event Transient

SEU Single Event Upset

SX version of FPGA

TBD To Be Determined

TCK JTAG Test Clock

TDI JTAG Test Data In

TDO JTAG Test Data Out

TMS JTAG Test Mode Select

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TMR Triple Module Redundancy

TRST JTAG Test Reset

VHDL Very High Definition Language

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Document Change Record (DCR)

418-XO-RPT-0045 DCR

CCR GeoXO X00110 Rev: Title: 418-XO-RPT-0045: baseline the Field Programmable Gate Array (FPGA) Design Review Methodology Contract # N/A GeoXO S/C: GeoXO Effectivity: Instrument

CCB Status: Approved Doc #: 418-XO-RPT-0045 CCB Date: 08/10/2022 Doc Version: 1.0 Contract Mod#: N/A DOORs Version: N/A Doc Change Date: Aug. 10, 2022 DOORs ID #: N/A