Attachment Q MEL.pdf
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- Attached to
- GeoXO Spacecraft DRAFT Request for Proposal (DRFP) Phase B Implementation Procurement Federal contract opportunity
- Solicitation number
- 80GSFC23R0010
About this file
This document provides a Mass Equipment List (MEL) supplemental instructions for the GeoXO Spacecraft DRAFT Request for Proposal (DRFP) Phase B Implementation Procurement opportunity issued by the National Aeronautics and Space Administration Goddard Space Center. The MEL instructions require proposers to provide current best estimates and contingency values for the mass, power, number of units, and heritage basis for each major flight element and component. Additionally, proposers must identify planned spares, engineering models and prototypes with their fidelity levels, required deliveries for simulators and testing, and component-level contingency allocations. For electronic boards and specialized integrated circuits, proposers must list the functionality, operational speed, design size, and board inclusion. The instructions also specify providing software element details like lines of code counts by Computer Software Configuration Item, functionality descriptions, and development methods utilized.
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New Technology or Engineering Change Options
NT
EC
Identical
Heritage Level Options F P N
NA
1. The flight elements and components entered on each row should be traceable to block diagrams and heritage claims provided in other parts of the proposal. For each major component, current best estimates (CBE) and contingency for mass and power, number of flight units required, and some description of the heritage basis must be provided. Power values should represent nominal steady-state operational power requirements. Information to be provided includes identification of planned spares, indentification of engineering models and prototypes with their fidelities, required delieveries for simulatiors and testing, contingency allocations for individual components, and other component
2. List each electronic board separately, identify the functionality of each board (either in the MEL or in the proposal), and provide the operational speed of the board. If proposing Field-Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs), or Radio Frequency Integrated Circuits (RFICs), list the design size (in the appropriate sizing parameter such as number of logic cells or logic elements), the board that will include the chip(s), MEL Supplemental Instructions:
Provide the following data for Software elements: (1) the number of logical lines of code by Computer Software Configuration Item (CSCI); (2) description of the functionality for each CSCI; (3) code counts categorized as either New, Modified, Full Reuse, or Auto-generated; (4) development method (spiral, waterfall, agile, etc.), Instructions for software (can be included under the heading for HERITAGE JUSTIFICATION and ADDITIONAL INFORMATION)
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