Test Strategy Report_Sample.docx

Test Strategy Report

Contract/ DO # for

Unit Under Test

UUT Nomenclature: Power Drive Unit, Antenna Control System UUT Part Number: 99-370-2700-15 from

Weapon System

ATE SYSTEM(S)

AN/USM-717(V) 2

Developed for Refer to SOW

Developed by Contractor Name Contractor Address

DISTRIBUTION STATEMENT: Refer to associated CDRL.

Document Control Number: TSRXXXXXXX Date

TSR REVISION SUMMARY

TSR TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

Reference Documents

Automatic Test Equipment

System Design Document Doc # 7992008 VIPER/T AN/USM-657(V) 1 – 4

Unit Under Test (UUT)

UUT P/N: 99-370-2700-15

UUT Manufacturer: General Dynamics SATCOM Technologies UUT Model Number: 123T UUT Nomenclature: Power Drive Unit, Antenna Control System UUT Type: LRU

Table 1: UUT Reference Documentation

Oct 2011

UUT Description

UUT general physical description

The 123T is designed to fit into a standard 19” rack. It is 1 RU (1.75”) high and 17.13” deep.

The front has the power switch, an indicator lamp, a 10 amp circuit breaker, and a 26-Pin military standard connector. The rear contains 8 D-Sub connectors (2 9-Pin Females, 4 15-Pin Females, 1 37-Pin Female, 1 21-Pin Mixed Signal Female), and an AC power receptacle.

Part Number/Nomenclature

Part Number: 99-370-2700-15 Nomenclature: Power Drive Unit, Antenna Control System Vendor Name/Part Number

Vendor Name: General Dynamics SATCOM Technologies Part Number: 99-370-2700-15 Model Number: 123T

UUT Category (analog, digital, hybrid, etc)

Analog, Radio Frequency/Motor Control

The UUT consists of the following SRAs/SRUs (if WRA/LRU UUT’s):

Table 2: UUT Components

UUT External Connectors

Table 3: UUT External Connectors

Exploded view of repairable assemblies, Test Points, connectors, adjustments, alignment points

Not Available

Disassembly for test/adjustment/alignment

None

Cooling requirements

None

UUT detailed functional description (theory of operation)

The Model 123T Power Drive Unit, part of the VSAT-Large system, is designed to position a transportable antenna in all axes of movement for the purpose of locating satellites of interest. It uses input data from an Antenna Control Unit to position the antenna with the correct azimuth, elevation and polarization for optimal communication with the user input satellite. Correct positioning is established by 3 sets motors, encoders, and limits switches.

Figure 1: UUT Functional Block Diagram

Trade-off Analysis

Functional vs. parametric performance testing

Functional Testing will be employed to test this UUT. The functional testing will stimulate the UUT to best simulate its intended mission and measure the performance in respect to mission requirements. The functional circuits are capable of being tested from the input to the output with access to both, therefore functional testing has been selected.

Fault detection/fault isolation analysis

Due to the design and functional characteristics of the UUT, fault detection will be limited to the use of stimuli and responses of the UUT via external connectors. The diagnostics will be designed to minimize the number of measurements accomplished in order to reduce the run time and to test the highest probable failure circuits first. This TPS will diagnose any failures to the following ambiguity groups:

Table 4: Fault Callouts and Ambiguity Groups

A6*J11

See Appendix A for a more detailed FAM Table.

Test program efficiency analysis

This TP shall fully meet contractual run time and diagnostic requirements. Code reuse will be maximized and atlas call procedures shall be utilized to ensure coding minimization. Sufficient comments shall be provided for full TPS maintainability.

Testing Concepts

As directed by the test program, the UUT, the ID, and the VIPER/T shall be configured as illustrated in the System Interconnect Diagram provided in Section 6 of this document.

Test Philosophy

UUT adjustment/alignment tests

No adjustment necessary.

Diagnostic testing

Test points and probing will be used to keep ambiguity groups to a minimum.

Digital testing

N/A

Power application/Safe-To-Turn-On tests (Test ID xxxxx – xxxxx)

The purpose of this test is to verify the UUT is free of power and ground faults prior to applying power as described in the following paragraph:

A DMM will be used to verify the correct ID is attached via an array of identification resistors. Once the correct ID has been verified, the following impedances of the UUT will be measured to assure safe turn-on:

Power testing and load requirements (Test ID xxxxx – xxxxx)

The output current limit to the azimuth, elevation, and polarization external motors is to be tested by measuring the voltage drop across a shunt resistor using a four terminal Kelvin connection. The polarization motor output will also be loaded down with a larger resistive load to simulate the actual motor impedance. The following table displays the load specification for each test.

BIT/BITE testing (Address all levels of testing, including diagnostics)

N/A

Timing/clock requirements and testing

N/A

Bus and memory testing

The 123T supports serial communication via both RS-422 and RS-232 protocols. Both will be tested and verified by the VIPER/T PC using the COM port.

RF Testing

N/A

UUT unique functions (digital/analog/hybrid)

N/A

Functional Testing (Test ID xxxxx – xxxxx)

Functional testing of the UUT requires sending commands and reading responses from multiple external connectors. These external communications will be simulated using VIPER/T hardware. One of these sources of communication is the PMU link which uses the J10 connector. The PMU link will not be tested directly; however, it will be used throughout this section to command the unit to perform several tasks and verify proper settings. The table below lists the monitoring and control pins of the J10 connector.

Table 7: J10 PMU Pinout

Power Up (Test ID xxxxx – xxxxx)

Table 8: Power Up Tests

ACU Serial Communication (Test ID xxxxx – xxxxx)

Verify UUT is able to communicate serially using the RS-422 Protocol with the ACU through J5.

The ACU will be simulated using the VIPER/T PC. Relevant UUT J5 connector pins are shown below.

Table 9: ACU RS-422 Connections

PMU Serial Communication (Test ID xxxxx – xxxxx)

Verify UUT is able to communicate serially using the RS-422 Protocol with the ACU through J5 in order to relay PMU commands. Communication is one way; therefore, only the capability to receive data will be tested.

The ACU will be simulated using the VIPER/T PC. Relevant UUT J5 connector pins are shown below.

Table 10: PMU RS-422 Connections

Heading Sensor Serial Communication (Test ID xxxxx – xxxxx)

This test will verify the UUT is able to communicate serially using the RS-232 Protocol through J6 to the VIPER/T COM 2 Port.

The Heading Sensor will be simulated using the VIPER/T PC. Relevant UUT J6 connector pins are shown below.

Table 11: Heading RS-232 Connections

Verification that the UUT is correctly receiving commands will be done using the ACU serial communication.

Polarization Motor Testing (Test ID xxxxx – xxxxx)

Instrumentation Required: DMM, Switching

Table 12: POL Motor Parameters

Polarization Potentiometers (Test ID xxxxx – xxxxx)

Instrumentation Required: DC PS, Switching, PC

Table 13: POL Potentiometer Parameters

Tilt Sensors (Test ID xxxxx – xxxxx)

Instrumentation Required: DC PS, Switching, PC

Table 14: Tilt Sensor Tests

Resolver Tests (Test ID xxxxx – xxxxx)

Instrumentation Required: OScope, Resolver Simulator, Switching

Table 15: Resolver Test Parameters

Azimuth and Elevation Motor Current Limit (Test ID xxxxx – xxxxx)

Instrumentation Required: DMM, Switching

Table 16: Az and El Motor Current Test Parameters

Azimuth and Elevation Tachometers (Test ID xxxxx – xxxxx)

Instrumentation Required: DCPS

Table 17: Tachometer Test Parameters

High Rate CW

High Rate CCW

Low Rate CW

Low Rate CCW

High Rate Up

High Rate Down

Low Rate Up

Low Rate Down

Motor Travel Range Faults (Test ID xxxxx – xxxxx)

Verify the UUT recognizes the series of limit switches that are present in the next higher assembly for movement in azimuth, elevation, and polarization. Limit switches, also known as interlocks, will be simulated through a combination of switch contacts using the VIPER/T Switching. Activation of these interlocks will cause faults messages that will be recognized via the ACU serial communication with the PC on the J5 connector and also disable motor movement in certain directions. Table 18 lists each fault, which pins to short to simulate the fault, and the effect of the fault. Enabled and disabled features will be verified using the simulated PMU control via J10.

Before performing the fault tests, the interlocks must be enabled via the ACU serial communication between the PC and J5

Table 18: Limits and Faults Test Parameters

* Normally Closed; Open to activate fault.

Repeat all testing in Table 19 with the interlocks disabled via the ACU serial communication between the PC and J5 and verify the interlocks have no effect on motor control.

Band and Polarization Status Messages (Test ID xxxxx – xxxxx)

To verify the band/polarization status messages, a series of combinations of switches using VIPER/T Switching will be performed. Table 20 lists the switch combinations with the appropriate status message verified using the ACU serial communication between the PC and J5. An “X” in Table 20 constitutes a short to J7-34 (+12V to Pol Feed Type); otherwise it is to be left open.

Table 19: Band Selection Switching Parameters

No Feed

Ka Band, Circular Polarization

X

X

Ku Band, Circular Polarization

X

X Band

X

C Band, Right Hand Circular Polarization

X

C Band, Left Hand Circular Polarization

Additional PMU Tests

Additional PMU control and monitor capabilities will be tested in this section. This test requires ACU serial communication between the PC and J5 along with PMU communication via J10, which again will be simulated by the VIPER/T instrumentation. The table below describes the tests to be performed. Unless otherwise noted, control switches are activated by being closed then opened, simulating a pushbutton switch. The Pass Condition column list the voltage that should be seen on the pin in reference to +12V (J10-G)

Table 20: Additional PMU Test Parameters

J10-N J10-P J10-R ~12VDC High Ω High Ω High Ω

J10-P J10-R

~12VDC ~12VDC ~12VDC

J10-L ~12VDC High Ω

J10-L High Ω

~12VDC

240 MVO Stow Mode (Test ID xxxxx – xxxxx)

Instrumentation Required: PC, DMM

This test will simulate stowing the antenna and verify the UUT’s ability to read limit switches associated with this sequence of events. Before starting this test, use the ACU serial communication between the PC and J5 to set the 240MVO Slow Type. Also, open all simulated interlock switches and connect R14 across the Elevation Motor Outputs (J8-A1 and J8-A2).

Table 21: 240 MVO Stow Test Sequence

Position

Output Voltages (Test ID xxxxx – xxxxx)

Instrumentation Required: DMM

Table 22: Output Voltage Tests

Functional Flow Chart (FFC)

Figure 2: Functional Flow Chart

System Interconnect Diagram

The interface device used for the testing of this UUT can also be used for additional UUTs. Only connections applicable to the testing of this UUT are shown in this section; however, some of the connections may be duplicated on other UUT interconnect diagrams if they are vital to the testing of that UUT.

Overall Hardware Interconnect Diagram

In addition to the cables and hardware contained inside the Interface Device (ID), there will be additional cables and hardware outside of the ID designed as TPH for this test program. They are described below in Figure 3. See Section 11 for specific details on the IH.

Figure 3: Overall Hardware Interconnect

ATE/UUT Compatibility Summary

Table 23: ATE/UUT Compatibility Table

ASSET

RANGE OF

STIMULUS/

RESPONSE

TOLERENCE

ACCURACY

RATIO

CRITICAL

TEST

PARAMETER

(Y/N)

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

DMM Accuracy for Voltage for 100VDC Range: ± (0.0207% * Reading + 0.0033% * Range)

DMM Accuracy for Resistance for 100Ω Range: ± (0.0842% * Reading + 0.0175% * Range)

Current Accuracy via four terminal Kelvin Connection:

Polarization:

(Current * Shunt Impedance) (1.5 ± 0.1A * 0.1Ω) = 150 ± 10mV AZ/EL High Rate Initial:

(Current * Shunt Impedance) (20.0 ± 1.0A * 0.1Ω) = 2 ± 0.1V AZ/EL High Rate Fold Back:

(Current * Shunt Impedance) (10.0 ± 0.5A * 0.1Ω) = 1 ± 0.05V AZ/EL Low Rate:

(Current * Shunt Impedance) (1.0 ± 0.05A * 0.1Ω) = 100 ± 5mV

DMM Accuracy for Voltage for 1VDC Range: ± (0.018% * Reading + 0.0034% * Range)

DMM Accuracy for Voltage for 10VDC Range: ± (0.0184% * Reading + 0.0032% * Range)

Test Constraints

No test constraints identified.

Operator Interaction

Inspect ID/ATE for completeness and visible damage.

A. Connect ID and cables (if any) as shown in the System Interconnect Diagram.

B. Load test program.

C. Perform ID tests.

D. Visually inspect the UUT for bent/broken pins and defective components.

E. Connect UUT to ID as instructed by test program.

F. Perform UUT functional testing IAW the test program prompts.

G. Respond to all operator prompts as required.

H. Perform manual probing as required by the test program I. Perform adj/align as required by the test program.

J. Perform repair actions as required.

K. Restart/Continue functional testing as required by the test program.

L. Remove UUT from the test configuration and return to stock/service.

TP Development Specification Non-compliance

Interface Hardware (IH) Preliminary Design Evaluation

Reference ID#2 Design Document, PN xxxxxx, for all specific overall ID design specifications. All ID design information contained in this TSR will be for general reference specific to the subject UUT.

Table 24: External Interconnect Hardware

IH Physical Layout

Interface Device Identification

Figure 4: Interface Device Identification Interconnect

Signal Interconnect

Figure 5: ID Signal Interconnect

IH Circuit Complexity

ID Circuit Complexity

Hardware to be contained in the ID is described in the table below.

Table 25: Internal Interface Hardware

0. Supplemental Test Equipment

None

IH Design Optimization

Reference ID#2 Design Document, PN xxxxxx, for all specific overall ID design optimization specifications.

IH Reliability and Maintainability

Reference ID#2 Design Document, PN xxxxxx, for all specific overall ID design reliability and maintainability specifications.

IH Self-Test Considerations

Mechanical Considerations

Engineering Notes

None

Appendix A – Fault Accountability Matrix (FAM) Table

Fault No.

Component Des./Pin No.

Failure Mode

D/ND

I/NI

Performance Test No.

Detected Diagnostic Test No.

Isolated

Ambiguity Group

Remarks

Appendix B – Detailed Flow Diagram (DFD)

Appendix C – UUT/ATE Analysis Table image1.emf

Microsoft_Visio_Drawing111.vsdx image2.emf

Microsoft_Visio_Drawing222.vsdx image3.emf

Microsoft_Visio_Drawing333.vsdx image4.emf

Microsoft_Visio_Drawing444.vsdx image5.emf

Microsoft_Visio_Drawing555.vsdx image6.emf image7.emf image8.emf image9.emf