Attachment_11_Test_Requirement_for_Production.pdf

THE BOlING COM):'ANV

CODe !DENT. NO. 81205

• THIS DOCUMENT IS:

.-J:

CONTROllED BY FLIGHT CONTROL 2-6031 AU REVISIONS TO THiS DOCUMENT SHAll 8E APPROVED BY THE ABOVE OIGANtlAOON PlIOR TO RELEASE.

PREPARED UNDER o CONTRACT NO. F336S7-83-C-21S4 o IR&D o OTHER

DOCUMENT NO. 0232-11262-1 MODEL AGM-86

TITLE TEST REQlIIREMENTS FOR PRODUCTION

PRINTED CIRCUIT CARDS s FCSE

(A321ot)

ORIGINAL RELEASE DATE 3 - J7-8~

ISSUE NO. TO

-y/ 0/.8"2.- 3/ IS/tv

PREPARED BY

SUPERVISED BY

APPROVED BY

APPROVED BY

,·IItIf· ~

0232-11262-1 :

H 1)0 2'" Q",G

7~B..=t

Brian.E.Keenan Text Box

Brian.E.Keenan Text Box

Tt-IE .llflIIEIND COMPANY

ABSTRACT

This document contains the test requirements for printed circuit boards, prior to installation in the Guided Missile Flight Controller DCU 250/A,(Flight Control System Electronics). Included are the production 'requirements for testing all FCSE circuits on each board and the EM! filter. After successful completion of these tests, the boards are encapsulated and installed in the FCSE, then subjected to FCSE tests.

NOTE

The initial release of this document contains the card test requirements exactly as set forth in Coordination Sheet 2-6052-8000-424 Rev. 0 dated 16 February 1982. This document supersedes the coordination sheet and will be the vehicle for future test requirement changes, if any .

KEY WORDS

TEST REQUIREMENTS

FLIGHT CONTROL SYSTEM ELECTRONICS (FCSE)

CARD TEST

PRINTED CIRCUIT BOARDS

AC POWER SUPPLY

DC POWER SUPPLY

BITE CARD

ROLL CARD

PITCH CARD

1._1 D232-11262-1

DO BOOO 21..15 ORIG. 11171

n. IIIII'ING c,...ANY

• TABLE 0 F CONTENTS

PARAGRAPH PAGE

TABLE OF CONTENTS 1.2

LIST OF TABLES 3

LIST OF FIGURES 5

1 INTRODUCTION 6

2 GENERAL NOTES 7

3 GYRO INTERFACE 8

3.1 IMPEDANCE TEST B

3.2 LOADS 8

3.3 POWER REQUIREMENTS B

3.4 EMP PROTECTION DIODES (m:LETED). 8

3.5 CIRCUIT TESTS 8

3.5.1 SINeE DEMODULATOR 16

3.5.2 ROLL RATE DEKlDULA TOR 19

3.5.3 YAW RATE DEMODULATOR "'J

i..

3.5.4 PITCH RATE DEP()OOLATOR 25

3.5.5 WHEEL SPIN MONITOR 28

3.5.6 SENSOR TORQUE ENABLE RELAY 29

4 BITE 30 • 4.1 IMPEDANCE TEST 30

4.2 LOADS 30

4.3 POWER REQUIREMENTS 30

4.4 EMP PROTECTION DIODES ([f:LETEO) 30

4,5 CIRCUIT TESTS 30

4.5.1 FCE POWER-ON LOGIC 34

4.5.2 MULTIPLEXER AND SIGNAL CONDITIONING 36

S COf!t1AND 39

5. 1 IMPEDANCE TEST 39

5.2 LOADS 39

5.3 POWER REQUI REMENTS 39

5.4 EMP PROTECTION DIODES 39

5.5 CIRCUIT TESTS 39

5.5.1 DIGITAL CIRCUITRY 4;;1.

5.5.2 NORMAL ACCELERATION COMMAND (AZC ) 48

5.5.3 THROmE Cotf4AND 51

5.5.4 COSINE ROLL COMMAND (COSBC) 53

5.5.5 SINE ROLL COMMAND (SINSe) 57

5.5.6 ACTUATOR RELAY 58

6 ROLL 59

6.1 IMPEDANCE TEST 59

6.2 LOADS 59

6.3 POWER REQUIREMENTS 59

• 6.4 EMP PROTECTION DIODES ([(LETEO) 59

6.5 CIRCUIT TESTS 59

1.2

0232-11262-1

00 &000 2''''!!! ORrG;. U71

THIl .OllNG OOp,lP4N'r

• TABLE OF CONTENTS (CONTINUED)

PARAGRAPH PAGE

6.5. 1 K01 VARIABLE GAIN AMPLIFIER 63

6.5.2 K" VARIABLE GAIN AMPLIFIER 66

6.5.3 Kp VARIABLE GAIN AMPLIFIER 67

6.5.4 YAW BUFFER AMPLIFIER 68

6.5.5 Kr VARIABLE GAIN AMPLIFIER 69

6.5.6 ROLL INTEGRATOR 70

6.5.7 ROLL SUMMING AMPLIFIER 72

6.5.8 ROLL BODY BENDING FILTER 75

6.5.9 ELEVON SUMMING AMPLIFIER 77

7 PITCH 80

7.1 IMPEDANCE TEST 80

7.2 LOADS 80

7.3 POWER REQUIREMENTS 80

7.4 EMP PROTECTION DIODES (DELETED) 80

7.5 CIRCUIT TESTS 80

7.5.1 AZC AND AZS FILTERS 84

• 7.5.2 AZ SUMMING AMPLIFIER 86

7.5.3 PITCH FILTER 89

7.5.4 Kq VARIABLE GAIN AMPLIFIER 90

7.5.5 KOI VARIABLE GAIN AMPLIFIER 91

7.5.6 KAZ VARIABLE GAIN AMPLIFIER 92

7.5.7 PITCH INTEGRATOR 93

7.5.8 PITCH ERROR SUMMING AMPLIFIER 95

7.5.9 PITCH BODY BENDING FILTER 98

8 AC POWER SUPPLY 101

8.1 IMPEDANCE TEST 101

8.2 LOADS 101

8.3 POWER REQUIREMENTS 101

8.4 EMP PROTECTION DIODES (DELETED) 101

8.5 CIRCUIT TESTS 101

9 D.C. POWER SUPPLY 106

9. 1 IMPEDANCE TEST 106

9.2 LOADS 106

9.3 POWER REQUIREMENTS

(DELETED)

9.4 EMP PROTECTION DIDOES 106

9.5 CIRCUIT TESTS 106

ACTIVE SHEET RECORO 113

REVISIONS 115 • 2.

0232-11262-1

DO eooo ~'4! ORlli. 4171

THE B.EING COMII"ANV

LIST OF TABLES PAGE • 3.1-1 IMPEDANCE TESTS FOR GYRO INTERFACE 9

3.2-1 LOAuS FOR GYRO INTERFACE 11

3.4 1 EMP PROTEGTION DIODES FOR GVRe INTERFACE 14

3.5.1-1 SIN 0E DEMOO TEST CONDITIONS 17

3.5.2-1 ROLL RATE DEMOD TEST CONDITIONS 20

3.5.3-1 YAW RATE DEMOD TEST CONDITIONS 23

3.5.4-1 PITCH RATE DEMOO TEST CONDITIONS 26

3.5.5-1 WHEEL SPIN MONITOR 28

3.5.6-1 SENSOR TORQUE ENABLE RELAY 29

4.1-1 IMPEDANCE TESTS FOR BITE 31

4.2-1 LOADS FOR BITE 32

4.4 1 E"ul) PROTECTION (;)10(;)£& ~gR 8IT~ 33

4.5.1-1 POWER AND OISCRETES 34

4.5.2-1 MULTIPLEXER AND SIGNAL CONDITIONING 37

5.1-1 IMPEDANCE TESTS FOR COHMAND 40

5-2-1 LOADS FOR CO~NO 41

5.4-1 EMP PROTECTION DIODES FOR COMMAND 42

5.5.1-1 TRUTH TABLE 44

5.5.2-1 TEST PERFORMANCE REQUIREMENTS FOR NORMAL

ACCELERATION OAC 49

5.5.3-1 TEST REQUIREMENTS FOR THROTTLE DAC 52

5.5.4-1 COS dc' SIN 0c DC GAIN 55

• 5-5-4-2 COS 0C' SIN 0C AC GAIN 56

5.5.6-1 ACTUATOR RELAY PERFORMANCE 58

6.1-1 IMPEDANCE TESTS FOR ROLL 60

6.2-1 LOADS FOR ROLL 61

6.4-1 EMP PR6TECf19N BIaSES 6!

6.5.1-1 TEST REQUIREP£NTS FOR VARIABLE GAIN

AMPLIFIER 65

6.5.4-1 YAW BUFFER 68

6.5.6-1 ROLL INTEGRATOR DRIFT 70

6.5.7-1 ROLL SUMMING AMPLIFIER 74

6.5.8-1 ROLL BBF GAIN/PHASE RESPONSE 75

6.5.8-2 DC GAIN 76

6.5.8-3 LIMITER 76

6.5.9-1 ELEVON SUMMING AMPLIFIER 79

7.1-1 IMPEDANCE TESTS FOR PITCH 81

7.2-1 LOADS FOR PITCH 82

7.4-1 EMf PR6TECTION BIOSES FOR PITCH 83

7.5.1-1 STEP RESPONSE 84

7.5.1-2 OC GAIN 85

7.502-1 Az SUMMING AMPLIFIER 88

7.5.3-1 PITCH FILTER RESPONSE 89

7.5.3-2 PITCH FILTER DC GAIN B9

7.5 .. 7-1 DRIFT PERFORMANCE 94

7.5.8-1 PITCH EFFOR SUMMING AMPLIFIER 96

• 3 0232-11262-1

00 15000 2 ""15 ORIG. "'71

7.5.9-1 7.5.9-2 7.5.9-3 8.1-1 8.2-1

8.4 1 9.1-1 9.2-1 9.4-1

CO 6000 21011~ ORIG. ""1

LIMITER

GAIN/PHASE

DC GAIN

LIST OF TABLES (CONTINUED

IMPEDANCE TESTS FOR AC POWER SUPPLY

LOADS FOR AC POWER SUPPLY

EMP PROTECTIOP~ BIOSES FOR ,0.£ P8WER SUPPLIES

IMPEDANCE TESTS FOR DC POWER SUPPLY

LOADS FOR DC POWER SUPPLY

EMP PR8TECTI8N DIODES FaR Be POWER SUPPLY

G232-11262-1

PAGE

3.2-1 3.4-1 4.5.1-1 5.5.1-1 5.5.1-2 5.5.2-1 6.5.1-1 8.5.12-1

..... "" """" 5 Ii .. ...... ,e: ... ,."

LIST OF FIGURES

LOAD CIRCUITS

EMP PROTECTION DIODE CIRCUITS

DIGITAL INPUTS FOR FCSE-BITE CARD

ADDRESS DATA

DIGITAL TIMING

RESISTOR LADDER - CALIBRATION

DIGITAL TIMING

400 Hz NOTCH OSCILLATION

0232-11262-1 o

PAGE

102.1

1. INTRODUCTION

The Flight Control System is composed of five (5) printed circuit boards which are:

Gyro Interface

Bite

Conmand

Roll

Pitch

232-11667

232-11668

232-11669

232-11670

232-11671

There are two power supplies used to operate the Flight Control System. Both of the power supply assemblies are made of two (2) printed circuit boards. The two power supplies and their sub assemblies are:

AC Power Su~ply

Mother Board

Daughter Board

DC Power Supply

Mother Board

Daughter Board

232-11676

232-11672

232-11673

232-11677

232-11674

232-11675

The 5 FCSE printed circuit boards dod two power supply assemblies are to be tested according to the requirements specified in this docu~ent. -

The applicable dash numbers to these PC cards are:

pec NUmber n2-11667

232-11668

232-11669

232-11670

232-11671

232-11676

232-11677

Dash Numbers 1, 2. 3, 4

1, 2. 3, 4

1, 2. 3, 4, 5, 6, 7

1,2. 3,4, 5

1. 2, 3, I, 2, 3, 1, 2, 3.

4, 5

0232-11262-1

H

G

IH

G

2. GENERAL NOTES

1 All TTL data inputs shall be defined:

.. a.. 0.00 ±. 0.10 Volts DC

II l'~ 2 .60 .:t O. 10 Vo 1 ts DC

2 Durfng test, each circuit containing an op amp will be checked for oscillation. The oscillation in all circuits will be less than 25 MV rms. The exceptions to this are the Power Supply circuits.

3. Resistor and capacitor tolerances for load circuits shall be + 10% and inductor tolerances + 15%~ unless otherwise spec; fied. -

4. For those OP-lS outputs, not i sol ated by 47 {1 - res i stors t they must not be loaded by greater than 300 'pi co-farads of wirin capacitance(when:connectfng loads or test equipment}.

5 If the exact input voltage cannot be attained then the test procedure documented in Paragraph 7.5.2 can be used to calculate the output tolerance •

DO 11000 lI. '<II! Oft/G. U1'

0232-'-1262-1

B

THill: BillING COM .. ANY

3. GYRO INTERFACE (232-11667)'

3.1 Impedance test. With power off, measure the specified impedance between the points indicated in Table 3.1-1.

3.2 Loads. Prior to performing electrical tests, connect the

specified loads to the pin numbers indicated in Table 3.2-1. Refer to Figure 3 .. 2-1 for loa.d circui~~"

3.3 Power requirements. The following voltage and ground inputs are to be applied to the indicated card pin numbers.

POWER INPUTS PIN NO. RETURNS PIN NO.

+5 ~ O.25VDC @ 1 Amp Max. 52 D GND 53

+15 ~ O.05VDC @ 0.5 Amp Max. 3 A GND 1

-15 ~ O.05VDC @ 0.5 Amp Max. 2

28V RTN 5

Connect digital and analog ground together external to the card under test while it is being tested. Connect the Thermal Plane (Pin 6) to Analog ground (Pin 1) .

3.4 EMP pra!eetie" djo6e!. With power suppl~ yoltao~~ 8ff, ~~form the EMP te~ts bJ applJing a "101 tage till ol1gh a } eS,i ~tancl! to the ~; gn81~ indicated in Table 3.4-1 as shown in Figure 3.4-1. :

3.5 Circuit Tests

, 0232=1-1262-1

TABLE 3.1-1 - IMPEDANCE TESTS FOR GYRO INTERFACE

• MEASUREMENT POINTS IMPEDANCE

PIN NO. PIN NO. ( OHMS)

SMRD-R Hi 48 SMRD-R_Hi T. P. 18 < 1

Sr.RD-R-Lo 50 SMRO-R La T.P~ 20 < 1

SMRD-P Hi 49 SMRD-P-Hi T.P. 19 < 1

SMRD-P Lo 23 SMRD-P La T.P. 22 < 1

StaRD-Y Hi 21 SMRD-Y Hi T.P. 51 < 1

SMRD-Y La 54 SMRD-Y Lo T~P. 24 . 1

Wheel Spinning Disc 45 Wheel Spinning Disc Test 15 < 1

Sin "E 42 Sin "E Test 13 <: 1

Roll Gyro Lo 33 Roll Gyro Test. 32 < 1

Yaw Gyro Hi 7 Yaw Gyro Test. a < 1 • Pitch Gyro Hi 34 Pi tch Gyro Test 35 < 1

DEf()O Sin "E: 36 FFOl£ 39 10K + 1%

Thennal Plane 6 A GNI} 1 > lOOK

DEMOD Roll Rate 11 FF03R 14 10K + 1%

DEKlD Roll Rate 11 RRG 41 < 1

NEG DEMOD Yaw Rate 9 YRG ')0 .... 0 < 1

NEG DEMOD Yaw Rate 9 FF02R 4 10K:!:. 1%

NEG DEMOO Pitch Rate 10 FFOIR 12 10K + 1%

Sin 0E RTN 43 A GND 1 <: 1

Roll Gyro Hi 47 A GND 1 <: 1

Yaw ~ro Lo 46 A GND 1 <: 1

Pitch Gyro Lo 40 A GND 1 <: 1

• Accel. Torq. CMD 58 Accel .. Torq. CMD Test 29 <: 1

[)Z3Z-1-1 ZbZ-1

TABLE 3.1-1 - lHPEDANCE TESTS FOR GYRO INTERFACE (CONTID)

MEASUREMENT POINTS IMPEDANCE

PIN NO .. PIN NO. ( OHMS)

SW Pitch Input Dr1 ve 57 SW Pitch Input Drive Test 28 < 1

SW Elevator CMD Drive 27 SW Elevator CMD Dri ve Test 56 < 1 , 2BV RTN 5

I A GND 1 > lOOK

B

D GND 53 28 V RTN 5 > lOOK

Thermal Plane 6 o GND 53 > lOOK 28 V RTN 5 )0 lOOK

0232-11262-1

B

SIGNAL

NEG CEKlD Yaw Rate

DEKlD Roll Rate

DEKlD Sin er NEG DEl<lD Pi tch Rate

YRG

RRG

Wheels Spinning Discrete·

Accel. Torq. eMQ

TABLE 3.2-1 LOADS FOR GYRO INTERFACE

PIN NO.

I

RETURN PIN NO.

A GND

A GND

A GND

A GND

A GND

A GND

D GND

A GND

0232-11262-1

B

LOAD CIRCUIT

20 K n 1

50 K n, 8 rnA 7

25 K n, 16 rnA 7

100 Kll 1

100 Kll 1

100 m 1.

D1git<:! 3

12.4 K O. It.o 1

I B

FIGURE 3.2-1 LOAD C I RCU ITS

S1 gna 1 f To Test R Equipment

Return

Si gnal t kc R To Test Equipmnt

Return

Signal Vee = 5 ::!:. .25 VDC 619n HI4150

24.9KO

Return -----+----___ _

Signal -----.,.....~lAl'v-k:J.-- Vee = 5 ::!:. .25 VDC 332 Jl I N4150

13.3Kn

Return -----....... -------

Signal-----,..... ....... "Vv--+:2--- Vee = 5 ::!:. .25 voe 1270Q

51.1Ko

IN4150

Return-----+--------

FIGURE 3.2-1

• S1 gnal

Return

Signal

Return

+15V

(PIN 3)

8 S1 gnal

Return

(PIN 1)

Signal • 9

Return

GWS <00

(PIN 26)

PITCH GWS <900

(PIN 24)

ROLL !lWS <900

(PIN 22)

YAW GIIS <900

(PIN 19)

GWS COM

(PIN 39)

LOAD CIRCUITS (CONTINUED)

R

L

1:

11 { R

R

R f:

4.230 3.6m 2.7W

"IT'"

R ,;, R .!n R L f'irr.

.. 4~ !. 3%, 1W }

.. 16.6 nil !:. 10%

0232-11262-1

To Test Equ1pl!I!nt

To Test Equipment

To Test Equipment

To Test Equipment

3 places

TABLE 3.4~1 EMP PROTECTION DIODES

fOR GYRO INTERFACE

• SIGNAL PIN NO. RETURN PIN NO.

SMR - Jl Hi 48 D. GND 53 1

SMRD - LO 50 D. GND 53 1

49 D. GND 53 1

SMRD - P Lo 23 D. GNO 5 1

SMRD - YHi 21 D. GND 53 1

SMRD c Y Lo 54 D. GND 53 1

*Sin ~E 42 Sin ~C RTN 43 2

Roll Gyro Lo 33 Roll Gyro Hi 47 2

Yaw Gyro Hi 7 Yaw Gyro L 46 2

Pitch Gyro Hi Pi tch G o Lo 40 2

• *Thi s diode is to be tes ted in ·one dl Apply a negative polarity test volt (i. e .• connect the negative terminal of· the power up y to Pin 42.).

FIGURE 3.4-1 EHP PROTECTION DIODE CIRCUITS

NOTE:

R Signal v~Input

L-Retum

To Printed Circuit Card

These voltages and currents are characteristics of the diodes and do not include circuit effects. The diodes are to be tested with both a positive and negative polarity voltage (V).

unless otherwise noted.

TEST

CONDITION

1 Veo :

I =

II I' I-liD I •

II '~BD

I .

~ " "60

I

NOMINAL MHlIMUM MAXIMUM

+ 6.8 6.12

175 IlIA

I i6.9 H.1 - 75 Rt'.

.!.. 29.9 18.9 ii II'

. Q1,Q 81 of;

~& WJ

D232-11262-1

7.48 til.S

22.8

19.1.1

VOLTS

velTS

VelTS

V9lTi

3.5.1 Sin 0E DEMODULATOR

ANALOG INPUTS:

Sin liE

400 Hz Ref

Sin 0E Rtn (A. GND)

ANAlOG OUTPUTS:

Demod Sin 0E

A. GND

TEST PROCEDURE:

PIN NO.

1. Supply 7.071 + 7% VRMS at 400.8 + 1.5% Hz to Pin 44. Use Pin 43 for all ac analog signal returns-; and Pin 1 for all dc analog signal returns.

2. For each of the conditions given in Table 3.5.1-1, measure the 1nput voltage (VRMS) at Pin 42 and the output voltage (VDe) at Pin 36, then compare the measured output vol tage against the following computed test limits, using the gain data given in the table for the corresponding input condition:

if input phase = +14°, then use

(~X OUTPUT) = (~X GAIN) (Measured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MIN GAIN) (Measured Input) + (MIN OFFSET) if input phase = +1940 (-166°), then use

(MAX OUTPUT) = (MIN GAIN) (Measured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MAX GAIN) (Measured Input) + (MIN OFFSET) where MAX OFFSET = + .002 VDe

MIN OFFSET = -.012 VDe

000000 a, •• $ CAIQ. il17'

0232-11262-1

TABLE 3.5.1-1 Sin 0E DEMOD TEST COND~TIONS

I A.N.A.lOG INPUT: Sin RtE DEKlO GAIN [C:>" PIN 42 a:::> (VDC/VRMS)

VRMS PHASE MAX GAIN MIN GAIN

7.071 + 14° +VT" + 2.3% +Yr - 2.3%

5.000 + 14°

1 1 3.536 + 14° o (riND) II) -- 0 0

3 .. 536 + 1940 (-166°) -V"l + 2.3% -vz -203%

5.000 . + 194° (-166°)

1 1 7.071 + 1940 (-166°)

~ The Sin 0E analog input signal shall be derived from 400 Hz Ref signal that is applied to Pin 44, to ensure both input signals have the saD! fre'quency. Its al1lJl itude shall be within ~7% of the nominal value given in the table and its phase relative to the 400 Hz Ref signal shall be within + 20 of the nominal value given in the table.

~ The demod gain, tolerance includes terms accounting for the neasur"eD!nt errors in the l11!asured delOOd input and output in addition to the circuit tolerances, and a term for ~he dis tortion in the input ac waveforms.

rl:;> Check output ripple. voltage (25 mVrms maximum).

DO I!:lOO ;i1ol! OI'lIClo, ~/'I

0232-11262-1

TABLE 3.5.1-1 Sin 0E DEMOD TEST CONDITIONS (Continued)

Measurement Accuracy Requirements

1. AC Signals

1 < V < 20.... + .080 VRMS

v < 1'" +.008 VRMS

2. DC Signa 1 s

1 < V < 20 - ±- .02% of reading, ±- .002 Vdc bi as

.1 < V < 1 - ~ .02% of reading, ~ .0002 Vdc bias

V < .1 - .!:. .02% of reading, ~ .00002 Vdc bi as

AC Input Signal Distortion Requirement

THO < 1.5%

00 lK)IJIJ i!"lI O~IC:. &I?~

0232-11262-1

3 .. 5.2 ROLL RATE DEr«lDLn...ATOR

ANALOG INPUTS:

Roll Gyro La

3908 Hz Ref

Roll Gyro Ht (A. Gnd)

ANALOG OUTPUTS:

Derood Roll Rate

A. Gnd

TEST PROCEDURE:

PIN NO.

L Supply 7.071 + 7% VRMS at 3908 + 1..5% Hz to Pin 31. Use Pin 47 for all ac analog signal returns and Pin 1 for all de analog signal returns.

2. For each of the conditions given in Table 3.5.2-1, measure the input voltage (VRMS) at Pin 33 and the output voltage (VOC) at Pin 11, then compare the measured output voltage against the following computed test l1mrtts, uSing the gain data given in the table for the corresponding input condition:

if input phase = 180°, then use

(MAX OUTPUT) = (MAX GAIN) (Measured Input) + (MAX OFFSET)

(MIN OUTPUT) - (MITN GAIN) (Measured Input) + (MIN OFFSET) if input phase - 0°, then use

(MAX OUTPUT) - (MIN GAIN) (Measured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MAX GAIN) (Measured Input) + (MIN OFFSET) where MAX OFFSET = + .. 003 VOC

MIN OFFSET = - .013 VDC

D232-1 T262-1

TABLE 3.5.2-1 ROLL RATE DEMOO TEST CONDITIONS

ANALOG INPUT: Roll :Gyro La DEr-'OD GAIN rr> PIN 33 tr:> (VDC/VRMS)

VRMS PHASE MAX GAIN MIN GAIN

7. 071 00 -vr + 2.3% - V'l:- 2.3%

5.000 00

1 1 3.536 00 o (GND) [D - a a

3.536 180

0 +V2"'"+ 2.3% +v'"2 ~ 2.3%

5.000 1800

1 1 I

1800 7. 071

.~[I:» The Roll Gyro Lo analog input s1gnal shall be derived from 3908 Hz

Ref signal that is applied to Pin 31, to ensure both input signals .

have the same frequency. Its amplitude shall be within ~7% of the nominal value given in the ta~e and its ~ha~e relative to the

3908 Hz Ref signal shall be within ~o of the nominal value given in the table.

-~ The demod gain tolerance includes terms accounting for the measure~ ment errors in the measured demod input and output in addition to the circuit tolerances, and a term for the distortion in the input ac·waveforms.

-II> Check output ri ppl e vol tage (25 mVrms maximum) .

0232 .. 11262-1

.::Ie ~oo :2' .", 0 111,.:0 •• ,' I

TABlLf: 3.5.2~1 ROLL RATE DEMOO TEST CONDITIONS (Continued)

Measurement Accuracy Requirements

1. AC 51 gna 1 s

" V < 20 .. + .080 VRMS

V <";. 1 .... + .008 VRH5

2. DC Signals l.~ V< 20-.±. .02% of reading, + .002 Vdc biias

.1~' V<. 1 - .:!: .02% of reading, + .0002 Vdc bias

V<.l - .:!:. .02% of reading, + .00002 Vdc bias

AC Ihput Signal Distortion Requirement

THO <. 1. 5%

D232~t1262 .. 1

3.5.3 YAW RATE DEMODULATOR

ANALOG INPUTS:

Yaw Gyro Hi

3908 Hz Ref.

Yaw Hyro Lo (A. Gnd)

ANALOG OUTPUTS:

Neg. Oemod Yaw Rate

A. Gnd.

TEST PROCEDURE:

PIN NO.

1. Supply 7.071 !7% VRMS at 3908.+1.5% Hz to Pin 31. Use Pin 46 for all ac analog signal returns s and Pin 1 for all de analog signal returns.

2. For each of the conditions given in Table 3.5.3-1, measure the input voltage (VRMS) at Pin 7, and the output voltage (VDC) at Pin 9, then compare the measured output voltage against the f~llowing computed test limits, using the gain data given in the table for the corresponding input condition:

ii input phase = 180°, then use

(MAX OUTPUT) (MAX GAIN)(Measured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MIN GAIN) H1easured Input) + (MIN OFFSET) if input phase = 00, then use

(MAX OUTPUT) = (MIN GAIN) {Measured Input} + (MAX OFFSET)

{MIN OUTPUT} (MAX GAIN) (Measured Input) + (MIN OFFSET) where MAX OFFSET = + .0075 VDC

MIN OFFSET = - .0325 VDC

0232 .. 11262-1

A 005000 Zl45 ':)AI~. "11

A

TABLE 3.5.3":'1 YAW RATE DEMOD TEST CONDITIONS

ANALOG INPUT~ YAW GYRO HI DEt«)O GAIN l2>' (VOC/VRMS) PIN 7 cc:>

VRMS

2.828

2.000

1.414 o (GND) [D

1.414

2.000

2.828

PHASE MAX GAIN MIN GAIN

-2.5~+ 2.3% -2.5~- 2.3%

1 1 o 0

+2.SVT + 2.3% +2.SVf" - 2.3%

1 1

~ The Yaw Gyro Hi analog input signal shall be derived from 3908

Hz Ref signal that is app11ed to P1n 31, to ensure both input signals have the same frequenc'y.~·. Its amplitude shall be within :!:}% of the nominal value g1ven in the table and its phase relative to the 3908

Hz Ref signal shall be within +20 of the nominal value given in the table.

The demod gain tolerance includes terms accounting for the measurement errors in the measured demod input and output inaddition to the circuit tolerances, and a term for the distortion in the input ac wavefonns.

~ Check output ripple voltage (25 mVrms maximum) .

0232-11262-1

TABLE 3.5.3-1 YAW RATE DEMOO TEST CONDITIONS (Continued)

Meas~~ement Accuracy Requirements

1 . AC Si gna 1 s

1 =r V I( 20 - ~ .080 VRMS

V < 1 ... + .008 VRMS

2. DC Siynals

1" V<20- + .02% of reading, ~ .002 Vdc bias

.1' V< 1 .... ~ .02% of reading, ~ .0002 Vdc bias

V of. • 1 .... + .02% of readi n9, + . 00002 Vdc bl as

AC Input Signal Distortion Requirement

THO < 1 .5%

00 !l00;) 21>UI 0 RIG;. #.171

0232-11262-1

3.5.4 PITCH RATE DEMODULATOR

ANALOG INPUTS:

Pitch Gyro Hi

3908 Hz Ref

Pitch Gyro La (A. Gnd)

ANALOG OUTPUTS:

Neg Demod Pitch Rate

A.. Gnd

TEST PROCEDURE:

PIN NO.

1. Supply 7.071 ~7% VRMS at 3908 ~ 1.5%Hz to Pin 31. Use Pin 40 for all ac analog signal returns, and Pin 1 for all de analog sig1~a1 returns.

2. For each of the conditions given in Table 3.5.4-1, measure the input voltage (VRMS) at Pin 34 and the output voltage (VDe) at Pin 10, then compare the measured output voltage against the following computed test limits, using the gain data given in the table for the corresponding input condition:

if input phase = 180°, then use

(MAX OUTPUT) = (MAX GAIN) (Measured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MIN GAIN) (Measured Input) + (MIN OFFSET) if input phase = Oo~ then use

(MAX OUTPUT) = (MIN GAIN) J01easured Input) + (MAX OFFSET)

(MIN OUTPUT) = (MAX GAIN) (Measured Input) + (MIN OFFSET) where MAX OFFSET 3 +.0075 VDC

DO !KIOO 21"" OflllIG, ""'1

MIN OFFSET = -.0325 VDC

2$.

0232 -1 ~ 262-1

THE BOEING CQM"'/UfY

'u

TABLE 3.5.4-1 PITCH RATE DEMon TEST CONDITIONS

ANALOG INPUT! PIT.OH GYRO HI DEr{)O GAIN I!> .

PIN 34 .£C> (VDC/VRMS)

VRMS PHASE MAX GAIN MIN GAIN

2.828 0° -2.sVr+ 2.3% -2.~VT -.2.3%

2.000 00

1 1 1 .. 414 00 o (Gnd) [])

I

- 0 0

1.414 1800 +2.5"2 + 2.3% +2.5Y'T -2.3%

2.000 1aoO

1 1 2.828 1800

DC;> The Pitch Gyro Hi analog input signal shall be derived from 3908Hz

Ref s1gnal that is applied to Pin 31, to ensure both input signals have the same frequency_ Its amplitude shall b~ within ~7% of the nominal valu~ given in the table and its phase relative to the 3908 Hz

Ref signal shall be within ~20 of the nominal value given in the table.

~ The demod gain tolerance includes terms accou~ting for the measurement errors in the measured demod input and output in addition to the circuit tolerances~ and a term for the distortion in the input ac waveforms.

~ Check output ripple voltage (25 mVrms maximum).

0232-11262-1

TABLE 3,5.4-1 PITCH RATE DEMOD TEST CONDITIONS (Continued)

Measurement Accuracy Requirements

1. AC Signals hf V < 20 ~!. .080 VRMS

\! < 1 -!. . Q08 VRMS

2. DC Signals llfV<20~:':. .02% of reading,:':. .002 Vdc bias

.'I(CV<l ~!. .02% of reading, :':. .0002 Vdc bias

V <.1 H!. ,02% of reading, :':. .00002 Vdc bias

AC Input Signal Distortion Requirement

THO <1.5%

.2.1 0232-11262-1

3.5.5 WHEEL SPIN MONITOR

ANALOG INPUTS

GIS 0°

SMRD-R Hi SMRD-R Lo SMRD-P Hi SMRD-P Lo SMRD-Y Hi SMRD-Y Lo

A. GND

ANAlOG OUTPUTS:

(Pin 16) (Pin 48) (Pin 50) (Pin 49) (Pin 23)

2.5 VRMS ~ 3% & 1.8 ~ 3% VRMS at 400 Hz ~6 Hz.

0.195 + .002 VRMS at 1335 Hz + 2 Hz & 1470 Hz + 2 Hz.

0.195+ .002 VRMS &0.160 + .002 VRMS at 1470Hz+2HZ. - - -

(Pin 21) - (1) (Pin 54) or (2) (Pin 1) NOTE: These are differential inputs; do not connect SMRD Lo to A. GND.

Wheels Spinning Discrete "1"; 2.4 to 5.0 VDC, 40 a max.

(Pin 45) Digital Ground (Pin 53) "0"; 0.2 ~ 0.2 VDC, -1.6 ma max.

TEST PROCDURE:

Apply inputs per table below, monitoring the wheels spinning discrete output;

TABLE 3.5.5-1 - WHEEL SPIN foI)NITOR .

INPUTS OUTPUT

GIS 00 SMRD-R SMRD-P SMRn-y WHEELS SPINNING

DISCRETE (PIN 16/1) (PIN 48/50) (PIN 49/23) \~IN 21/54) (PIN 45)

2.5 Vi{MS .195 VRMS .195 VRMS .195 VRMS

400 Hz 1470 Hz 1470 Hz 1470 Hz 11111

.195 VRMS ,

1335 Hz "0"

.195 VRMS .195 VRMS

1470 Hz 1335 Hz

.19~ VRMS .195 VRMS

1470 Hz 1335 Hz loll VKM::> .195 VRMS 400 Hz 1470 Hz

2.5 VRMS .160 VRMS

400 Hz 1470 Hz

.195 VRMS .160 VRMS

1470 Hz 1470 Hz

.195 VRMS .160 VRMS

1470 Hz 1470 Hz

.195 VRMS

1470 Hz 1'1'1

*GWS 00 (Pin 16/1) voltage amplitude must be lowered prior to increasing SMRD-Y (Pin 21/54) frequency •

DO eooo 2.<48 ORIG. "/71

D232-11262-1

3.5.6 SENSOR TORQUE ENABLE RELAY

ANALOG INPUTS:

ACCEL PRELAUNCH TORQ CHO

ACCEL STIMULUS

PITCH CM!) DRIVE

ELEVATOR CMD DRIVE

SENSOR TORQUE ENABLE

28 VIlC RTN

A. &NO

ANALOG OUTPUTS:

ACCEL TORQ CMD

SWITCHED PITCH INPUT DRIVE

SWITCHED ELEVATOR CHO DRIVE

A. &NO

MEASUREMENT POINTS

INPUT OUTPUT

ACCEL PRELAUNCH ACCEL TORQ CMD

(PIN 26) (PIN 58)

ACCEL STIMULUS ACCEL TORQ CMD

(PIN 55) (PIN 58)

PITCH CMI) DRIVE SW PITCH DRIVE

(PIN 25) (PIN 57)

A. &NO SW PITCH DRIVE

(PIN 1) (PIN 57)

ELEVATOR CMO DRIVE SW ELEVATOR DRIVE

(PIN 30) (PIN 27)

A. &NO SW ELEVATOR DRIVE

(PIN 1) (PIN 27)

PIN NO.

RESISTANCE BETWEEN

MEASUREMENT POINTS

o v. ~~P~! EIl!U_ ~:~~~P~~gUiUEN. SENSOR TORQUE EN.

"(PIN 59) (PIN 59l - =

<a! >100K\l

>100K\l <ZJ

:> 10Ol(!} <211

<211 :> IOOK\l

:> IOOI(!} <ZJ

<31 '.>IOOK\l

0232-11262-1

A

0060002.14 OFlIC;. 4J7!

A

4. BITE (232-11668)

4.1 Impedance Test. With power off, measure the specified impedance between the points indicated in Table 4.1-1.

4.2 loads. Prior to performing electrical tests, connect the specified loads to the pin nU.nbers ir!dicated in Table 4.2-1. Refer to Figure 3.2-1 for load circuits.

4.3 Power requirements. The following voltage and ground inputs are to be applied to the indicated card pin numbers.

POWER INPUTS PIN NO. RETURNS PIN NO. -.-

+5 :!:. 0.25 VDC @ 1 Amp Max 52 o GND 53

+15 + 0.05 VDC @ 0.5 A!lll Max 3 A GND 1

-15 :!. 0.05 VDC @ 0.5 Amp Max 2

28 VDC Un Sw ) 7 ) )28VDC + 1% ) 28 V RTN 5 )300 maMax. )

28 VDC Sw ) 4 )

Connect digital and analog ground together external to the card under' test while it is being tested. Connect Thermal Plane (Pin 6) to Analog Ground (Pin 1).

4.4 EI!!, protection diodes. IIH" ~ewe~ sijjl~ly '/eltages eff, flel'ful'm tile EPIP tests by I!~ply;n!l a voltage thlO~gh a 11!5is~tlnee to the signals illdicated hi Table 4.4"1 as shoWIl ill Fi9~te 3.4-1.

4.5 Circuit Tests

D232-11262-1

TABlE 4.1-1 - -iMPEDANCE- TESTS FOR fiI TE

PIN NO. PI~ NO. (OHMS)

FCE TEST.ClOCK STROBE _15 PRELAUNCH CLOCK STROBE: 45 <1

RMC 39 RMC TP 9 «1

RMC 39 FFI0E 41 10K! 1%

LHC 37 LMC TP 8 <1

Lf«: -- 37 FF09E 11 . 10K.:!:.. 1%

REP 12 FF02D 19 10K 1:. 1%

LEP 40 FFOID 48 10K !. 1%

PRti 46 PRG T.P. 17 <1

FCE ENABLE 21 FF02S 23 10K! 1%

THERMAL PLANE 6 A. GNP 1 >100K

REF SENSE 50 REF SENSE T. P .- 54 10K + 1%

TEST SIGNAL RTN 25 A. GND 1 <1

2av RTN 5 A. G.'4D 1 >100K • 2BV RTN 5- D. GND 53 ~100K

FCE TEST DISC 29 FCE TEST DISC T.P.- 59 <1

FeE PWR-ON RELAY 24 FCE PWR-ON RELA Y 20 <1 FeE TEST DISC RTN - 55 RELAY COMKlN 56 <1

AZ DISABLE 28 AZ DISABLE T.P. 58 <1

ACCEL PRELAUNCH TORQUE 27 ACCEL PRELAUNCH TORQ 57 <1

CMD CMD

28 VDC SW. 4 29 VOC Un SW 7 >2000 TEST RESPONSE 30 TEST RESPONSE TaP, 26 10K .:!:..2 %

D. GNO 53 A. GND - 1 > 8SK

THERMAL- PLANE 6 D. GND 53 >100K

THERMAL PLANE 6 2aV RTN 5 >lOOK FCE ENABLE 21 FeE POWER ON 24 <1

RELAY C~

DZ3Z-II~fi~-l

LEFT ELEVON

POSITION

ELEVAlOR CO~ND t()NITOR

TEST RESPONSE

FeE PWR-ON RELAY

RIGHT ELEVON

POSITION

ACTUATOR CURRENT

LEFT

ACTUATOR CURRENT

RIGHT

AILERON COMMAND

t()NITOR I. REFERENCE SENSE

FeE TEST DISCRETE

Az DISABLE

TABLE 4.2-1 - LOADS FOR BITE

PIN No-I

RETURN

A. GND

A. GND

TEST SIGNAL RTN

28 V TRN

A. GND

A. GND

A. GND

A. GND

TEST SIGNAL RTN

FeE TEST

DISC RTN

A. GND

0232-11262-1

IN NO.

LOAD Clf<CUIT

10 Kn O.lw 1

10 Kn 0 .. 100 1

0.1 Jlf 350 Kn 2

2500 4cu 1

10 KQ 0.1(0 1

10 KG O.Il!} -,1

10 Kn D.lU) 1

10 Kn O.leu 1

0.1 ~ f, 350 KQ 2

SOD 2W 1

4.99 KQ D.1eo 8

TABLE 4.4-1 - EMP PROTECTION DIODES

FOR BITE

SIGNAL PIN NO. RETURN

47 GUID SIG COMMlN.

RMC 39· A. GND

lMC 37 A. GND

REP 12 A. SHD

lEP 40 A. GND

ACTUATOR CURRENT RI 35 A. GND

ACTUATOR CURRENT LEFT 36 A. GND

ELEVATOR COMMAND 33 A. SHD

KlNITOR

LEFT ELEVON POSITION A. GNO

RIGHT ELEVON POSITION

AIlEHON CO~ND 34 f()NITOR

TEST RESPONSE 30

*FCE ENABLE

*FCE TEST DISC

*These diodes are to be t ted in o~e direction only.

Apply a negative polar; y.test voltage (i.e.t connect the negative tenninal f the power' supply to Pins 21 and 29) •

0232-11262-1

PIN NO.

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

5 4

5 4

4.5.1 FCE Power-On Logic

01 gi ta 1 In~uts:

Serial Data CTO'Ck + ~ Prelaunch Clock Strobe Digital GND

Analog Inputs:

Air Vehicle Test Command Guidance Signal Common Re 1 ay COl1lOOn FCE Enable

28 V RTN

Analog Outputs FeE Power-On Relay Command

28 V RTN

FeE Test Discrete FCE Test Discrete RTN Az Disable Accel Prelaunch Torq CMD Analog Ground

Pin No.

TABLE 4.5.1-1 - POWER AND DISCRETES

INPUTS OUTPUTS

Air Relay FeE Test FCE FeE Test Vehicle ca.on Enable Accel Pwr-On otsc:

Test CI4l Pin 56 Pin 21/5 DigitAl Relay CMD Pin 29/55 PIN 47/22 Pin 24/5

0+.001 VDC 28 V RTN Open 1 0-1 VDe ~9~ a.tf:WVO( 3+.1% VDe 28 V RTN Open 1 27.01.1•0 (I2 • SMIlax)

Open Open 1 27+1VDC 3 vee 0-1 voe 3 VDe 28 , RTN Open 2 27+1VDC '7.0+1.0VOC 3VDC Open Open 2 27+iVOC O-l-VOC

0 28 Y RTM 28+1%V 1 27+lVDC 0 ... 1 VDe 'tl2mAmax i • I

L Load digital data per Figure 4.5.1-1 with Bft 10 :I: 1I01i.

2. Load digital data per Figure 4.5.1-1 with Bit 10 == IlII! •

D232-11262 ... 1

Az

Disable Pin 28/1

7.S0+.1VOC

O:!:..tvDe

7.S0+.1VDC

O+.lVDC 7-;SO+.lVDC

7 .. 50!.1VDC

. Accel Prel Torq

CHO

Pin 27/1

0+.1 VDC

O:±:.l vee

0+.1 vee a702+.1VDC

0+.1VOC

~.1VOC

-,i.

, 1 " SE~IAL:IlATA

. (PIN 31)'

ct:K + GATE

(PIN 32)

, • /, I ' r I ' t , . ,

• . I '

·'0

'0

CLOCK/STROBE ____ ......---:....---~---....... fl, 0

(PIN 45) .

NOTES:

(1). Data bits shift~d on the non to "1" transition of.ti:K+~.

Data stored in "0h to "In transition of Clock/Strobe. . .. - - .

(2) For digital input levels see '.General Note1 1 Sheet 7 a

(3) BIT 10 ·:...·Test Accel Relay Cmd BIT BII 11 & 12~': Not used BIT 13, 14. 15. & 16,-: Mult1~lexer Cmd BIT~

FIGURE 4.S~ 1~1 DIGITAL INPUTS FOR FCS£-BlTE CARD

THe •• ,ING eo~"'NY

4.5.2 MULTIPLEXER & SIGNAL CONDITIONING

DIGITAL INPUTS: PIN NO.

Seri al Data 31 )

ClOCk + Gate 32 ) See Figure 4.5.1-1 & ) Table 4.5.2-'1 Clock/Strobe 45 )

Di gi ta 1 Ground 53 I

ANALOG INPUTS:

Wheels Spinning Disc 13 "111 = 2.6 + 0.1 VDC, 40. }.lamax.

UO" = 0.3 ~ 0.1 VOC, -1.6 rna max.

+15 VDC 3 15 VOC + .05 VDC

PRG 46 )

RRG 16 )

NAC 42 )

RMC 39 )

LMC 37 ) + or - 9.9996 ~ .020 VDC, REP 12 ) LEP 40 ) 1 rna max ORe 44 )

OLC 43 )

YGF 51 }

YRG 49 )

Analog Ground 1 )

ANALOG OUTPUTS:

Actuator Current Right 35 ) Actuator CUrrent Left 36 ) Elevator Command Monitor 33 ) Aileron ColllJ1and Monitor 34 ) See Test Procedure Left Ilevon Position 10 ) Right Ele~on Position 14 } Test Response 30 ) Ref. Sense 50 ) Ana log Ground 1 )

TEST PROCEDURE:

Apply inputs per Table 4.5.2-1, monitoring outputs to specified tolerances in Table 4.5.2-1. This test is designed to not require the measurement of the analog input signals (i.e., the analog input signal tolerances are compatible with the test equipTMnt D/A converter accuracy).

-Measurement accuracy requirements:

0015000 21-4rJ OFilGi. ~/--"

1 < Ivr< 20.,·~ .02% of reading, ~ .0020 Vdc bias .1 j', 1 V'< 1., ~ .02% of reading, :!:. .0002 Vdc bias

IV1< .1~ ~ .02% of reading, ~ .00002 Vdc bias

0232-11262-1

PIN NO.

VOLTAGE

X

PIN 44

+9.9996 VDe

-PIN 44

-9.9996 VDe

PIN 44

+9.9996 VDe

PIN 44

-9.9996 VDe

PIN 12

+9.9996 VDe

PIN 12

-9.9996 VDC

PIN 40

-9.9996 VDe

~N40 .9996 VDe

PIN 39

+9.9996 VDe

PIN 39

-9.9996 VDC

PIN 37

-9.9996 VOC

PIN 37

+9.9996 VDC

PIN 46

+9.9996 VDC

PIN 46

-9.9996 VDC

PIN 16

-9.9996 VDC

PIN 16

+9.9996 VDe

PIN 49

+9.9996 VDC

ANALOG INPUTS

TABLE 4.5.2-1

MULTIPLEXER & SIGNAL CONDITIONING

DIGITAl INPlITS ANALOG OUTPUTS

PIN NO. WHEEL SPIN . TEST RESP. BIT BIT IB :T BIT BIT PIN NO.

VOLTAGE

X

PIN 43

+9.9996

PIN 43

-9.9996 VOC

PIN 43

-9.9996 VDC

PIN 43

+9.9996 VDe

X

X

X

X

X

X

X

X

X

X

X

X

X

DISCRETE

(PIN 13) 16 15 14 13 10

0 0 0 0 0 0

0 0 0 1 0 0

C 0 0 1 0 0

0 0 0 0 1 0

0 0 0 0 1 0

0 0 1 0 0 0

0 0 1 o· 0 0

0 0 a 1 1 0

0 o. 0 1 1 0

0 0 1 1 0 0

0 0 1 1 a 0 a a 1 0 1 0

0 a 1 0 1 0

0 1 0 0 1 0

0 1 0 0 1 0

0 1 () 0 0 0

0 1 0 0 0 0

0 1 0 1 0 0

CONTINUED ON NEXT PAGE

0232-11262-1

(PIN 30) VOLTAGE VOLTAGE

X' 9.987+.0607

PIN 33

+9 .9526~.02B7 +9.999 8±.. 0361

PIN 33 -.0038+.0361 -9.9526+.0287 -

PIN 34

-9. 952.6.±. 0292 -.0038+.0361

PIN 34

+9 .9526 +.0292 +9.9998+.0361

PIN 14

+9.9526+.0349 +9. 9998!.. 0373

PIN 14

-9.9526+.0349 - • 00 38!.. 0373

PIN 10

-9.9526 +.0349 -~OO38!..0373

PIN 10

+9.9526 +.0349 +9 .. 999B.:!:. 0373

PIN 35

+9.~5?6+.0349 +9. 9998±..0373

PIN 35

-.0038+.0373 -9 .9S26 +.0349

PIN 36

-9 .95267_" 0349

-.0038+.0373

PIN 36

+9 .. 9526+ +9.999B±..0373

X +9. 9998±.. 0373

X - • 00 38!.. 0373

X -.0038+.0373

X +9.9998+.0373

X +9.9998+.0373

PIN NO.

VOLTAGE

PIN 49

-9.9996 VDC

PIN 51

-9.9996 VDC

PIN 51

+9.9996 VDC

-pfN 42

+9.9996 VDC

PIN 42

-9.9996 VDC

PIN 42

-9.9996 VDC

X

• NOTE:

TABLE 4.5.2-1 (CONTINUED)

MULTIPLEXER & SIGNAL CONDITIONING

ANALOG INPUTS DIGITAL INPUTS ANALOG OUTPUTS

PIN NO. WHEEL SPIN

VOL TAGE DISCRETE

(PIN 13)

X a

X 0

X 0 x 1

X 1

X 0

X X

X - Don I t Ga re

BIT iB :T BIT BIT 16 15 14

1 0 1

1 0 1

1 0 1

0 1 1 a 1 1

0 1 1

X X X

D232~'11262-1

X

PIN NO. TEST RESP. BIT (PIN 30)

10 VOLTAGE VOL TAGE

0 X -.0038+.0373

0 X -.0038+.0373

0 X +9.9998+ .. 0373

0 X I +9,9998::,.0373

0 X -.0038+.0373

0 X 9. 987~. 060 7

X PIN 50 X 14. 85.:!:.. 58%

I

THt' I.',NG ~ANY

5. COMMAND {232-11669}

5.1 Impedance Test. With power off, measure the specified impedance between the points indicated in Table 5.1-1.

5 .. 2 loads. Pri or to pe rfo nni n gel ectri ca 1 tes ts, connect the specifWToads to the pin nl.lrt.ers indicated in Table 5.2-1. Refer to' Figure 3.2-1 for load circuits. '

5.3 Power Requirements. The following voltage and ground inputs are to be applied to the indicated card pin numbers.

POWER INPUTS PIN NO.

+5 ~ 0.25 vee @ 1 Amp Max. 52

+15 ~ 0.05 VDC @ 0.5 ~. Max. 3

-15 ~ 0.05 VDC @ 0.5 Amp. Max. 2

RETURNS

D. GND

A. GND

PIN NO.

28 VOC RTN 5

Connect digital and analog ground together external to the card under test while it is being tested. Connect Thermal Plane (Pin 6) to Analog Ground (Pin 1).

5.4 EMP protection diodes. With power supply voltages OFF, perform the EMP tests by applying a voltage through a resistance to the signals indicated in Table 5 .. ~-1 as shown in Figtlre 3,4-1.'

5.5 Circuit Tests

Burn-in is required during initial fabrication testing, or when F recalibration of either the Normal Acceleration Command or Thhottle Command digital -to-analog converters is necessary_ The purpose ~ ~ burn-in is to insure that each digital-to-analog. converter is stat;:e at the time of calibration. To accomplish burn-in, apply plus-and-minus l5VOC power to the Command Card (using the A.gnd for a return) for a period of not less than fifteen minutes. F

.39 _ . 0232':;11262-1

F co Mlnn 2"S ORI 10, ./71

TABLE 5.1-1 IMPEDANCE TESTS FOR COMMAND

MEASUREMENT POINTS IMPEDANCE

PIN NO. PIN NO. (OHMS) •

'SERIAL DATA 9 SERIAL' DATA 10 <1

DATA SIGNAL 26 DATA SIGNAL TEST 56 <1

DATA COMP 55 DATA CaMP TES:r 25 <1

CI1JEK + GAit 17 CLOCK + WE 18 <1

CLOCK SIGNAL 54 CLOCK SIGNAL TEST 24 <1

CLOCK CaMP 57 CLOCK CaMP TEST 27 <1 GATE SIGNAl 29 GATE SIGNAL TEST 58 <1

GATE COMP 59 GATE COMP TEST 30 <1

AZC 8 FF04E 37 10K + 1%

SIN0c COt+1AND 35 . FF02E 34 10K + 1%

SINe RTN 4 A GND 1 <1

ACTUA10R RTN 15 A GNO 1 <1

THERMAL PLANE 6 A GND 1 )tl00K • ACTUATOR ENABLE 16· . ACTUATOR ENABLE TEST 45 <1 ACTUATOR ENABLE: 16 FFOlS 42 10K + 1%

-15V ACTUATOR 13 -15V ACTUATOR TEST 43 . <1

ACTIVATE

+15V ACTUATOR 14 +15V ACTUATOR TEST 44 <1

ACTIVATE

COS 0 c CO'MMAND 32 FF03E 33 10K + 1%

COS t'c RTN . 31 A GND 1 <1

THROTTlE COI'+1AND 38 FF05C 41 10K + Z% THROITLE ·eHO RTN 12 A GND . 1 <1 ~RonlE ENABLE 411 THROTTLE ENABLE TEST 11 . <1 THRomE ENABLE 40 FF03S 7 10K + 1% lav RTN 5 A GND 1 >100K

O. GND 53 A GND 1 >10K

2av RTN 5 o GNO 53 >lOOK

THERMAL 'PLANE 6 O.GND 53 >100K

THERMAL PLANE 6 28V RTN 5 >100K • 40

TABLE 5.2-1 • SIGNAL PIN NO.

+15V ACTUATOR 14

THROTTLE COftolAHD 38

SERIAL DATA 9

CLOCK + GAIT 17

'trncK + wr 18

~ 20

Kq 49

~ 51

COS "c COItNIND 32

SIN "c COItNlND 35

• -15V ACTUATOR 13

ACTIVATE

SERIAL DATA 10

CLOCK 46

KAZ 47

~I 50

KDI 48

Kr 21

FCSE TEST 23

AZC 8

LOADS FOR COMMAND

RETURN IN NO.

ACTUATOR RTN 15

THROTTL~ CfoI) RTN 12

O. GND 53

D. GND 53

O. GNO 53

D. GND 53

D. GND 53

D. GND 53

COS "c RTN 31

SIN (Ilc RTH 4

ACTUATOR RTN 15

D. GND 53

D. GND 53

D. GHD 53

D. GND 53

D. GND 53

D. GNO 53

D. GND 53

A. GND 1

0232-11262-1

LOAD CIRCUIT

150n 3.» 1

1371tl 0.15 IIf 2

DIGITAl 5

DIGITAL· 3

DIGITAL 3

DIGITAL 4

DIGITAL 4

DIGITAL 4 ,

1700 , 500 nil 9

2700 • 500 nil 9

1500 3.» 1

DIGITAl 5

DIGITAL 3

DIGITAL 4

DIGITAL 4

DIGITAl 4

DIGITAL 4

DIGITAl 4

133K1l 1.0 J.i f 6

TABLE 5.4-1

• SIGNAL

DATA SIGNAL

DATA COMP

CLOCK SIGNAL

CLOCK COMP

GATE SIGNAL

GATE COMP

EMF PROTECTION DIODES

FOR COMMAND

PIN NO. RETURN

26 D. GND

55 ' D. GND

54 D. GND

57 D. GND

29 D. GND

59 D. GND

~~ ~ ~, .~ nTU

0232-11262-1

PIN NO. CIRCUIT I

53 1

53 1

53 1

53 1

53 1

53 1

.n n

Ie

5.5.1 DIGITAl CIRCUITRV

DIGITAL INPUTS

DATA - S1~al

DATA - Cofl1llement Clock - Signal

Clock - Coqll ement Gate - Signal

Gate - Coqllement Digital Ground

DIGITAl OUTPUTS

SERIAL DATA

Clock

ClOc'f + Gate

KeI

KAZ

KOI

Kq

Ke Kp

Kr

FeE Test

Spare

Spare

Spare

COs 'e Sin Sc Throttle

AZ

Oigital Ground

PIN NO.

NA

NA

NA

NA

NA

For digital inputs and outputs refer to Table 5.5'~1-1 • . J

0232 .. '-1262-1

CO 110002'." 01:1.11:. <4/71

TABLE 5.5.1-1 TRUTH TABLE

r-"

ADDRESS¥- ' .. 71 47 48 49 20 50 51 21 23 22 28 NA NA NA NA NA

..., , 2. , Sl6- KAZ KDI Kq ~ ~I Kp Kr FeE ~parE ~aY1! ~an! ~~ ~" .. ~ ~ A~ N-. ITr~T

0 0 " 0 () 0 " 0 0 " " '0 tJ 0 D " tJ 0 0 " • " () 0 , 0 IJ a 0 , 0 0 C) D " 0 0 t!JJ 0 0 t:)

0 0 , 0 0 (J D 0 (J , I (I D t:J 0 a " 0 0 <:::J 0

0 0 , I 0 () 0 D 0 D f 0 0 0 () " rJ (J () (J

0 I 0 (J 0 0 (J () 0 0 0 I () 0 0 0 () " (J " 0 I tI I 0 0 0 t:J 0 0 0 t) D 0 0 D I 0 0 ()

0 , I 0 0 " 0 C) 0 Q 0 tJ " 0 0 (J 0 I 0 ., IJ I J I 0 D 0 D 0 0 D () " " d 0 a 0 I " I D 0 (J 0 a " 0 0 (J 0 0 () tJ 0 0 0 0 0 I

I 0 0 I () I 0 0 0 0 0 " " " (J 0 0 " 0 ,

• I (J I " 0 () 1 0 0 0 0 " " 0 o· a 0 0 " (J

I 0 , I 0 0 0 I (J " (J t::> 0 "- d " 0 0 0 D

I J 0 0 0 tJ 0 " () 0 0 " I 0 0 0 0 0 0 0

I I 0 I 0 D () (J 0 () 0 " ('J I " 0 0 0 0 0

I I I D 0 (J " 0 0 0 0 a () (:) I D () 0 0 C"J

, I I , 0 tJ 0 0 (;) 0 0 0 0 0 0 I " 0 0 0

IJ 0 0 D , D 0 () 0 () 0 0 " 0 () 0 (J a 0 0

D IJ 0 I I X >( X 0 x- x X x X )( X X )( x x.

D 0 , 0 I X X )( X 0 x )l x )( x. X- X )( X X.

D 0 , I I )( X X " X 0 X X x X x X X. )( x.

0 J 0 0 1 X X X X X x. 0 X )(. X. X x -x )(. )C.

• 0 I 0 I I X l( x X. x ~ x x )(' x x. 0 x X )(

0 , , (J I ~ )( >C X X x. X )( X X )( >' 0 x X

~4 D232-11262.;.1

TABLE 5.5.1-1 (Cant'd.) /

A.D •• SS ., ~TE 47' 48 49 20 SO 51 21 f& 22 28 HA NA NA NA NA _I KAZ KDI Kq "s ktI -I) Kr ~ri!' ~i'l ~ SJ~ 'rfIwHj t. Az .. J .. , () , I I , l( )( X )C. J( )( X X X X )( X " 0 J(

, D (J ." I X X X X X X X X X )( )t X X X 0

I D D I 1 0 )( J( )( X ~ X .J( " J(. X X '>\ x. J(

, () I 0 J )( 0 X X X. X X X X X X X X )( l(

I t> I I I X X 0 oX J( " )( X K J( X X X X J(

I I D f) r )( X X X X oK X 0 X X X X X X .)(

, I D , I X X X X X )( X X 0 X X X J( X )(

I I , " r " X X X X X X X X D X )( X X J(

, , J , I J( X )(. J( X aX X X X oX. a )( X X .J(

*Address Data per Figure 5.5;1-1"') X ~ 00 not need to check' . • o = 0.0 to 0.45 VDC 1 = 2.4 to 5.0 VDC

DATA CLOCK GATE OUTPUTS

I

SIGNAL COMP SIGNAl. COHP SIGNAL- COMP DATA CLOCK GATE ~-~U"'1'i. "'tIA 11 PINHO. PIN NO. PIN NO. PIN NO. PIN NO. PIN NO,. PIN NO. PIN NO PIN NO. PIN NO. 26 55 54 57 29 59 9 46 NA 17

0 I " , Ct , " 0 0 I

0 r () I , 0 ., Q I I

0 I I 0 0 I 0 , 0 , " 1 , 0 , 0 0 I I 0

I , 0

I f 0 0 J 0 (J

I tJ 0 I , 0 , 0 , f • , 0 I 0 D , J J 0 , I 0 , 0 • 0 I , I 0 4:>

FeE Serial Digital Data - Word Format

16 I 15 14 13 \12 11 10 9 8 7 6 5 4 3

HSB LSB SI~ I~ ,--=-v---' .. """--v-

DATA ADDRESS

~ SPARE

TIMING FOR THIS OATA IS DEFINEO IN FIGURE 1.5.1-2

ADDRESS

4 3 2 1

0 a 0 0

0 Q 0 1

0 Q 1 Q

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 a 0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 '1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

NOMENCLATURE

NOT USED

K0 - . Roll Gain

K0I - Roll Integral Gain

Kp - Roll Rate Gain

Kr - Yaw Rate Gain

COS 0c - Cosine Roll Command

SIN 0e - Sine Roll Command

. STC - Throttle Corrrnand

Aze - Acceleration Command

KA~ - Acceleration Error Gain

Kor - Acceleration Integral

Kq - Pitch Rate Gain

- FCE Test

SPARE

FIGURE 5.5.1-1 - ADDRESS DATA

0232-11262-1

Gain

TIME

2 1

BIT

NUMBER

,T1

CLOC~I'\

SIGNAL

GATE

GATE

COMP

DATA SIGNAL

DATA CO"".

II ~

11 r-

I 1 2 I 3 91 12

13 114 (15 1 16 I

I 1 2 I 3 ., 12 113 I 14 115 116

T2 Lags Tl ."

T4 Lags T3

II 111 = 2 to 5 'VOC

"0" - a to .8 VDC

Do tests using the digital input levels of Genera 1 Note 1. Sheet 7.

5 The printed circuit c~rd shifts data on the "III to 110" transition of the clock signal.

FIGURE 5.5.1-2 DIGITAL TIMING

0232-T1262-1

11111

110"

11111

"0" 111" "011

"111

"0 11

5.5.2 NORMAL ACCELERATION COMMAND (Aze)

DIGITAL INPUTS

Data Signal:

Data Complement:

Clock Signal:

Clock Complement:

Gate Si gnal :

Gate Complement:

Di gi ta 1 Ground

ANALOG OUTPUT

Acceleration Command (AZC)

Analog Ground

PIN NO.

I

See Table 5.5.2-1 for test performance requirements and digital data inputs.

If the test is a part of initial fabrication and the voltage for the A all "ones" Logic Input is out of tolerance, calibration is required to obtain 10.000 '0.030 volts at the output. If the test is a retest init.iated by a failure at a higher level test (e.g., FCSE PRVT or FAT)..~ calibration is only required if the output, is not within the retest tolerance (± .076 volts) for the all "ones" LOGIC INPUT condition. To calibrate, short any combination of the resistors R251 through R256 to obtain 10.000 ± 0.030 volts at the output (refer to Figure 5.5.2-1). For clock data and gate inputs refer to Figure 5.5.1~2.

Measurement accuracy required on calibration step is ± .02% of reading error maximum plus ± 2.0 mVdc bias error maximum.

CC !fOOO 21<4'5 C 1"41 Q •• '7'

0232-11262-1

A

A

TABLE 5.5.2-1

TEST PERFORHANCE REQUIREMENTS FOR NORMAl. ACCELERATION OAC

I LOGIC INPUTS , ANALOG

~_ i I I INPUTS p;"'~iI5 1413 12 11 10 I 9 8 ~

1 1 1 1 1

1 1 0 0 0 1 0 100

~ ~ ~ b ~ 1 0 0 '0 0

1000 10 o o o o o o o

1 0 0 ~ r 0

Ibto~~ 0 1 I ~ r u 0 o o o o o o o o a o o o o o o o o o o o

1 1 1 o 0 0 o 0 0 o 0 1

NONE

o 0 O. 0 0 0 0 0 o 000 0 000 o a a NONE o 0 0 0 0 0 0 0 o 1 a o 0 0 0 0 000 1 0 0 OOOlDr 001 a a 0 0000POI0 a 0 0 O,,~uu 10

0p~OI 0 a 00~10 00

0r1p~ 00 OlrOp 00 0111 r 1 1 o 0 0 0 o a 0 0 o a 0 0 o 0 0 a 000 0

1 1 1 1

MEASUREMENT ACCURACY REQUIREMENTS:

ANALOG OUTPUT (VOLTS)

TYPICAl

10.000**

5.0049

2.5024

1.2512

0.6256

Q.3128

0.1564

0.0782

0.0391

0.0196

0.0098

0.0000

-0.0000

-0.0098

-0.0196

-0.0391

-0.0782

-0.1564

-0.3128

-0.6256

-1.2512

-2.5024

-5.0049

10.0000**

MAXIMUM MINIMUM

10.030

5.0434

2.5287

1.2734

0.6465

0.3334

0.1769 0.0987

0.0596

0.0401

0.0303

0.0173

0.0173

0.0107

0.0009

-0.0186

-0.0577

-0.1358

-0.2920

-0.6040

-1.2266

-2.4685

-4.9471

-9.8853

9.9700

4.9664

2.4761

1. 2290

0.6047

0.2922

0.1358 0.0577

0.0186

-0.0009

-0.0107

-0.0173

-0.0173

-0.0303

-0.0401

-0.0596

-{) .0987

-0.1770

-0.3336

-0.6472

-1.2758

-2.5363

-5.0627

-10.1147

RANGE BIAS ERROR SCALE FACTOR ERROR

0< V <.1 . .C~ V < 1.

1. < V<20

+ .02 mVdc +" .02 mVdc ~2.0 mVdc

• **Check ripple voltage ~ (25 mVnns maximum)

+ .02% +" .02% ~ .02%

49 .

D232-11262-1

FIGURE 5.5.2-1 RESISTOR LADDER - CALIBRATION

RESISTOR NORWIL

ACCELERATION

154 316 634

DAC-OS 17 ., •• 0

J RA R2S1 "!fA .. ~

RB 1;: RB R252

S.UK 2 .5~;K RC R253

·RF

., ~ • RO R254

15 RE RO

RE R255

1'61.9K RF R255

RS RG R257

13 I--

Using printed circuit "pads" locate,d on the card short out the resistors to provide the specified output voltage for the condition specified. Shorting out the resistor will 9ive you the corresponding approximate voltage increase •

RESISTOR

RA " 154 ohms

RB ~ 316 ohms

Re 2 634 ohms flO " 1. 27 K ohms

RE : 2.55 K ohms flF: 5.11 It ohms

All

VOL TAG'!:

30 mV

50 mY

120 mV

240 mY

480 mY

960 mV

1890 mY

0232-11262-1

THROmE

R262

R263

R264

R265

R206

R267

R26B

5.5.3 THROTTlE COMMAND

ANAlOG INPUTS

Throttle Enable:

28 VDC Return:

or GITAl INPUTS

Data S1 gIlal:

Data COlfCllement

Clock Signal

Clock Complement:

Gate S1 gnal :

Gate Complement

ANALOG OUTPUT

Throttle Command:

Th rottl e Return:

PIN NO.

See Table 5.5.3-1 for test performance requirements and digital data inputs. If the test is a part of initial fabrication and the voltage for the al1"~ones" LOGIC INPUT is out tolerance, calibration is re quired to obtain 10.150 ± 0.030 volts at the output. If th~ test is a retest initiated by a failure at a higher level test (e.g., FCSE. PRVT or FAT). calibration is only required·if·the output is not" within the retest tolerances (± .076 volts) for the all "ones" LOGIC INPUT condition. To calibrate short any combination of the resistors R262 A through R268 to obtain -10.150,± O.J~O_volts at the output when +14 volts DC is provided to the tHrottle enable and all bits except the sign bit are high (refer to Figure 5.5.2-1). For clock data and gate inputs refer to Figure 5.5.1-2.

Measurement accuracy required for the above calibration step is ± .01% of reading error maximum plus ± 2.0 mVdc bias error maximum .

. ,51 0232,.11262-1

A

TABLE 5.5.3-1 TEST REQUIREMENTS FOR THROTTLE OAC

LOGIC INPUTS ANALOG INPUT ANALOG OUTPUT (VOLTS) (VOL TS)

Z]",,:Bi«1 15 114 11312 It 110 I 9 18 jBi" THROTTLE TYPICAL ! MAXIMUM tr; ::E:r-;' I i !-I I ENABLE i

- - - - - - - - - - - a + 1 voe 0.000 0.100

1 1 1 1 1 1 1 1 1 1 1 14.0 .:!: 0.5 VDC 10.150** 10.2663

1 1 0 0 0 0 0 0 a a a 5.0800 5.1387

1 a 1 0 a 0 a 0 0 0 0 2.5400 2.5744

1 a a 1 0 0 0 a 0 0 0 1. 2700 1. 2949

1 0 a 0 1 0 0 0 0 0 a 0.6350 0.6568

1 a 0 a a 1 0 0 0 a 0 0.3175 0.3385

1 0 0 0 0 0 1 0 0 0 0 0.1588 0.1796

1 0 0 a 0 0 a 1 0 0 0 0.0794 0.1001

1 0 a 0 0 0 0 0 1 0 0 0.0397 0.060a

1 0 a 0 0 a a a a 1 a 0.0198 0.0405

1 a 0 a 0 a 0 a a a 1 0.0099 0.0306

1 0 a 0 0 a a a 0 0 0 0.0000 +0.0175 a 0 a 0 0 0 0 0 0 a 0 0.0000 +0.0175

0 a a a a a 0 a 0 0 1 -0.0099 0.0108 a 0 0 0 0 a 0 a a 1 0 -0.0198 0.0009

0 0 a 0 a 0 0 a 1 0 a -0.0397 -0.0190

0 0 a 0 0 0 a 1 0 0 a -0.0794 -0.0587 a a 0 0 0 a 1 a 0 a a -0.1588 -0.1381 o . a a 0 0 1 a 0 0 0 0 -0.3175 -0.2967

0 a a 0 1 0 0 0 a 0 0 -0.6350 -0.6139 a 0 0 1 a a a a a a 0 -1.2700 -1.2476

0 0 1 a 0 a 0 a 0 a a -2.5400 -2.5134

0 1 0 0 0 a 0 0 0 0 0 -5.0800 -5.0409

0 1 1 1 1 1 1 1 1 1 1 -10.1500** -10.120

I

Measurement accuracy requirements: Same as gi ven in Table 5.5.2.

**Check ripple voltage ~ (25 mVrms maximum). D232-11262-1

MINIMUM

-0. lOG

10.0337

5.0213 2.5056

1. 2451

0.6132

0.2965

0.1380

0.0587

0.0190

-0.0009

-0 .0108

-0.0175

-0.0175

-0. 0306

-0.0405

-0.0604

-0.1001

-0.1795

-0.3383

-0.6561

-1.2923

-2.5666

-5.1191

-lD.180

5.5.4 Cosine Roll Command (Cos9c)

ANALOG INPUTS PIN NO.

Reference: 400 Hz Phase Input 36

Reference Return: Analog Ground 1

DIGITAL INPUTS [[;>

Data Signal

Da ta COfllJ 1 emen t Clock Signal

Clock C~~lement

Gate Signal Ga te Camp 1 ernen t

Digital Ground:

ANALOG OUTPUT

Output Signal: Cos0c Command

Analog Ground: Cosec Return 31 fD. Digital inputs and- timing is defined- in F~.gure 5.5.1-:~~

TEST PROCEDURE

1. DC Tests:

Setup 11400 Hz Phase Input" ~ + 10.000 'VDC, then for each serial data word in Table 5.5.4-1: measure the IlCosl&'c Col11l1ilnd u o!Jtput (VDC) and check against the follOWing computed test limits:

MAX cosec Output = (MAX DC GAIN) (Measured "400 Hz Phase Input") +

+ (MAX DC OFFSET)

MIN Coslc Output = (MIN DC GAIN) (Measured "400 Hz Phase Input U )-+

+ (MIN DC OFFSET)

where MAX and MIN DC GAIN are given in Table 5.5.4~I*and (MAX DC OFFSET) ~ +.001 VDC and

(MIN DC OFFSET) ~ -.007 VDC.

* Use Table 5.5.4-1(a) for 232-11669-1,2, or 3.

Use Table 5.5.4-1(b) for 232-11669-4. 5.

co eooo :1:1 .. " QRIG. "'7.

D232-11262 .. 1-.

5.5.4 Cosine Roll Command (Cos~c) (Continued)

TEST PROCEDURE (Continued)

2. AC Tests:

Setup "400 Hz Phase Input" = 10. VRMS @ 400 Hz, then for each serial data word in Table 5.5.4-2:lreasure the fiCas ~c Corr.mand" output (VRMS and phase) and check 'against the following computed test 1 imits:

MAX COS0c OUTPUT = (MAX AC GAIN) (Measured "400 Hz Phase Input")

MIN COS0c OUTPUT = (MIN AC GAIN) (Measured "400 Hz Phase Input'!)

where MAX and MIN AC GAIN are given in Table 5.5.4-2~

MEASUREMENT ACCURACY REQUIREMENTS

1. DC Signals: VDC

1. < V < 20. - i. .. 02% of reading, ~ .002 Vdc bias

.1 < V <1..,,-..., ~*02%ofreading,:::. .0002 Vdc bias

V <.1 ~ :. .02% of reading, ~ .00002 Vdc bias

2. AC Signals: VRMS

1. < V < 20 • .-....; + .080 VRMS bi as

3. AC Phase Shift

1. <: V ,< 20 ................ 2:. 3 DEGREES

* Use Table 5.5.4-2{a} for 232-11669-1,2, and 3.

U,e Table 5.5.4-2(b) for 232-11669-4, 5, 6.

00 !lOOO :<. "'11 ORI Gi. "'7'

0232-1l262-1

A

A

... Tf.E~E 5.5 .. ~-1(a) Cosd C

' Sin~c DC Gain for 232-11669-1,2, 3

SERIAL DATA WORD I" DC GAIN (VDe/VDe) CD ~~13121110Im TYPICAl MAXIMUM MINIMUM

111 1 111 1 1 .. 703177 [D .709328 .694626 .

1 0 0 0 0 a 0 0 0 0 1 ..35362 .355098 .351902 0 1 0 0 0 0 0 0 0 0 1 .. 17661 .177576 .175404 fo- 0 1 0 0 0 0 0 0 0 1 .088019 .088684 .. 087114 0 0 1 0 0 0 0 0 0- 1- -- .043809 .. 044343 .043035

0 0 0 0 1 0 0 0 °t!f .021705 .022174 .020996 0 0 0 0 0 1 0 0 o ~ .010652 .011091 .009973 0 0 0 0 0 0 1 0 0 0 1 .0051265 .005543 .004470 0 0 0 0 0 0 0 1 0 0 1 .0023629 .002771 .001715 0 0 0 0 0 0 0 1 0 1 .0009815 .001386 .000337 -- 0 0 0 0 0 0 0 0 0 1 1 .000291 .000694 -.000352 0 0 0 0 0 0 0 0 0 0 1 .000000 .000000 .000000

0 0 0 0 O' 0 0 0 0 .000000 .000000 .000000

0 0 0 0 0 0 0 0 0 1 0 -.001091 -.Ouuo~ -.001734 --- 0 0 0 o. 0 a a a 1 0 0 -.0017814 -.001376 -.002427 0 0 0 0 0 0 0 1 0 0 0 -.0031628 -.002740 -.003826 0 0 0 0 0 0 1 0 0 0 0 -.0059263 -.005504 -.006588 0 '0 (i 0 0 1 0 0 0 0 0 -.0114518 -.011004 -.012139 0 0 0 0 1 0 0 0 0 0 0 -.0225037 -.022014 -.023233 0 O. 0 1 ~ 0 0 0 o 0 0 -.0445073 -.044032 -.045422 0 0 1 0 0 0 0 0 ~ ~ ~ -.088815 -.088067 -.089803

~o 0 0 0 0 0 0 ~ ~ -.177402 -. 176276 -.178768 . 0 0 0 a 0 (] to ~o -.354404 -.352595 -.356453

1 1 1 1 1 1 1 1 1 1 P -.711144 [D -.704332 -.720356

IZ> Q ed r ippl ~ v >It ~ge (2 ~ m inn , DBx1J11J11

I"f"'. 6a1 tol' D232-11262-1 L.:...I'" n erance incl udes tenllS accounting for rreasUreJ1'ent errors in the 55 reasured input and output i~ addition to circuit Slain tolerances • .

If.,;::''~ 5.5.~-1 (b) COsd

' Sin~c DC Gain for 232-11669-4, 5, 6 A • SERIAL DATA WORD ,- f DC GA.IN (VDC/VDC) ED I t:::J\.O 15 14113112111110 9 8 ~t-~ TYPICAL 1 PAXIMUM MINIHUM ~-

I U')

1 1 1 1 1 1 1 1 1 1 1 · 7071773 [I) .710073 .7042809 .' ----1 0 0 0 0 a 0 0 0 0 1 .354204 .3554716 .3525692 ,-- -- -- ,-,- --- -----

0 1 0 0 0 0 0 -, 0 0 0 1 . 1770102 .1777562 .1762642 -- ---0 0 1 0 0 0 0 0 0 0 1 .0884188 .0887783 .0880592 -- -- - -

0 0 0 1 0 0 0 0 0 d· r - .0442094 .0443900 .0440288 0 0 0 0 1 0 0 0 .0221047 -

0 0 1 .0221966 .0220127 '-0 0 0 0 0 1 0 0 0 0 1 .Oll0523 .0111015 .011 0032

0 0 0 0 0 0 1 0 0 0 1 .0055262 .0055562 .0054961 0 0 0 0 0 0 0 1 0 0 1 .0027631 .0027860 .0027402 0 0 0 0 0 0 0 0

1 0 1 ' .0013815 .0014023 .0013608

0 0 a 0 a 0 a 0 0 1 I .0006908 .0007110 .0006706

-0 0 0 0 0 0 a 0 0 0 1 0 0 0

• 0 0 0 a a a a 0 0 0 0 0 0 0 , --0 0 0 0 0 0 0 0 0 1 0 -.0006908 -.0006707 -.0007109 _.

0 0 0 o _ 0 0 0 0 1 0 0 -.0013815' -.0013611 -.0014020., ' -- 0 0 0 0 0 0 0 1

0 0 0 -.0027631 -.0027414 -.0027848

0 0 a 0 0 0 1 0 0 0 0 -.0055262 -.0055001 -.0055523 -0 '0 b' D 0 1 0 0 0 0 0 "".0110523 -.0110133 .0110914 , r--- 0 0 0 0 1 0 0 0 0 a 0 -.0221047 -.0220346 -.0221748

-a o . 0 1 0.. 0 0 0 0 0 0 -.0442094 -.0440736 -.0443452 1-- -- - -- - - 0 0 1 0 0 0 0 0 0 0 0 -.0884188 -.0881494 ,-'.0886881

'-0 1 0 0 0 0 0 0 0 0 0 1- .177Q102 - .1764364 -. 1775839 .

---, 1 0 0 0 a 0 0 0 0 0 P --.3540204 -.3529264 -.3551143 -- I 1 1 1 1 1 1 -.7071773 [D -.7049950 -.7093596 1 ! 1 0

:(0 I iC~ ripp l~ vpl t~ge (2;l m 'hTI rraximum

3 -11262 ... 1 ~. 022 & Gain tole!"ance lncludes te~ ac~ounting for ~asurerrent errors in the 55.1 measured ,nput and output l~ 2dd~tion to circuit gain tolerances. A

• MSB

Hi

TABLE 5.5.4-2 (a) Cos~ s Sinl AC GAIN for 232-11669-1,2, and 3 c c

DATA OUTPUT AC GAIN (VRMS/VRMS) u:> PHASE

TYPIC~ I ~IJ~" TOLERANCE

w\XIMUM MINIP4JM 14 13 12 11 10 9 8 1 6 (DEGREESl

1 1 1 1 1 1 1 1 1 o + 3 .707177 .. 715201 .. 699153

1 1 1 1 1 1 1 1 0 180 + 3 .707144 .715337 a 698950

Gain tolerance includes terms accounting for measurenent errors in the measured input and output in add1tion to circuit tolerancesa

D232-11262~1

• MSB

TABLE 5.5.4-2{b} Cos~ 11 Sin0 AG GAIN for 232-11669-4, 5., 6 c c

DATA OUTPUT

PHASE

AC GAIN (VRMS/VRMS) lD

14 13 12 11 10 9 8 1 ~IGN 6

TDlEAANCE

TYPICAL MAXIMUM (DEGREES)

1 1 1 1 1 1 1 1 1 0+3 .797·1773 I .. 716996 I

1 1 1 1 1 1 1 1 0 180 + 3 7 . I I .70 1773 I .717148 I

Gain tolerance incl udes terms accounting for measurement errors in the measured input and output in addition to circuit tolerances .

56. 1 0232-11262-1

A

MININUM

.697358

.697206

A

5.5.5 Sine Roll Command (Sin 'e)

ANALOG INPUTS

Reference: 400 Hz Phase Input

Reference Return: Analog Ground

DIGITAL INPUTS u::> Data Signal Data C0l'l1l1emnt Clock.