SOW.pdf

STATEMENT OF WORK

Title: Design service for Memory Device Characterization Board

Lab: Physical Measurements Lab (CHIPS R&D metrology program GCPN 6.05)

BACKGROUND INFORMATION

The National Institute of Standards and Technology (NIST), Physical Measurements Laboratory (PML), Nanoscale Device Characterization Division (NDCD), Alternative Computing Group (ACG), requires board design, fabrication, and assembly service for memory characterization platform. This is an FPGA-based board design service with a custom memory array chip along with ADCs, DACs, and other active and passive components to establish a communication/control interface between the FPGA and the memory array. Researchers and industries with custom memory devices will use this board as a standalone benchtop platform to characterize their memory devices and measure various metrics.

The board developed through this service will be used as a memory characterization platform along with a suite of benchmarking applications to characterize memory devices at an industrial scale.

PURPOSE

NIST requires board design service for characterizing memory devices. This board will be used to characterize and evaluate custom analog memory devices developed by researchers and industry. Benchmarking applications, tools and metrics will be developed and tested on this board with various memory devices.

MINIMUM REQUIREMENTS

The Contractor shall provide design services as set forth in this Statement of Work.

All line items shall be shipped in the original manufacturer’s packaging and include all original documentation and software, when applicable.

Line Item 0001:

Description: Field Programmable Gate Array-based memory characterization board to characterize custom analog memory devices Quantity: 10

1. Board design and fabrication service for a Field Programmable Gate Array (FPGA) based test platform with custom memory device array chip, multi-channel ADCs, and DACs.

1.1 Schematic Design Capabilities

Develop schematics for the next-generation FPGA-based test platform (Daffodil) with a custom memory array chip. This platform will include a Zynq System on Module (SOM) from Avnet. The SOM will be a daughter card-type module to the Daffodil main board with a custom memory device array chip, ADCs, and DACs.

The Avnet SOM daughter card will contain a Zynq Ultrascale+ FPGA, DDR3 memory module, SD controller, USB controller, and ethernet modules connected to the main card through a 3 JX3 connector.

The schematic design can be implemented with any commercially available design tool. However, Altium is preferred as the original project, and the schematics for the daughter card are available in Altium format.

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1.2 Layout Capabilities

Layout and route the design from the generated schematics, considering factors such as size, heat dissipation, and signal integrity. Choose the appropriate trace width and clearance based on the signal and component operating frequency.

Create a solid ground plane to reduce noise and improve signal integrity. In general, follow standard best practices and design guidelines from the component vendors.

1.3 Signal Integrity Analysis Capabilities

This capability is preferred but not absolutely required. Even though the current design may not have any signals over 100Mhz, it is preferred that the designer perform signal integrity analysis to identify crosstalk, reflections, and impedance mismatches in the design. This will ensure that the design is future-proofed when migrating to high-speed components. The designers can use any commercially available integrity analysis tool.

1.4 Fabrication and Assembly Capabilities:

Board fabrication is to be done with FR4 or FR408HR material and should be compatible with the SOM daughter card. A rigid-flex or rigid-type board with

Class II inspection is required. Main components like the SOM and the memory chip mounting socket required for assembly will be provided as part of the contract. The service provider can purchase the remaining components, such as

ADCs, DACs, connectors, and any other active/passive components.

I. SCHEDULE OF DELIVERABLES

Deliverable Number Description Quantity Due Date

Place of Delivery

1 Schematics deliverables with all associated files

1 5 weeks NIST Gaithersburg

2 Layout deliverables with all associated files

1 4 weeks NIST Gaithersburg

3 Output from signal integrity analysis (if any)

1 2 weeks NIST Gaithersburg

4 Fabricated, assembled, and tested board with test results

10 5 weeks NIST Gaithersburg

Standards of Acceptance: The NIST COR with input from the TPOC shall review all the above deliverables and respond with an acceptance or request for revision email to the Contractor's Point of Contact (POC) within 3 weeks of receipt of the deliverable. This section applies to deliverables that must be reviewed and approved for acceptance (e.g., draft plans, drawings, etc.)

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PLACE OF PERFORMANCE

Contractor Site

PERIOD OF PERFORMANCE

12-16 Weeks from date of an award

PERFORMANCE STANDARD

A bi-weekly meeting to update the status of development will be required.

A Clear written report stating the results and tests for each deliverable discussed in the table above will be required.

DELIVERY TERMS

Delivery shall be F.O.B Destination (or equivalent incoterms, such as DDP) and shall occur in accordance with the delivery due dates provided in the table above.

FOB Destination means: The contractor shall pack and mark the shipment in conformance with carrier requirements, deliver the shipment in good order and condition to the point of delivery specified in the purchase order, be responsible for any loss of and/or damage to the goods occurring before receipt and acceptance of the shipment by the consignee at the delivery point specified in the purchase order; and pay all charges to the specified point of delivery.

Soft deliverables shall be delivered to NIST through a secure file-sharing system provided by NIST.

Hard deliverables shall be mailed to NIST to the address below:

The contractor shall deliver all Line Items to:

National Institute of Standards and Technology

Shipping and Receiving

100 Bureau Drive, Building 301

Gaithersburg, MD 20899

Attn: TPOC (TBD)

INSPECTION & ACCEPTANCE

In addition to the inspection and acceptance terms articulated in the specific FAR clause that allows the Government reserves the right to perform such performance tests and evaluations as defined below to verify specified system performance. Such tests and evaluations, if performed, shall be conducted within the environment that the system is to be operated. The Contractor has the right to be present during the tests and evaluations, if performed, at the Contractor’s expense.

Performance Tests:

1. Continuity test.

2. The board bring up test

3. Power sequence test

4. FPGA programming and program retention test

5. Power levels and noise level test.

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6. Throughput test between SOM and the memory device array

NIST may choose at its discretion to forego this part of acceptance testing.

A visual inspection of the equipment will be performed by the NIST TPOC to identify surface defects or any form of indication that any equipment was damaged during transport to NIST. The Government shall have sole discretion to require repair or replacement of damaged and/or nonconforming supplies at no cost to the Government. The Government at any time prior to acceptance shall reject the equipment due to defects and/or nonconformance. The vendor is responsible for latent defects discovered any time after final inspection. However, the extent of its liability shall be prorated over the useful life of the equipment.

Ownership of the equipment shall transfer to NIST upon acceptance by the Government.

The Government will test, inspect, and accept or reject the deliverables within 3 weeks of receipt unless otherwise indicated above. The Government reserves the right to conduct quality assurance testing to confirm that a given instrument(s) meets the manufacturer’s and/or the Government’s performance specifications.

WARRANTY

The contractor shall warranty the entire system for a period of a minimum of 1 year after receipt of the equipment. Warranty shall commence upon acceptance of the system by the Government.

PAYMENT SCHEDULE

Payment shall be made upon receipt of a proper invoice, completion of deliverables and upon completion of testing and acceptance as set forth herein, by the COR.

Payment terms shall be net 30.

CYBERSECURITY PRIVACY REQUIREMENTS

NIST requires a solution that provides security and privacy protection consistent with requirements defined by applicable federal laws, regulations, policies, and standards

(e.g., the Federal Information Security Management Act (FISMA), OMB Circular A-130, and FIPS Publication 200). The solution provider (including subcontractors) may meet these requirements through various means, including but not limited to FedRAMP authorization, current third-party assessments (e.g., SSAE, PCI), and/or responses to

NIST special publication control set SP 800-171.

Minimally Acceptable Controls

• System security plan describing physical, technical, and administrative controls implemented to protect systems and sensitive personally identifiable information (SPII).

• IT management processes to establish and manage secure configuration baselines including routine patching for all operating systems and applications.

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• Access to SPII is restricted to those with a need to know. Personnel with access to SPII have background investigations performed (e.g. criminal, financial etc.), and are trained on secure handling of SPII.

• Access Controls for SPII meet or exceed industry best practices for access and identification control including, but not limited to, connectivity to servers and databases, multi-factor authentication for remote accesses for administration, secure configurations for any devices accessing the system, and strong physical security for any place where the data is accessed.

• The solution supports multifactor authentication for users and/or supports integration with customer federation services for Single-Sign capability.

• Processes for scanning on a continual basis for vulnerabilities and proper configurations for all aspects of the system, as well as processes for timely mitigation of findings.

• Auditing and Incident Response processes including customer notification of suspected or actual incidents and logging with sufficient information to perform forensics on any incident. Processes for notifying and providing appropriate mitigations, including but not limited to credit monitoring services, for subsidy applicants in the event of suspected or actual incidents.

• SPII is encrypted in transit using TLS 1.2 or better and encrypted at rest in all places the SPII is stored. All encryption algorithms and modules are FIPS 140- 2/140-3 validated.

If unable to meet any of the requirements listed above, the Contractor may provide details of mitigations or alternative protections in place to ensure the appropriate handling and protection of SPII.

If the Contractor provides services to other Federal agencies, provide a general description of the security risk management approach and client point of contact.