AMENDMENT IV.docx
DOCX document 23 KB Posted
- Solicitation number
- 1333ND25QNB030052
About this file
This document is an Amendment (Amendment 0004) for a federal contract opportunity related to FPGA-based board design services issued by the National Institute of Standards and Technology (NIST). The amendment addresses several technical specifications and requirements for a memory device characterization board, including specific details about semiconductor components and design expectations.
Key technical requirements include finding alternative DAC and ADC components with parallel programming capabilities for 75 DAC and 25 ADC channels, maintaining the resolution of existing prototype components (ADS7950SBDBT and AD5391BSTZ-5). NIST mandates signal integrity simulation for the motherboard PCB and requires functional verification testing. The technical point of contact will be actively involved in reviewing every design phase, with an emphasis on early collaboration through an acceptance test plan review and sign-off process. The solicitation (Number: 1333ND25QNB030052) seeks a custom-designed product with specific technical specifications for board design services.
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Other files
| File | Type | Posted |
|---|---|---|
| AMENDMENT III.docx | DOCX document | |
| AMENDMENT II.docx | DOCX document | |
| SOW.pdf | ||
| 1333ND25QNB030052.docx | DOCX document |
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Text version
AMENDMENT 0004
Question: What is the acceptable SOM/SBC Selection:
Answer: NIST shall provide the SOM. Here is the SOM of choice https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/ultrazed/ultrazed-eg/
Question: What is the required ADC & DAC specifications for this application?
Answer: NIST currently has a prototype board with ADS7950SBDBT and AD5391BSTZ-5. NIST has about 5 DACs and 7 ADCs to provide 75 DAC channels and 25 ADC channels. However, these channels can only be programmed serially. NIST is looking for DACs and ADCs that can program and read 25 channels parallel. They must have the same resolution as the device mentioned above but with parallel programming capabilities.
Question: Is there a need for signal integrity simulations for the Carrier/Motherboard PCB?
Answer: Signal integrity simulation is a requirement for the Motherboard board PCB.
Question: Will functional verification testing be sufficient for the custom-designed product, or are additional validation steps required?
Answer: Functional verification testing shall be sufficient.
Question: Would the user be open to reviewing and signing off on an ‘acceptance test plan’ early in the design cycle to ensure alignment with the agreed specifications?
Answer: Absolutely, the technical point of contact shall be involved in reviewing every phase of the design.
File details come from the government source that posted it. Updated .