Minitherms3D_Proposers_Day_Slides.pdf

Miniature Thermal Management Systems for Three-Dimensional Heterogeneous Integration (Minitherms3D) Proposer’s Day

Mark Rosker, MTO Director

Briefing prepared for Minitherms3D Proposer’s Day

27 January 2023

Approved For Public Release; Distribution Unlimited

C4ISR: Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance PNT: Positioning, Navigation, and Timing

Disruptive Microsystems

Directed Energy Electronic WarfareC4ISR PNT

Microsystems ManufactureLocal Processing Spectrum Dominance

High-performance, intelligent microsystems and next-generation components

Microsystems Manufacture: Key challenges

Realizing heterogeneous 3D electronics

Optimizing design and test for complex circuits and prototypes

Overcoming security threats across the entire hardware lifecycle

2D electronic interconnects limit throughput, functionality, miniaturization, and efficiency

Increasingly complex circuits and assembly stretch the limits of current design, packaging, and test capabilities

Persistent hardware threats limit the ability to access and utilize advanced electronics technology

Developing electronics for extreme environments

Electronics performance and reliability are limited by extreme temperature, voltage, current, and radiation

Source: Adobe Stock

2D: Two Dimensional 3D: Three Dimensional Approved For Public Release; Distribution Unlimited

Electronics Resurgence Initiative (ERI) 2.0 plan

Original ERI funding ERI 2.0 Baseline

ERI 2.0 Enhancement

FY27FY26FY25FY24FY23FY22

Overcoming security threats across the entire hardware lifecycle

Optimizing design and test for complex circuits and prototypes

Securing communications

Realizing heterogeneous 3D electronics

Accelerating innovation in artificial intelligence hardware to make decisions at the edge faster

Increasing information processing density and efficiency

Manufacturing complex 3D microsystems

Developing electronics for extreme environmentsNGMM

NGMM: Next-Generation Microelectronics Manufacturing program

Maintain research base

Create national capability New research focus

Source: Advanced Technology Services, Inc.

Source: Adobe Stock

Source: Adobe StockSource: Adobe Stock

Today

Heterogeneous Integration (Minitherms3D) program

Currently, 3D integration is limited by thermal access to each layer and heat exchanger performance

Minitherms3D will develop thermal management technologies to enable multi-tier 3D microsystems

3D: Three Dimensional www.darpa.mil

Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D)

HR001123S0019

Proposers Day January 27, 2023

Brian D. Nuckols Contracting Officer

DARPA Contracts Management Office

Distribution Statement A. Approved for Public Release; Distribution Unlimited.

Proposers Day Disclaimer

A copious amount of information is made available to potential proposers to clarify program goals/objectives and proposal preparation instructions.

However:

• Only the information/instructions in the BAA counts

• Proposals will only be evaluated in accordance with the instructions provided in the BAA

• Any response provided by the Government in the FAQ that’s different than what is provided in the BAA will be made formal by an amendment to the BAA

• Such responses will make note of an impending BAA amendment

Only a duly authorized Contracting Officer may obligate the Government

BAA Overview

Described in Federal Acquisition Regulation Part 35:

– For the acquisition of basic and applied research

– FAR 35.016 (a): Shall only be used when “meaningful proposals with varying technical/scientific approaches can be reasonably anticipated.”

– BAAs allow for a variety of technical solutions

– The BAA defines the problem set, the proposer defines the solution (and SOW)

DARPA Scientific Review Process

– Proposals are evaluated on individual merit and relevance as it relates to the stated research goals/objectives rather than against one another

– Selections will be made to proposers whose proposals are determined to be most advantageous to the Government, all factors considered, including potential contributions to research program and availability of funding

Government may select for negotiation all, some, one, or none of the proposals received Government may accept proposals in their entirety or select only portions thereof Government may elect to establish portions of proposal as options

BAA Overview, Cont’d

Multiple Awards Anticipated (~$69M total)

Multiple award instrument types:

– Procurement contract

– Other Transaction

– Grant

– Cooperative Agreement

Phase 1 (Base Period)

– Hot spot mitigation approaches for a stack of 3 equally-powered tiers with total thermal dissipation of 4 kW, while establishing approaches for thermal isolation and large tierwise heat removal

– 18 months

Phase 2 (Option Period)

– Demonstrate the thermal management of a stack of 5 equally-powered tiers, with total dissipation of 6.8 kW, along with targets for thermal isolation, inside the stack thermal resistance reduction, as well as reduction in the thermal link resistance to the ambient heat rejection component

– 18 months Phase 3 (Option Period)

– Demonstrate the overall system level thermal resistance and volumetric heat rejection targets in a simulated application environment

– 12 months 10

BAA Process/Timeline

1. BAA published: January 23,2023

2. Proposers Day: January 27, 2023

3. Abstracts Due: February 22, 2023

4. FAQ Submission Deadline: March 27, 2023

5. Proposals Due: April 11, 2023

7. Proposals are checked for BAA compliance

Non-conforming proposals are not reviewed (and cannot be selected)

8. Government conducts Scientific Review Process

Clarification requests may be sent to various proposers

8. Contracts negotiated & awarded (performance start): October 2023

(can assume Oct 2023 for Pricing)

See BAA for complete date/time information Monitor SAM.gov for any BAA amendment(s)

Eligibility Issues

All interested/qualified sources may respond subject to the parameters outlined in

BAA

Foreign participants/resources may participate to the extent allowed by applicable Security Regulations, Export Control Laws, Non-Disclosure Agreements, etc.

FFRDCs and Government entities:

- Are not prohibited by the BAA from proposing

- Are, however, subject to applicable direct competition limitations

- Are, however, required to demonstrate eligibility (sponsor letter)

The burden to prove eligibility for all such team members rests with the proposer

All elements of a proposal (tech and cost, prime and subs – even FFRDC team members) must be included in the prime’s submission

Real and/or Perceived Conflicts of Interest:

- Identify any conflict/s

- If any are identified, a mitigation plan must be included

Abstracts (1 of 2)

Abstracts are strongly encouraged:

1. They minimize unnecessary effort in proposal preparation and review

2. They reduce the potential expense of preparing an out of scope proposal

The abstract provides a synopsis of the proposed project (tech and budget)

Government will reply by letter with one of two possible responses:

1. Encourage full proposal, and may provide feedback

2. Discourage full proposal, and will provide feedback

DARPA will not communicate further (verbally or in writing)

Regardless of DARPA’s response to an abstract, proposers may submit a full proposal

DARPA will review all full proposals submitted without regard to abstract recommendation/feedback

Distribution Statement A. Approved for Public Release; Distribution Unlimited. 14

Abstracts must include the following components:

• Cover Sheet

• Innovative Claims

• Technical Approach

• Deliverables

• Cost and Schedule

Submit UNCLASS submissions to the DARPA BAA Website (https://baa.darpa.mil) per the instructions in Section IV.C.2, “Abstract Submission Information,” of the BAA.

Abstracts (2 of 2)

Max of 5 pages

The total page limit does not include the cover sheet (required) or a submission letter (optional) https://baa.darpa.mil/

Full Proposal Ground Rules

KEY POINTS:

Two Technical Challenges: TC1 and TC2 Both technical challenges must be addressed in the proposal

All three Phases must be proposed (Base and two priced Options)

An organization/company/individual can be on multiple proposals

Submit unclassified proposals ONLY to the DARPA BAA Website (https://baa.darpa.mil)

Click “Finalize Full Proposal” button (otherwise you have not submitted)

Do not submit classified proposals/information to the DARPA BAA Website

If unsure, please follow the instructions in the BAA for inquiring

Propose to the program (goals, objectives, metrics, schedule, deliverables) the BAA has defined, not to the program you desire https://baa.darpa.mil/

Volume 1: Technical/Management Proposal

– Be mindful of the page limitations (20 pages)

– Be sure to respond to all 12 of the required “Detailed Proposal Information” items

• Technical Approach – is the centerpiece of the technical proposal

• Statement of Work – Organize by Phase/Option, then by Tasks. Define all tasks (what you are doing, not how you are doing it) and deliverables (data, software, and material items, as applicable).

– Pay attention to key technical elements in the “Funding Opportunity Description” that must be addressed in all proposals

Volume 2: Cost Proposal

– No page limitations

– DARPA Standard Cost Proposal Spreadsheet (required for contracts/OTs)

– Fully detailed cost build-ups/estimates (Prime & Subcontractors)(All instrument types)

• Summary Cost Build-up: By phase and performer fiscal year

• Detailed Cost Build-up: By phase, technical task, and month

– Subcontractor proposals are required (to include SOW)

– No Rough Order of Magnitudes (ROMs)

– Certificate of Current Cost/Pricing Data will be required for any procurement contract award meeting the prescribed threshold (i.e., the adequate price competition exemption does not apply to BAAs)

Full Proposal Preparation

Volume 2: Cost Proposal

– DARPA Standard Cost Proposal Spreadsheet The Government requires that proposers* use the provided MS Excel DARPA Standard Cost Proposal Spreadsheet in the development of their cost proposals. A customized cost proposal spreadsheet may be an attachment to this solicitation. If not, the spreadsheet can be found on the DARPA website at http://www.darpa.mil/work-with-us/contract-management (under “Resources” on the right-hand side of the webpage). All tabs and tables in the cost proposal spreadsheet should be developed in an editable format with calculation formulas intact to allow traceability of the cost proposal. This cost proposal spreadsheet should be used by the prime organization and all subcontractors. In addition to using the cost proposal spreadsheet, the cost proposal still must include all other items required in this announcement that are not covered by the editable spreadsheet. Subcontractor cost proposal spreadsheets may be submitted directly to the Government by the proposed subcontractor via e-mail to the address in Part I of this solicitation. Using the provided cost proposal spreadsheet will assist the Government in a rapid analysis of your proposed costs and, if your proposal is selected for a potential award, speed up the negotiation and award execution process.

*University proposers requesting a grant, cooperative agreement, or Other Transaction for Research do not need to use the MS ExcelTM DARPA Standard Cost Proposal Spreadsheet. Instead, a proposed budget and justification may be provided using the SF-424 Research & Related Budget forms provided via https://www.grants.gov.

Use the single TA spreadsheet Do not make changes that are specifically prohibited by the instructions Questions are welcomed. Please direct them to costproposal@darpa.mil

Full Proposal Preparation, cont’d

Associate Contractor Agreement

(ACA)

The success of Minitherms3D depends in part upon the open exchange of information between performers

All performer awards will include a clause requiring that performer to enter into an ACA with all other performers under the program

Performers will collaborate closely throughout the program, at a minimum:

– Maintenance of a close liaison and working relationship;

– Maintenance of a free and open information network with all Government identified Associate Contractors;

– Delineation of detailed interface responsibilities;

– Entering into a written agreement with the other Associate Contractors setting forth the substance and procedures relating to the foregoing, and promptly providing the Agreements Officer/Procuring Contracting Officer with a copy of same; and,

– Receipt of proprietary information from the Associate Contractor and transmittal of Contractor proprietary information to the Associate Contractors subject to any applicable proprietary information exchange agreements between associate contractors when, in either case, those actions are necessary for the performance of either. 18

Data Rights

Government desires as few restrictions as possible

If asserting less than Unlimited Rights (e.g., Restrictions):

– Provide and justify basis of assertions using the prescribed format

– Explain how each item will be used to support the proposed research project

– Explain how the Government will be able to reach its program goals (including technology transition)

The proposer (prime) must submit a Data Rights Cert covering the entire team (prime and subcontractors), as applicable Provide a Data Rights Cert no matter the instrument type being proposed This information is assessed during evaluations (barriers to transition)

Non-Conforming Proposal Determinations

Failure to submit proposal on time – non-conforming!

– Proposal due date and BAA closing date are the same – so, late is late!

Failure to submit using the correct mechanism – non-conforming!

– Unclassified proposals ONLY to DARPA BAA website

– Classified proposals/information ONLY per “Security Information” section of the BAA

Failure to submit both proposal volumes – non-conforming!

– OT proposals must also include a full cost volume (Cost Realism is an evaluation criterion for all proposals)

– OT proposals must also include a detailed list of payment milestones (Milestone Plan)

Pages beyond the page limitation (tech prop) – additional pages will not be reviewed

ROM/s instead of full subcontract cost proposal/s – non-conforming!

– “I didn’t have time to get the subcontract proposal(s)” will not change the outcome

– “My subcontractor/s would not give me a proposal” will not change the outcome

Missing FFRDC or Government Entity cost proposal – non-conforming!

Communications

Prior to Receipt of Proposals (Solicitation Phase): Follow instructions in

BAA

Typically handled through the FAQ, but see BAA exceptions (e.g., security)

After Receipt of Proposals/Prior to Selections (Scientific Review Phase):

Limited to Contracting Officer or BAA Coordinator (with approval) to address clarifications requested by the review team Proposal cannot be changed in response to clarification requests

After Selection/Prior to Award (Negotiation Phase): Negotiations are conducted by the Contracting Officer PM and/or COR typically tasked with finalizing the SOW (with PI) PM and/or COR typically involved in any technical discussions (i.e., partial selection discussions) Pre-award costs will not be reimbursed unless a pre-award cost agreement is negotiated prior to award

Informal Feedback Sessions (Post Selection): May be requested/provided once the selection(s) are made

– If made on a timely basis (~2 wks after letter), all requests will be accepted

Referenced Links http://www.darpa.mil/work-with-us/contract-management#SolicitationContracting (General DARPA contract management information) (DARPA Standard Cost Proposal Spreadsheet) http://www.darpa.mil/work-with-us/additional-baa (general BAA info pertaining to all instrument types) http://www.darpa.mil/work-with-us/procurementcontracts (info pertaining to contracts) https://acquisitioninnovation.darpa.mil/ (info pertaining to OTs) http://www.darpa.mil/work-with-us/reps-certs (DARPA-specific reps and certs for all instrument types) (Note August 2020 version of 52.204-24)(Similar is required for OTs as well)

Distribution Statement A. Approved for Public Release; Distribution Unlimited.

http://www.darpa.mil/work-with-us/contract-management#SolicitationContracting http://www.darpa.mil/work-with-us/additional-baa http://www.darpa.mil/work-with-us/procurementcontracts https://acquisitioninnovation.darpa.mil/ http://www.darpa.mil/work-with-us/reps-certs

3D Heterogeneous Integration (3DHI) and DARPA Dr. Thomas Kazior

Program Manager, MTO

Minitherms3D Proposer’s Day

January 27. 2023

December 16, 2020 Higher Levels of Integration is Key Enabler for Improving System Performance and SWAP-C…..

…. but can we get the heat out?

3DHI

Distribution Statement A – Approved for Public Release, Distribution Unlimited

Source: DARPA

Outline

Heterogeneous Integration Evolution Millimeter Wave Arrays (ELGAR - Electronics for G-band Arrays) Device Level Heterogeneous Integration (H2 – Heterogeneous Heterostructures) Device Level Thermal Management (THREADS - Technologies for Heat Removal in

Electronics at the Device Scale) Summary

Distribution Statement A – Approved for Public Release, Distribution Unlimited

Heterogeneous Integration Evolution

DAHI (2.5D)

Today – Monolithic Tomorrow – Modular

CHIPS (2.5D) 3DHI

Distribution Statement A – Approved for Public Release, Distribution Unlimited

Source: DARPA

Source: Teledyne, DARPA DAHI Source: DARPA CHIPS BAA

Source: DARPA

3D Heterogeneous Integration Provides a Path to Enhanced

Performance, Increased Functional Density, Lower Size and Cost

‘Modular’ stacking of heterogeneous technologies/functions allows tailoring for different applications

DAHI (3D)

Can it be Manufactured

OSD SHIP (2.5D)

Distribution Statement A – Approved for Public Release, Distribution Unlimited

Source: OSD SHIP RFS

NGMM (3D)

(Next Generation Microelectronics Manufacturing)

3DHI assembly design kit

Manufacturing process

National facility

3DHI R&D and low-volume manufacturing

Source: SUSS

Source: Adobe Stock

National facility

3DHI R&D and low-volume manufacturing

Sustainable, quantifiably assured SOTA advanced packaging for DoD and defense industrial base

NGMM: 3DHI pilot line fed by research portfolio to address gaps

R&D for Advanced Manufacturing 3D Electronic Design

Automation Design for Test in

3DHI

Electrical and Thermal Codesign 3D Security Awareness

Virtual Prototyping

Additive Manufacturing

High Density Interconnects

3D Thermal Management

Automated Chip Handling Automated Inspection

Representative ERI 2.0 research topics

3DHI: 3-dimensional heterogeneous integration ERI: Electronics Resurgence Initiative

Source: Mobius Connect

Impact: Millimeter Wave Arrays - Multichip modules to 3DHI

‘Modular’ stacking of heterogeneous technologies/functions allows tailoring of transceiver for different applications

Source: DARPA

3D Integration Provides a Path to Enhanced Performance, Increased Functional Density, Lower Size and Cost; Key Enabler at Millimeter Wave Frequencies

28Distribution Statement A – Approved for Public Release, Distribution Unlimited

Traditional Multi-chip Module

Source: Kazior, IEEE 2016 International Microwave Symposium Workshop MG, Heterogeneous integration of Silicon RFIC with III-V

JUMP: ComSenTer

JUMP: Pre-competitive University Research Funded by DARPA and Industry

Moderate-Power 140 GHz 2D Arrays

Gabriel Rebeiz, UCSD

High-Power 100-300GHz 2D Arrays: How?

29Distribution Statement A – Approved for Public Release, Distribution Unlimited

Source: Mark Rodwell, JUMP ComSenTer

New Program: ELectronics for G-band ARrays (ELGAR)

30Distribution Statement A – Approved for Public Release, Distribution Unlimited

UWBG Materials: Options for getting the heat out

Parameter Unit GaN on SiC AlN β-Ga2O3 Diamond c-BN Electron Mobility 103 cm2/V·s <1 0.43 0.15 4.5 0.83

Vpeak 107 cm/s 2.5 1.3 1.1 1.9 TBD EBK 105 V/cm 40 154 103 175 150 Eg eV 3.4 6.0 4.9 5.5 6.4 κ W/cm·K 2.9 3.19 0.27 22.90 9.40

Substrate Diameter inch 6 2 4 1 N/A

P-type dopability Good Poor No Good TBD

N-type dopability Good Moderate Good Moderate TBD

Superior material properties

Bandgap structure? Thermal properties? Dopant limitations?

~90 K

Temperature dependence of properties?

A. Parisini, R. Fornari, "Analysis of the scattering mechanisms controlling electron mobility in β-Ga2O3 crystals," Semiconductor Science and Technology 2016, 31, 035023.

β-Ga2O3

1 2 3 4 5 6 7 0x

1x

2x

3x

4x

5x

GaN

AlN

Ga2O3 c-BN

Diamond

GaAs

SiC

Si

N or m al iz ed

B re ak do w n

St re ng th

(G aN

Bandgap Energy (eV)

Bubble Area ∝ Thermal Conductivity

Many UWBG Materials exhibit high thermal conductivity ... but how do we integrate them?

Source: NRL/MIT-LL

Tsao, J. Y. et al., “Ultrawide‐Bandgap Semiconductors: Research Opportunities and Challenges,” in Adv. Electron. Mater. 2018, 4, 1600501.

Distribution Statement A – Approved for Public Release, Distribution Unlimited 31

Heterogeneous Junctions

Device Level Heterogeneous Integration Heterogeneous Heterostructures (H2) program

Publication date: 4/6/2021, Deadline date: 5/7/2021 https://beta.sam.gov/opp/5d1d985b0de04fb39fdfc723f3cc0552/view

Source: DARPA

Problem: Device structures with “ideal” combination of electrical and thermal material properties required for next generation high performance devices do not exist

Approach: Graft (bond) dissimilar materials to create novel heterojunctions that capitalize on unique properties of individual layers

Phase 1: Develop new processes to form low defect density heterogeneous heterojunctions

Phase 2: Design novel heterogeneous heterostructures guided by accurate physics-based modeling and simulation

Technologies for Heat Removal in Electronics at the Device Scale

(THREADS)

The THREADS program aims to overcome thermal limitations and achieve robust transistors operating near the electronic limit of RF output power

DARPA

Past DARPA Program: NJTT (Near Junction Thermal Transport)

Adopted from “Thermal Management of Active Electronically Scanned

Arrays”, by John D.

Albrecht, David H. Altman, Avram Bar-Cohen, and Joseph J. Maurer, 2013

IEEE International Symposium of Phase Array Systems and Technology.

3X increase in power density achieved

Past DARPA Program: ICECool

Adopted from “Near Junction Microfluidic

Cooling for Wide Bandgap Devices”, Bar-Cohen, Maurer, Sivananthan, MRS 2015.

1000 W/mm2 thermal dissipation achieved

THREADS Technical Challenges Overview

Achieving high output power and safe operating temperature requires reduced thermal resistance both within and outside of the device

1/RTotal = 1/Rwithin + 1/Routside

Transistor Thermal Resistance Routside device

Rwithin device

Parallel Thermal Resistance

Model

Channel Buffer

Waste Heat

Intrinsic: Within the active device (Rwithin)

Extrinsic: Outside of the device (Routside)

DARPA

THREADS Objective

PA = Power amplifier Pour = RF output power

GaN = Gallium nitride

*Measured continuous wave (CW) at X-band (8 – 12 GHz) ** Equates to a Median Time to Failure (MTTF) > 106 hour

Efficient AlGaN/GaN HEMT Power Amplifiers, IEEE 2008

The THREADS program aims to develop technologies to overcome the thermal limits and realize robust transistors that operate near their electronic limit of RF output power

DARPA

Specific Goals* o Performance o Pout= 81 W/mm o Transistor thermal Resistance: 8X reduction o Robustness o Channel temperature: < 225 °C** o Final program demonstration o Robust high power density transistor and PA

Summary/Conclusions

Future communications and sensor systems require higher BW, higher data rates and cost and energy effective solutions to meet mission requirements: driving need for:

• Higher functional density - Integration of a diverse set of materials, devices and functions

Chip-scale, wafers-scale and device-scale 3D Heterogeneous Integration solutions are emerging

• Heterogeneous Heterostructures

• Si-like processing of non-Si devices/components/functions

• Integral thermal solutions

Distribution Statement A – Approved for Public Release, Distribution Unlimited 38

39Distribution Statement A – Approved for Public Release, Distribution Unlimited

Heterogeneous Integration (Minitherms3D)

January 27, 2023

Yogendra Joshi Program Manager, MTO

Proposer’s Day Presentation

Thermal management technologies to enable multi-tier 3D microsystems

Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)

What does 3D mean?

Vertical stacking of active chipsActive chips connected through a passive interposer layer

Package interconnect pitch ~ 125 µm

Traditional 2.5D Interposer 3D

Memory

Logic

Mixed signal

Printed circuit board

Interconnect pitch shrinks 4x

Flip chip and wire bonds on printed circuit board

Interconnect pitch shrinks 10x-100x

Silicon interposer Active chip on active chip

(e.g. memory stacked on logic)

Bond or bump

What is 3DHI?

Source: https://imgflip.com/memegenerator/Inigo-Montoya

3DHI: 3-dimensional heterogeneous integration

Heterogeneous Integration

44Distribution Statement A – Approved for Public Release, Distribution Unlimited

Extending Moore’s law and broadening our impact Pe rfo rm an ce

, N um be r o f T ra ns ist or s

1990 2000 2010 2020 20301980

1st Wave Geometric

Scaling

• DUV lithography

2nd Wave BEOL Scaling

• Low-κ/Cu interconnects

• Bus width scaling

3rd Wave 3D Devices

• FinFETs

• High-κ dielectric

• Strain engineering

• Multi-core architectures

Intel 486

4th Wave Heterogeneous Integration

• Alternative materials

• Domain-specific functions

• 3D architectures

Slide courtesy Mark Rosker, DARPA/MTO

Materials Devices Function

Heterogeneously integrated electronics – emerging opportunities Process

My definition of 3DHI heterogeneous integration of different material systems in the same chip/package

III-V, II-VI

(GaAs, InP, HgCdTe)

Wide bandgap (GaN, SiC)

Ultrawide bandgap (AlGaN, Diamond)

Laser, LED, Detector

HEMT, MESFET,

JFET

Photonics, RF

Photonics, RF, Power

Em er gi ng

O pp or tu ni tie s

HEMT, MESFET,

JFET

Photonics, Power

Bump, µ-Bump, TSV, Hybrid

Bump, µ-Bump, TSV, Hybrid

Bump, µ-Bump, TSV, Hybrid

Tr ad iti on al F oc us Silicon MOSFET, FinFET, GAAFET

Logic, Memory

Silicon germanium Bi-CMOS, HBTs

Analog, Mixed- Signal, RF

Bump, µ-Bump, TSV, Hybrid

Bump, µ-Bump, TSV, Hybrid

Integration in a three-dimensional (3D) tiered stack of:

• Different circuits (processing, memory, analog/RF)

• Materials (Si, compound semiconductor)

What is 3D heterogeneous integration?

Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)

2.5D and 3D Heterogeneous Integration, F. Sheikh, R. Nagisetty, T. Karnik, and D. Kehlet, IEEE Solid-State Circuits Magazine, 85, Fall 2021

Example concept of 3D heterogeneous integration of RF, analog, mixed-signal, and digital circuits

• High-power die stacking is limited to 2.5D integration to allow heat transfer through top and bottom of assembly

High-power 3D integration is limited by thermal access to each layer & heat exchanger performance

50 mm x 50 mm base; 5 CFM

280W 119 mm x 79 mm x 65 mm 450g; 2U server 11,000 rpm fan https://www.dynatron.co/product-page/a35

Hung et al., IEEE ECTC, 2021 Simons, Electronics Cooling, 2003

Current state-of-the-art (SOA) - 2.5D thermal management

TC1 TC2

Technical Challenge 1 (TC1) – Reducing thermal resistance within the stack. 3D integration leaves one or more interior layers without direct thermal access to the heat rejection component

Technical Challenge 2 (TC2) – Reducing thermal resistance external to stack. Heat exchangers in bulk material (e.g., Aluminum) limited by surface area to volume, and air convection

SoA: State-of-the-Art

Minitherms3D Goal:

Compact thermal management to enable a scalable number of high power tiers

Simulation assumptions:

Material: Silicon Tier size: 3 cm x 3 cm x 0.7 mm Heat flux: 150 W/cm2

Heat transfer coeff. top: 50,000 W/m2K Heat transfer coeff. Bottom: 100 W/m2K Ambient temperature: 20 oC

End of program demo:

• 3D stacking of five high power tiers

• Total heat dissipation > 6.8 kW (>7X SoA)

• Heat rejection system < 0.006 m3 (<2X SoA)

Technical challenges

TC2a: Reducing link thermal resistance from the stack surface to the heat rejection component (10 cm – 1 m)

TC1b: Increasing thermal isolation between adjacent functional blocks (1 µm- 1 mm)

TC1c: Increasing heat removal from each tier while maintaining low thermal resistance (1 cm – 3 cm)

TC1: Reducing thermal resistance within the 3D stack

TC2: Reducing thermal resistance outside the 3D stack

TC1a: Increasing in-tier heat transfer without increasing tier thickness (1 µm-100 µm)

TC2b: Increasing volumetric heat rejection while reducing heat rejection resistance to air (10 cm – 30 cm)

49Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)

TC1a:

Increasing in-tier heat transfer without increasing tier thickness

• Electrical-thermal co-design

• Need CMOS compatible tier integration

Hot spotTier Hot spot size 0.1mm

0.2mm

0.5mm

Additional assumptions:

Material: Silicon Tier size: 3 cm x 3 cm Hot spot power: 1 W Heat transfer coefficient: 100 W/m2K Ambient temperature: 20 oC

SOA: In-plane thermal conductivity = 150 W/m-K Goal: In-plane thermal conductivity = 2,000 W/mK

Minitherms3D

Increasing transistor integration

• Thinner tiers: improved electrical performance

• Thicker tiers: improved thermal performance

TC1b:

Increasing thermal isolation between adjacent functional blocks

Current approaches such as vacuum gaps are not scalable, and interposers result in poor isolation

Logic Memory

In-plane thermal isolation

Out-of-plane thermal isolation

Current out-of-plane isolation approaches with ball grid array interconnects and underfill result in significant thermal coupling

Goal: Thermal conductivity ratio 0.0002 for in-plane and out-of-plane

SOA: Thermal conductivity ratio 0.01 for in-plane and out-of-plane

Logic

Memory

TC1c:

Reducing the lateral thermal resistance of each tier

Simulation assumptions:

Material: Silicon Number of tiers: 2-5 Die size: 3 cm x 3 cm Maximum tier temperature: 100 oC Heat flux: 150 W/cm2

Heat transfer coeff. (top): 50,000 W/m2K Heat transfer coeff. (bottom): 5 W/m2K Ambient temperature: 20 oC

SOA: 1 kW for top tier heat removal Goal: Five-tier stack with total 6.8 kW

Single tier SOA

TC2a:

External thermal resistance - stack to rejection component link

• Multiple interfaces outside stack bottleneck in heat removal

• Negating thermal resistance reduction inside the stack

SOA: 30 oC/kW Goal: 1 oC/kW

Thermal link

TC2b:

Increasing volumetric heat rejection capability to air

SOA

Minitherms3D

2U/3U VPX/VITA Enclosure

SOA: Volumetric heat rejection capability = 500 kW/m3 Goal: Volumetric heat rejection capability >1,100 kW/m3 https://info.boydcorp.com/hubfs/Thermal/Two-Phase-Cooling/Boyd-3D-Vapor-Chamber-MACE-Technical-Datasheet.pdf https://www.vadatech.com/product.php?product=588&catid_now=0&catid_prev=0

He at

R ej ec tio n Vo lu m e (x

-3 m 3 )

TC Metric SOA Phase 1 Phase 2 Phase 3

1a Hot spot heat flux(a) (W/cm2) 200 2,000 2,000 2,000

1b Thermal isolation(b) 0.01 0.0007 0.0002 0.0002

1c Specific internal thermal resistance(c) (cm2 oC/W) 0.3 0.18 0.09 0.09

2a Stack-to-sink thermal resistance(d) (oC/kW) 30 10 1 1

2b Heat sink volumetric capability(e) (kW/m3) 500 700 1000 1130

2b Heat sink thermal resistance(f) (oC/kW) 20 15 6.6 5.7

(a) Maximum hot spot size 2 mm x 2 mm; Si tier size 1 cm x 1 cm – 3 cm x 3 cm with background heat flux of 150 W/cm2;

solution must allow electrical interconnect density 4x107/mm3

(b) Applies to both in-plane isolation and out-of-plane isolation

(c) Maximum value within 3D Si stack, based on reference temperature of 20 oC

(d) Based on temperature difference between maximum stack surface temperature and maximum heat sink base temperature

(e) Defined as ratio of the heat rejection capability to the volume of the heatsink

(f) Based on temperature difference between maximum heat sink base temperature and ambient temperature

Program metrics

Phase 3 (12 months)Phase 2 (18 months)Phase 1 (18 months)

Program structure and schedule

Kickoff

BAA

Oct ‘23

Jan ‘23

CY 2022

FY 2027FY 2023 FY 2024 FY 2025 FY 2026

CY 2023 CY 2024 CY 2027CY 2025 CY 2026

Technical Challenges TC1: Reducing thermal resistance within the 3D stack

TC2: Reducing thermal resistance external to the 3D stack

Phase 1 Demonstrate underlying technologies at lower stack power

• 4 kW, three-tier stack

• Rejection technologies development

Phase 3 Progress to transition

• 6.8 kW, five-tier thermal system at the edge

• Demo under realistic thermal environment

Phase 2 Performance enhancement of stack interior and exterior thermal technologies

• 6.8 kW, five-tier stack system

• Laboratory demo

IV&V Testing Multi-scale, multi-disciplinary simulation/design tools

FY 2028

Three-tier stack demo

Five-tier stack demo

Integrated thermal modeling demo

System demo

56Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)

Milestones

Phase Milestone Date 1 Inside the stack thermal management approach design review Q1FY24

Hot spot target completion for three-tier stack Q4FY24 Three-tier stack thermal management modeling and experimental demonstration review

Q2FY25

2 Thermal isolation metric completion Q4FY25 Thermal link metric completion Q2FY26 Five-tier stack thermal management modeling and experimental demonstration review

Q4FY26

3 Initial demonstration of integrated thermal management approach Q2FY27 Integrated thermal modeling demonstration Q3FY27 Final demonstration of integrated thermal management approach Q1FY28

• BAA Posting: Friday, January 23

• Abstracts Due: Wednesday, February 22, max 5 technical pages

• FAQ Closing: Monday, March 27, send all emails to HR001123S0019@darpa.mil

• Proposals Due: Tuesday, April 11, max 20 technical pages

Timeline mailto:HR001123S0019@darpa.mil

1. Overall Scientific and Technical Merit

2. Potential Contribution and Relevance to the DARPA Mission

3. Cost and Schedule Realism

Evaluation Criteria – In Order of Importance

60Distribution Statement “A” (Approved for Public Release, Distribution Unlimited)