DARPA_Minitherms3D_ProposersDay_MITLL_20230127_b.pdf

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Attached to: Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration (Minitherms3D) Federal contract opportunity
Solicitation number: HR001123S0019
Issued by: Defense Advanced Research Projects Agency

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Minitherms3D_FAQ_04102023_Updated.pdf	PDF	Apr 11, 2023
Minitherms3D_FAQ_03162023_Updated.pdf	PDF	Mar 20, 2023
Eden_and_Fab_Slides_Minitherms3d.pdf	PDF	Mar 6, 2023
DARPA_MiniTherms_-_SNL.pdf	PDF	Mar 1, 2023
Minitherms3D_FAQ_Final.docx	DOCX document	Feb 17, 2023
Proposers_Day_Attendees_Contact_List.pdf	PDF	Feb 3, 2023
Minitherms3D_Proposers_Day_Slides.pdf	PDF	Feb 3, 2023
HR001123S0019.pdf	PDF	Jan 23, 2023
HR001123S0019_Attachment_5_DARPA_Standard_Cost_Proposal_Spreadsheet.xlsx	XLSX spreadsheet	Jan 23, 2023
HR001123S0019_Attachment_4_OT_Certs_Template.docx	DOCX document	Jan 23, 2023
HR001123S0019_Attachment_1_Cost_Volume_Proposer_Checklist.pdf	PDF	Jan 23, 2023
HR001123S0019_Attachment_3_General_MTO_Controlled_Unclassified_Information_Guide__CUIG_.pdf	PDF	Jan 23, 2023
HR001123S0019_Attachment_2_Proposal_Summary_Chart.pptx	PPTX presentation	Jan 23, 2023

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Delivered to the U.S. Government with Unlimited Rights, as defined in DFARS Part 252.227-7013 or 7014 (Feb 2014). Notwithstanding any copyright notice, U.S.

Government rights in this work are defined by DFARS 252.227-7013 or DFARS 252.227-7014 as detailed above. Use of this work other than as specifically authorized by the U.S. Government may violate any copyrights that exist in this work.

This material is based upon work supported by the Department of the Air Force under Air Force Contract No. FA8702-15-D-0001. Any opinions, findings, conclusions or recommendations expressed in this material are those of the author(s) and do not necessarily reflect the views of the Department of the Air Force.

Donna Yost DARPA Miniature Integrated Thermal Management Systems for 3D

Heterogeneous Integration (Minitherms3D) Proposer’s Day

27 Jan 2023

MIT LL Fabrication and Heterogeneous-Integration Capabilities

Minitherms 3D Proposer’s Day slides - p2 DRW Yost, M Smith, & CK Chen 27 Jan 2023

Microelectronics Facilities at MIT-LL

Microelectronics Laboratory

Back-end Processing CleanroomElectronic Packaging FacilityIII-V OMVPE Growth

III-V Fabrication Cleanroom

“The mission of MIT Lincoln Laboratory is to carry out a program of research and development pertinent to National defense with particular emphasis on advanced electronics.”

Minitherms 3D Proposer’s Day slides - p3

• Overview of Fabrication and Packaging at MIT LL

• Test Article Capabilities

• Partnering with MIT LL

Outline

Minitherms 3D Proposer’s Day slides - p4

Lincoln Microelectronics Laboratory (ISO-9001, DoD Category-1A Trust Certified)

• 70k ft2, 8100 ft2 Class-10, 10,000 ft2 Class-100

• Production-class sub-90-nm toolset on 200-mm-diameter wafers

• 24 x 5 three-shift operation

Process Capabilities

• Gigapixel Charge-Coupled-Device (CCD) Imagers

(Vis/NIR, UV, X-ray)

• Avalanche Photodiode (APD) Imaging Technology

• 90-nm Fully-Depleted Si-on-Insulator (FDSOI)

CMOS for Extreme Environments

• Nb-Based Superconducting Circuits

• Silicon and Silicon-Nitride Integrated Photonics

• GaN-on-Silicon RF Technology Development

• Micro-Mechanical Sensors (MEMS) and

Microfluidics

• Device research (Diamond, sub-10-nm)

• 3-D circuit integration technology

The US Government’s most advanced captive Si-based research and advanced prototyping facility

CCD and APD Imagers

GaN-on-Silicon (CMOS Compatible)

Radiation Hardened

CMOS

Integrated Photonics

Minitherms 3D Proposer’s Day slides - p5

3D Integration Capabilities at MIT-LL

Pitch 1 mm 100 µm 10 µm 1 µm

Density 1 / mm2 100 / mm2 10,000 / mm2 1,000,000 / mm2 re-Imagine CMOS FPGA Fabric

Flexible, Smart Imaging Arrays

Integrated Photonics and Lasers

Wafer-Scale Systems Quantum Devices

GaN Phased Array Radar

Multi-Chip Modules

Wafer-scale Hybrid Interconnect

2.8 µm pitch

Interposers with Superconducting

TSVs

30µm pitch 10µm pitch

Fine-pitch µBump bond

MEMS and Microfluidics

Full-Wafer TSVs (Through Si Vias)

250 µm

Wafer Align And Bond

200 mm wafers

Minitherms 3D Proposer’s Day slides - p6

Parameter TSV 725 µm depth TSV 500 µm depth

MCM size 48mmX48mm 200 mm wafer

48mmX48mm 200 mm wafer

TSV diameter 200µm 150µm

80µm

150µm 80µm 50µm

TSV metal Cu plate Cu plate

TSV Pitch 400µm 300µm 200µm

300µm 200µm 100µm µBump In In, Sn, Cu, Sn-Ag

In In, Sn, Cu, Sn-Ag

3D integration for Qubit system packaging

Lincoln Advanced Multi-Chip Module (MCM) Packaging Solutions with TSVs

Available In Development Future Development

300µm

MIT LL Three-Tier Stack

1 mm

Minitherms 3D Proposer’s Day slides - p7

MEMS and Microfluidics

Parameter Current Capability

Transport Media Liquids Gases

Actuation Methods (hydraulics)

Electowetting Surface tension Gas pressure

Surface Engineering

Hydrophobic Hydrophilic Textured

Materials Si Polyimide, SU-8

Length Scales Sizes (material dependent)

100’s µm 100’s nm <10’s nm

Features Cavities, Channels

Available In Development Future Development Linear Motion Rotational Motion / Pumps

Electrowetting Microhydraulics

Grayscale Features and Surface Engineering

Quartz

Deep Si Etched Microfluidics

1 mm 1 mm

1 mm

Walsh, Malouin, Browne et al., IEEE Trans. (2019) Kedzierski, Chea, Nature (2021)

Minitherms 3D Proposer’s Day slides - p8

Multi-Chip Bonding and Micro-Bumping

Parameter Current Advanced I-Line 248-nm

Nominal MCM size 48mmX48mm 48mmX48mm 20mmX20mm

Lithography I-line I-line 248-nm

Line width 0.8 µm 0.8 µm 0.35 µm µBumping Full wafer Full wafer Full wafer µBump In, Sn, Sn-In, Au, Au-Sn

Au, Au-Sn Cu

Au, Au-Sn Cu, Sn-Ag

Pitch 25µm (12µm bump) 10µm (5µm bump) 5µm (1.5µm bump)

Stitched MCM 96mmX96mm 96mmX96mm 88mmX88mm

Stitched Litho I-line I-line I-line and 248-nm

200-mm Wafer MCM Litho feature

LDI: 3.5µm LDI+ I-line:0.8µm

LDI: 2µm LDI+ I-line:0.8µm

LDI: 1µm 248nm :0.35µm

Available In Development Future Development

Wafer-Scale MCM

10µm pitch

Das et al., IEEE ECTC (2020) Das et al., IEEE ECTC (2019)

Minitherms 3D Proposer’s Day slides - p9

Interposers with Through Silicon Vias

Parameter Current Advanced I-Line

Interposer size 20mmX20mm 48 mmX48 mm

TSV depth 200µm 200µm

Line width 3µm 1µm

TSV size 10µm X 24µm 10µm X 24µm

TSV metal TiN Cu

TSV Pitch 70µm 70µm

TSV litho I-line I-line µBump In In, Sn, Cu, Sn-Ag

10 µm

TSV interposer

Available In Development Future Development

Yost, Schwartz, Mallek, et al., npj Quantum Information (2020) Mallek, Yost, et al., arXiv (2021) µm

Minitherms 3D Proposer’s Day slides - p10

Tier2 Wafer

Wafer Alignment and Oxide Bonding Capability

Parameter Current Capability

Wafer size 200 mm W2W-alignment capabilities across 200-mm wafer < 0.25 µm

W2W-alignment typical < 1 µm

Alignment method IR microscope real-time feedback to 6-axis piezoelectric stage

Pressure < 5 psi Pressure zones (top and bottom wafer chucks) 4 zones

Temperature for Van-der-Waals bond Ambient

Recommended post-bond oven anneal for covalent bond

175ºC for 3 hours

Available In Development Future Development

Vector Map of Wafer Misalignment Across 200-mm Wafers x-Mean/3Sigma(um): -0.216 / 0.946 y-Mean/3Sigma(um): -0.200 / 0.791

1 µm Oxide Bonding at Room Temperature

Chen, Yost et al., IEEE S3S (SOI-3D-Subthreshold Microelectronics) (2013) Burns, et al., Handbook of 3D Integration (2008) (2011)

Minitherms 3D Proposer’s Day slides - p11

Three-Dimensional Circuit and Microsystem Integration

Three FDSOI CMOS Tiers

Oxide Bond Interface

Tier-2

Tier-3 3D Via

3D Via

Transistor Layers

Tier-1 Transistor Layer 20 µm

RF Back Metal

Tier-1

• Wafer-scale high-density 3D integration supports low power, compact, advanced microsystems

• Heterogeneous integration enables optimization of each tier for a specific function such as imaging, photonics, signal processing, analog or high power RF applications

Oxide Bond Interface

Chen, Yost et al., IEEE S3S (SOI-3D-Subthreshold Microelectronics) (2013) Burns, et al., Handbook of 3D Integration (2008) (2011)

Minitherms 3D Proposer’s Day slides - p12

• Overview of Fabrication and Packaging at MITLL

• Test Article Capabilities

Minitherms 3D Proposer’s Day slides - p13

CMOS: 90nm FDSOI

• Dual threshold process

• 7-level-metal BEOL (back-end-of-line)

Test Article Capabilities

GaN-on-Si HEMTs

• CMOS compatible

• 2-level-metal MMIC process

Heater Chip (Concept)

• CMOS compatible

• Addressable heating elements & temperature sensors

• MIT LL available to provide test articles to evaluate 3DIC cooling solutions

– Will use demonstrated fabrication processes, designs, and technologies

– Target 1.3 kW per chip, hot spot heat flux 2 kW/cm2

Microjet Cooling

• CMOS compatible

• Bonded to surface of device for integrated cooling

Minitherms 3D Proposer’s Day slides - p14

CMOS Capability at MIT Lincoln Laboratory

90 nm Fully Depleted Silicon-on-Insulator CMOS Wafer

TEM of single gate of 90nm FDSOI device

Process Design Kit Process TCADLibrary and IP Fabrication Test

0.5 µm

TCAD = Technology Computer Aided Design

Channel

Gate

Source Drain

Fully Depleted Silicon-on-Insulator CMOS Technology at LL:

1. Flexible technology platform with demonstrated cryogenic, low power, high voltage, and RF variants at the 90 nm node

2. 100% in-house fabrication on 200 mm SOI substrates with seven metal layer aluminum back-end-of-line

3. Infrastructure to enable and support design through test

4. Compatible with 2.5D and 3D heterogeneous integration for high performance microsystems

Gouker, P., FDSOI CMOS www.ll.mit.edu/media/7201

Minitherms 3D Proposer’s Day slides - p15

CMOS-compatible 200-mm GaN-on-Si:

1. Process Design Kit (PDK) and Custom Design services

2. Au-free ohmic contacts

3. MMIC process with MIM capacitors, resistors, and thick metal-2 for RF performance

4. Both coplanar waveguide or microstrip architectures supported

5. fT, fmax > 50, 70 GHz

6. Through-substrate vias (TSVs) provide path for RF signal directly through substrate

GaN-on-Si HEMT & Power Amplifier

TiN gate

TiN/Al metal-1

Oxide

Source Drain

500 nm

500 µm

GaN-on-Silicon

5 µmContact to GaN

Compatible with 3D heterogeneous integration:

1. CMOS technologies for optimized mixed-signal operation

2. Microjet cooling for compact thermal management

Warnock, et al., IEEE/MTT-S International Microwave Symposium (2020)

GaN epitaxial layer

Si substrate

OxideGate

G aN o n

Si Si

C M

O S

CMOS metal layers

5 µm

Bonding interface

Cross section of CMOS/GaN wafers

Minitherms 3D Proposer’s Day slides - p16

Integrated Microjet Cooling

Microjets thermal solution same size as device:

1. Embeds the cooling within the substrate, minimizing thermal interfaces

2. Customizable designs, uses industry-standard silicon processing and is scalable to foundry-level production

3. 400,000 W/m2 ºC heat transfer coefficient with low flow rate and modest pressure (an order of magnitude higher than microchannels (~20,000 W/m2°C) or cold plates (~2,000 W/m2 °C)

4. Microjets have been demonstrated on functional RF devices, increasing the device gain

100 1,000 10,000 100,000 1,000,000

Air cooled Cold plate

Nucleate Boiling Microchannels

Microjets

Heat Transfer Coefficient (W/m2 oC)

Walsh, Malouin, Browne et al., IEEE Trans. on Components, Manufacturing, and Technology (2019)

Minitherms 3D Proposer’s Day slides - p17

Heater / Temperature-Sensor Chip Concept

• Single Layer Chip

– Heaters and sensors are interconnected with

90nm BEOL integration

• Temperature Sensors

– SOI diode operation – calibrate temperature to forward bias voltage required to achieve target diode current

– Requires 2 or 4 connections (TBD)

• Heater Design/Capability

– Silicide resistors

– 2kW/cm2 hotspot heat flux

– 1.3 kW/chip

• Bump Pads

– 50 µm diameters with 100 µm pitch and can handle 1A

– Additional bump pads can be included to assist in cooling

Through Vias

Heaters

Temperature Sensors

Bump Pads

Minitherms 3D Proposer’s Day slides - p18

• Overview of Fabrication and Packaging at MITLL

• Test Article Capabilities

Minitherms 3D Proposer’s Day slides - p19

• When any proposing entity would like to utilize MIT-LL technology in their approach to an open BAA, the proposer(s) should offer a response to the BAA that calls for the use of MIT-LL as Government Furnished Capability (GFC)

– MIT-LL will provide the proposer(s) with all the necessary information (technical description, schedule, and cost package) to perform the GFC required activities at MIT-LL. The Proposer MUST include this information in their proposal response for the DARPA technical evaluation to be completed.

– MIT-LL will also provide the proposer(s) with a letter from our contracting officer authorizing our participation in the proposed activity

• MIT-LL will provide a separate Statement of Work (SOW) directly to DARPA containing the same technical activities, schedule and cost as included in the original proposal(s).

• MIT-LL would then be funded directly by DARPA using a Military Interdepartmental Purchase Request (MIPR) to cover it’s activities under the proposal(s)

• MIT-LL will fully participate as a program team member to make the activity a success

How To Work With MIT Lincoln Laboratory (MIT-LL) yost@ll.mit.educhen@ll.mit.eduContact info:

mailto:yost@ll.mit.edu mailto:yost@ll.mit.edu

Minitherms 3D Proposer’s Day slides - p20

• MIT-LL mission is to support technology for national security

– System prototyping and demonstration

– Long-term technology development

– Technology transfer to US industry to meet future US government needs

• Heterogeneous integration capabilities available for low volume, trusted use

– Interposer fabrication with TSVs

– 2.5D micro-bump bonding

– Wafer-scale integration with high density 3D interconnect

• Test articles are available to enable performer cooling solution demonstrations

Summary

GaN-on-Si HEMTs Heater Chip (Concept)Microjet CoolingCMOS: 90nm FDSOI

Delivered to the U.S. Government with Unlimited Rights, as defined in DFARS Part 252.227-7013 or 7014 (Feb 2014). Notwithstanding any copyright notice, U.S.

BACKUP

Minitherms 3D Proposer’s Day slides - p22

Technologies at MITLL Enabled by 3D Integration

2000 2005 2010 2015

ARMY

APS - CMOS

3DL1

Three tier

180 nm CMOS

3DM2

Three tier

180 nm CMOS

3DM3

Three tier

150 nm CMOS RF third tier

MOSAIC I

APS - CMOS

MOSAIC II

APS – CMOS

> 1 million pixels

VISA

Three tier

1.5V CMOS

3.3V CMOS

APD

NIRD

CMOS - MEMS

SWIR

InGaAs detector - CMOS

EPHI

Photonic -

CMOS

Two tier Foundry

JAZZ

3D Integration Technology Demonstrations

Advanced Imagers 200 mm

GaN – CMOS 200 mm

MIT LL Fabrication and �Heterogeneous-Integration Capabilities

Microelectronics Facilities at MIT-LL

Outline

Lincoln Microelectronics Laboratory�(ISO-9001, DoD Category-1A Trust Certified)

3D Integration Capabilities at MIT-LL

Slide Number 6

MEMS and Microfluidics

Multi-Chip Bonding and Micro-Bumping

Interposers with Through Silicon Vias

Wafer Alignment and Oxide Bonding Capability

Three-Dimensional Circuit and Microsystem Integration

Outline

Test Article Capabilities

CMOS Capability at MIT Lincoln Laboratory

GaN-on-Silicon

Integrated Microjet Cooling

Heater / Temperature-Sensor Chip Concept

Outline

How To Work With MIT Lincoln Laboratory (MIT-LL)

Summary

BACKUP

Technologies at MITLL Enabled by 3D Integration

File details come from the government source that posted it. Updated Feb 23, 2023.