Minitherms3D_FAQ_03162023_Updated.pdf

Miniature Integrated Thermal Management Systems for 3D Heterogeneous Integration

(Minitherms3D)

HR001123S0019

Frequently Asked Questions (FAQs) Updated as of 3/16/2023

1. Is providing liquid between tiers an acceptable solution for TC1b (thermal isolation)?

A. There is no restriction on materials as long as they do not have adverse environmental impact that cannot be mitigated.

2. Is there any limitation on gap thickness?

A. Tier thicknesses and gaps between tiers must be consistent with their intended functionality and interconnect density requirements.

3. What is included in the definition of heat rejection volume?

A. The heat rejection volume refers to the hardware used to reject heat to the ambient air.

4. Is there a preferred fabrication facility such as Sandia National Laboratories or Massachusetts

Institute of Technology Learning Laboratory (MIT-LL)?

A. There is no specific requirement for selecting a fabrication facility. Each proposing team must provide solutions which meet all the BAA requirements.

5. Are the outputs of Phases 1 and 2 expected to feed into Phase 3 for a DoD-relevant application?

A. All phases must be proposed together and need to be consistent with a commercial and/or

DoD-relevant end application.

6. Is the maximum tier temperature 85oC?

A. Maximum tier temperatures must be consistent with material/devices requirements for the tier.

7. How is success measured when thermal resistance is very low due to low heat flow?

A. Both in-plane and cross-plane heat transfer need to be addressed to meet the BAA metrics that can be found in Table 1 on page 11 of the BAA.

8. Is it permissible to provide a solution where the bottom is liquid cooled and the top is air cooled?

A. Choices of cooling techniques within the stack and its surfaces are left up to the performer and subject to the size constraints specified on page 11 of the BAA.

9. Can the vertical sides of the enclosure be used as part of a liquid cooling solution?

A. There is no limitation on where a solution is placed as long as it is consistent with all BAA requirements and environmental impact.

10. Do you expect 1-phase or 2-phase cooling solutions?

A. There is no limitation of this nature in the BAA.

11. Do you expect air-side cooling for the link (TC2a)?

A. The link is for transmitting heat from the 3D stack to the heat rejection component.

Solutions that are consistent with all BAA requirements and environmental impact are permissible.

12. How evenly distributed does 6.8kW power in tiers need to be?

A. Tiers must be equally powered. Performers can exceed the power specification if they want.

13. Are solutions allowed to have more than 5 tiers?

A. Yes, solutions with more than 5 tiers are permitted if they are consistent with the intended functioning of the stack, interconnect density requirements for various tiers, and all of the goals of the BAA.

14. Is there government furnished equipment (GFE) specified/provided?

A. No GFE is specified/provided.

15. Is there any example of a system that you are looking to achieve by this prototype?

A. No exemplar solutions are provided by the government. Proposed solutions must be consistent with the requirement for ultimate heat rejection to ambient air. For Phase 1 and Phase 2, the ambient environment is at 20oC and atmospheric pressure. For Phase 3, performers must propose a representative heat rejection environment that is consistent with DoD-relevant applications.

16. Is the hot spot size requirement of 2mm by 2mm a maximum or minimum?

A. The hot spot size requirement is the maximum at the specified heat flux.

17. What is the role of methodology and framework? What is the modeling expectation?

A. These elements would be used for the selection and justification of the proposed approaches to meet the specified targets. The needs and expectations for modeling are listed on page 13 of the BAA for all phases.

18. Do I need to have industrial partners within my team?

A. Teaming is left open to proposers as long as the BAA requirements are met.

19. Can performers consolidate and merge to promote the combined solutions?

A. The Associate Contractor Agreements (ACA) clause allows for changes in teaming throughout the program.

20. Is it possible to work with other teams to engage in internal research and development (IRAD) efforts influenced by Minitherms3D and independently determined to be applicable for DoD?

A. There are no restrictions on IRAD efforts influenced by Minitherms3D to be pursued as separate initiatives.

21. What type of thermometry is required?

A. There is no limitation on the equipment/circuitry used to measure metrics, but proposals must illustrate how metrics will be measured.

22. Are we permitted to provide a thermal emulator tier using heaters to accurately provide a variety of DoD-relevant thermal profiles? If so, are active or passive heaters preferred?

A. Yes, a thermal emulator tier is permissible. There is no limitation on any heater type but all BAA goals must be met.

23. Are we permitted to use an off-the-shelf part instead of a custom chip to reduce the chip cost? If so, there are other issues such as being able to interface with the off-the-shelf chip, whether it has the heat flux, whether there are enough temperature sensors on it, etc.

A. The use of off-the-shelf components, in whole, or in part, is allowable, as long as the stated goals in the BAA for powering, thermal management, and metrology can be achieved.

24. Could you explain the following from Table 1. Minitherms3D Metrics on page 11 in more detail?

“Solution must allow electrical interconnect density 4 x 107/mm3 for processing tier; tier thickness and spatial power dissipation distributions must be consistent with the intended functionality and interconnect density requirements, and allow the demonstration of all TC1 challenges”. The underlined text above is not clear for me. Does it mean that we have to include 4 x 107 interconnects within mm3?

A. Any thermal management solutions proposed for the processing tier must meet the volumetric interconnect density requirement for 3DHI. For more details, refer to the proceedings of the 2021 International Solid-State Circuits Conference [1]. As stated in the BAA, there is no requirement to fabricate functional tiers for Minitherms3D. However, the proposed approaches must not violate interconnect density requirements.

[1] Douglas Yu, “Foundry solutions for 2.5D/3D Integration”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2021.

25. Is there a specific interconnect bandwidth requirement for a processing tier?

A. There is no specific interconnect bandwidth requirement.

26. Can interconnect density (4e7/mm^3) be traded for bandwidth providing the same level of throughput density (bits / s mm^3)?

A. No, you must follow the requirement for interconnect density. As mentioned in question 25, there is no requirement to fabricate this density of interconnects, as long as the proposed thermal management approach does not violate it.

27. Can you explain the definition of air conditions? According to the BAA, the air surrounding the thermal system is available at 1 atm of pressure and 20 oC temperature. The definition of air pressure can be ambiguous as the pressure of a fluid can be static or total.

A. For Phases 1 and 2, the ambient pressure and temperature conditions are prescribed to represent a laboratory environment at 1 atm (static) and 20 oC. “Atmospheric pressure” on page 10 of BAA refers to 1 atm, or standard atmospheric pressure. For Phase 3, as stated in the BAA, the metrics need to be demonstrated for a representative application environment, chosen by the proposer.

28. How do you define thermal system volume? According to the BAA, the thermal system volume is limited to 0.006 m3.

A. “Heat rejection system < 0.006 m3” on page 7 of the BAA refers to volume of the hardware used to reject the heat to the ambient air, including whatever materials it is composed of, as well as air moving device(s).

29. Are there constraints for heat rejection system volume for TC2b?

A. Yes, see the paragraph under “B. Program Description” on page 7 of BAA and box entry of “Figure 2” on page 9 of the BAA. Both references state that heat rejection system volume needs to be < 0.006 m3.

30. Does a SiGe BiCMOS tier satisfy the requirement for a compound semiconductor tier?

A. Yes, see page 12 of BAA for more details on the material type criteria.

31. Must the tier be a square?

A. Footnote (a) of “Table 1” on page 11 of BAA specifies the footprint size or tier size needs to be square within the range of 1 cm x 1 cm to 3 cm x 3 cm.

32. Do proposed solutions for TC2a need to be defined along with all the other TCs?

A. Yes, define and discuss the details of the proposed solution for meeting metric TC2a, which is the thermal link between the 3DHI stack and the heat rejection device. See paragraph under “Technical Challenge (TC2): Reducing thermal resistance external to the 3D stack” on page 9 of the BAA for guidance.

33. Does the realistic thermal environment need to be defined in the proposal?

A. Yes, define and discuss the boundary conditions of the proposed realistic environment for the demo at the end of Phase 3 as stated on the BAA. See last paragraph on page 10 under “D. Technical Area” and “Figure 3” on page 13 of the BAA for reference.

34. What is the expectation of thermal modeling for this program?

A. Refer to paragraph 5 on page 12 of the BAA for guidance on the modeling requirements. It reads “In addition to the experimental demonstrations, Minitherms3D performers will be expected to develop thermal modeling capability from the device to system level for 3D stacks under steady state and transient conditions to simulate realistic operating conditions, incorporating the new physics brought in by the proposed multi-scale thermal management techniques. This will include interfacing of multiple modeling scales from nm to tens of cm, and s to several minutes. Reduced order modeling capability will be developed to perform co-design and multi-objective optimization at the system scales. The modeling capabilities will be developed within each phase. The transition path from the program to target applications will be facilitated through the demonstrations near the phase boundaries.”

Questions based upon technical challenges (TCs):

I. TC1a: Increasing in-tier heat transfer without increasing tier thickness.

i. Can you define “hot spot” and “hot spot heat flux” in more detail?

A. The maximum hot spot size and heat flux are 2 mm x 2 mm, and 2 kW/cm2 respectively.

B. Hot spots are localized regions with significantly higher heat fluxes than the rest of the tier which is subjected to a background heat flux.

ii. Is hot spot heat flux a requirement on every tier?

A. Yes.

iii. Is 1 cm x 1 cm to 3 cm x 3 cm a tier size requirement?

A. Yes.

iv. Is background heat flux of 150 W/cm^2 a requirement for every tier?

A. Yes.

II. TC1b: Increasing thermal isolation between adjacent in-plane and out-of-plane functional blocks.

i. In the Table 1 note for TC1b, what is meant by in-plane AND out-of-plane isolation (inter- or intra-chip)?

A. In-plane and out-of-plane refer to within the tier and between adjacent tiers, respectively.

ii. Q. Do the TC1b Phase 2 and 3 metrics simply prescribe a material with a room temperature thermal conductivity of <0.03 W/m-K and shall it be used if the bulk semiconductor is Si and <0.011 W/m-K if GaAs?

A. Yes, the metrics simply prescribe a thermal conductivity ratio between the isolation region and the base semiconductor tier. Proposers should use the appropriate physical properties for proposed tiers.

iii. Does this requirement for a particular tier material potentially conflict with the overall goal of improved thermal management for 3DHI packages?

A. Isolation is needed only in localized regions of a tier or between neighboring tiers, where thermal coupling may adversely impact intended performance. The local isolation approach needs to be consistent with the overall thermal management requirement.

iv. Is thermal isolation a requirement between every tier?

A. Thermal isolation is a requirement between adjacent regions within a tier and between neighboring tiers, where needed.

v. Is between-tier thermal isolation necessary if the cooling approach is sufficient to keep individual tiers within their respective temperature limits?

A. Thermal isolation is needed where functional requirements make this desirable.

While the BAA metrics for isolation need to be demonstrated, these need to be implemented in prototypes, where needed.

vi. Since heterogeneous integration is of significant government interest, why are all of the TC1 metrics in this BAA derived from Si-based 3D simulations and device types (e.g., RAM, Si

CMOS)?

A. Si-based 3D simulations are provided as examples of challenges in 3D stacking.

The metrics apply regardless of tier material type. Page 12 of the BAA asks for at least two different tier materials, including at least one Si tier, and one compound semiconductor material tier.

III. TC1c: Increasing heat removal from each tier while maintaining low thermal resistance.

i. Can potential solutions include application spaces that use tiers that are powered at unequal levels?

A. Equally powered tiers are required to demonstrate the BAA deliverables.

However, approaches developed should be usable for unequal tier powers up to the required demonstrated ones.

IV. TC2a: Reducing link thermal resistance.

i. What does “maximum stack surface temperature” specifically refer to in the TC2a metric, note (d)? Does this metric incentivize the use of Si over higher temperature capable GaN and SiGe?

A. It refers to the maximum temperature on the surface of the 3D stack. The metric does not incentivize a specific semiconductor material. The stack must include at least one Si tier, and at least one compound semiconductor material.

V. TC2b: Increasing volumetric heat rejection capability while reducing heat rejection resistance to air.

i. Can you expand on the definition of heat rejection system and its volume? (e.g., Does heat rejection system volume include internal air? Where is the boundary between tiers and link drawn?)

A. Heat sink rejection system volume refers to the volume of the hardware used to reject the heat to the ambient air, including whatever materials it is composed

of. The boundary between tiers and link is specified in the BAA as no more than 20% outside of the 3D stack footprint.

ii. Can proposers consider alternate primary heat rejection mechanisms analogous to air cooling in Phase 1 and 2 to transition to a wider range of Phase 3 defense applications?

A. Proposed approaches for Phases 1 and 2 must be consistent with those in Phase 3.

VI. Footnote (a) of Table 1 states that the proposed solution “must allow electrical interconnect density 4 x 10^7/mm^3 for processing tier.” The interconnect density usually is given as the number of interconnects per area, not the number of interconnects per volume. It does not seem to be a simple typo where mm^2 was inadvertently changed to mm^3 because this would give an unreasonable average pitch of 6 interconnects/um. Please clarify this requirement.

A. For 3D heterogeneous integration a volumetric interconnect density requirement is necessary to ensure interconnect delay requirements are met with stacking. See, for example, the proceedings of the 2021 International Solid- State Circuits Conference [1]

[1] Douglas Yu, “Foundry solutions for 2.5D/3D Integration”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, USA, Feb. 2021.