HR001124S0038_HAPPI_FAQ_Update_10_21_24.pdf

HR001124S0038

Heterogenous Adaptively Produced Photonic Interfaces (HAPPI)

Frequently Asked Questions (FAQ) Document Updated on October 21, 2024

Q1. What is the anticipated total funding for the HAPPI Program?

A1. Total funding for the program is $30M for 36 months. DARPA anticipates multiple awards.

Q2. Does the 3um x 3um interconnect pitch scale with the center wavelength across the 400-1800 nm wavelength range, or is it constant for any center wavelength chosen within the range?

A2. It remains constant at 3um x 3um.

Q3. Does the spectral bandwidth of 100 nm scale with the center wavelength across the 400-1800 nm wavelength range, or is it constant for any center wavelength chosen within the range?

A3. It remains constant at 100 nm. The intent is to support broadband applications and avoid highly selective wavelength solution. Geometric scaling is allowed, if necessary, as long as the approach does not have inherit bandwidth limitations.

Q4. The BAA states that no specific material platform will be defined but it also mentions 100–500 µm thick semiconductor substrates. Are non-semiconductor substrates such as glass allowed?

A4. Glass and other non-semiconductor optical materials are of interest and traversing interfaces between heterogeneous materials is highly encouraged. At least one of the materials in the heterogeneous stack may be a semiconductor as the platform must be able to support active optoelectronic devices.

Q5. Will Abstract feedback be shared with the proposer team?

A5. Yes.

Q6. When will Abstract feedback be shared?

A6. A specific date for abstract responses cannot be provided. The processing time will depend on the number of submissions received.

Q7. Should UARCs contact DARPA before submission?

A7. Yes, UARCs will generally follow the instructions provided for FFRDCs. Please reach out through the BAA email if further clarification is needed.

Q8. Only one proposal is allowed per lead organization. Can we submit multiple abstracts?

A8. Yes.

Q9. Can technology or materials be used that are compatible with a foundry process, but not currently used?

A9. Yes.

Q10. Can modifications be done to the interposer and/or substrate at the BEOL?

A10. Yes.

Q11. What is the quantitative requirement on alignment?

A11. There is no alignment requirement in the BAA. Proposals should discuss alignment in the context of the proposed fabrication and assembly approach and the goal of achieving the loss metric. The approach to alignment should be compatible with automation and chip-scale manufacturing.

Q12. Can each layer have their laser, modulator or photodetectors?

A12. Integration of lasers, modulators or photodetectors is not required in the program.

They are allowed to be used in debugging, testing or calibration.

Q13. Should coupling be bidirectional?

A13. Yes.

Q14. Does the proposed material have to be CMOS-compatible?

A14. No. The proposals should discuss the pathway to manufacturability with the proposed materials.

Q15. Can you provide a funding range per proposal?

A15. DARPA does not specify funding range per proposal. We anticipate funding multiple proposals within the total program budget.

Q16. Is there an aggregate bitrate requirement or metric?

A16. Bitrate is not specified in the BAA. Data-transmission metrics are outside of the scope.

Q17. Do you have a target architecture or topology in mind?

A17. No. The architecture and topology are proposer defined.

Q18. Do you have a latency target for end-to-end path?

A18. There is no conversion or processing in the electronic domain. Therefore, we expect the latency to be time-of-flight.

Q19. How important is “reconfigurability” for HAPPI? Must the system architecture be “adaptable” or “tunable”?

A19. Reconfigurability and/or tunability is not required. “Adaptable interfaces” refers to any methods that may be used to achieve optical alignment post fabrication or assembly.

A20. Will the US Government be doing test and evaluation for the go/no-go milestones.

Q20. No. The data for the go/no-go milestones is supplied by the performers. Submission and approval of the test plans as well as live hardware demonstrations at the performer’s site are required per the BAA.

Q21. Is free-space optics ruled out?

A21. Yes. “Free space” is defined as unguided propagation in air. Refer to Q32 addressing small gaps occurring in chip-to-chip packaging. In such cases, microscale optical elements can be used as long as the solution is compliant with the specified array pitch.

Q22. Is there a minimum or a maximum number of waveguide layers for the originating or terminating PICs.

A22. The minimum number for both discrete chips is 4. The partitioning between the two chips can be 2-2 or 1-3. There is no maximum.

Q23. What does the minimum number of layers mean if the routing is not done by a layered approach?

A23. The HAPPI BAA (pg. 6) calls for transitions from in-plane to out-of-plane waveguiding and connections between multiple waveguiding layers per chip in a multichip stack. The approach should support traditionally produced waveguides. As stated in the BAA (pg.5), the “approaches should include coupling to a PIC platform with demonstrated optoelectronic components (sources, amplifiers, modulators, multiplexers, tuners, filters, detectors, and other optoelectronic components) while meeting the program loss and density metrics”.

Q24. What does 6.2 funding mean?

A24. It is DoD funding for Applied Research.

Q25. Are the current metrics subject to change?

A25. No.

Q26. Can the 3D routing footprint cover a larger area than the 2D coupling array?

A26. Yes. The proposer must show through analysis that the approach remains scalable and meets the BAA metric for the density and size of the coupling array.

Q27. Does the 3 µm pitch apply in vertical direction, between waveguide layers?

A27. No. The vertical pitch is performer defined.

Q28. Does the link array need to be square (3 mm x 3 mm)? Can it be rectangular with the same area?

A28. Yes, the array footprint is square, as specified in the BAA.

Q30. Is there a maximum height for the 3D routing?

A30. No, solutions should be compatible with chip scale integration and packaging dimensions.

Q31. Are there any polarization maintenance or polarization control requirements?

A31. No. Polarization maintaining or polarization invariant waveguides are not specified. Per the BAA, any approach should account for polarization-dependent losses and outline corresponding mitigation strategy.

Q32. The interface between the two chips is shown with zero gap. Is this meant to imply hybrid bonding (i.e. no solder balls)?

A32. All BAA graphics are for illustration purposes only. Both gapless and small gap (e.g.

accounting for solder ball thickness) are of interest. If a gap is envisioned, the optical path should be protected through standard packaging processes such as solder reflow, underfill, encapsulation, passivation, etc.

Q33. Is it envisioned to have electrical connections (in addition to optical connections) traverse the chip-to-chip interface?

A33. Yes. While it is not required for approaches to support coexisting electrical and optical connections through the chip-to-chip interface, it is highly encouraged.

Q34. Is there a power consumption requirement?

A34. No. Energy for one-time post fabrication trimming is unconstrained. However, any non-zero static power consumption may limit the scalability of the solution and should be addressed in the proposal.

Q35. Is international collaboration allowed?

A35. Yes. Per the BAA, “All responsible sources capable of satisfying the Government's needs, including both U.S. and non-U.S. sources, may submit a proposal that shall be considered by DARPA”.

Q36. Is there a requirement to implement “one to many” routing?

A36. No. All metrics in the BAA refer to point-to-point links.

Q37. What is the motivation for the requirement to traverse >100 µm substrate material?

A37. To enable optical through-substrate via, allowing vertical stacking of more than 2 photonic chips.

Q38. Is the HAPPI concept limited to 2-chip stacks?

A38. No. DARPA is interested in solutions, generalizable to more than 2 stacked dies.

Q39. Can the Phase 2 approach be demonstrated through die to wafer packaging?

A39. Yes.

Q40. How will ITAR issues be handled if foreign entities or individuals are performing on the program?

A40. Performers are responsible for determining and protecting ITAR information during program meetings and collaboration events.

Q41. Is there a preference for certain contract instruments?

A41. No.

Q42. If a performer is allowed to submit multiple abstracts, but is allowed only one proposal, who should determine which approach is to be caried forward in the proposal?

A42. CORRECTED: The BAA does not restrict the number of proposals per organization. Multiple proposals per organization are allowed.

Q43. Are broadband comb sources and/or modulators in the program scope?

A43. No.

Q44. The BAA references wavelengths in the 400 – 1800 nm band. Does the proposal need to cover the entire band?

A44. No. Covering 100 nm sub-band within the 400 – 1800 nm is sufficient.

Q45. Does the Government have a preference for a photonic foundry for technology transition?

A45. No. DARPA will consider any foundry capable of reproducing and sustaining the technology for DoD use. For further guidance, reference the BAA, Section II: Evaluation Criteria, Potential Contribution and Relevance to the DARPA Mission.

Q46. Does the link array size refer to number of physical channels or data channels that may be multiplexed on fewer physical links?

A46. It refers to physical channels.

Q47. Should active material platform be integrated in the final demonstrators in Phases 1 and 2, or should be just described?

A47. The active material platform should be integrated and demonstrated in functional links. The program metrics refer to measured performance on such links.

Q48. The 1000 x 1000 array size implies 1 million independent waveguides for addressing the array. Is that the program intent?

A48. As discussed in the test and evaluation section, the BAA states that the performance of the array can be evaluated by employing daisy-chained structures and statistical methods.

Q49. Does the program target specific DoD applications?

A49. The HAPPI program will develop foundational technology capable of transitioning to follow-on application-specific R&D. While discussion of DoD applications is encouraged, it is not required beyond addressing the BAA, Section II: Evaluation Criteria, Potential Contribution and Relevance to the DARPA Mission.

Q50. Can amplification be used to offset some of the losses for a net loss of 1 dB?

A50. No.

Q51. Can we propose routing devices requiring electrical actuation, and therefore, electrical connection?

A51. Yes. See, also A34 discussing power consumption.

Q52. If the university is not allowed to lead the proposal due to non-fundamental aspect of the BAA, is the university at least allowed to submit a proposal abstract and then have an industry partner to lead the proposal?

A52. There is no restriction on universities to submit Abstracts and Proposals. “Non-fundamental research” refers to publication restrictions only. It is entirely in the university discretion if they would participate.

Q53. In the BAA and at today’s presentation, both 90 degree and non-90 degree rounding layouts were shown. Are we required to do both, or can we do one of them so long as we can meet the milestones?

A53. No. Demonstrating one or the other is sufficient as long as the solution meets the metrics.

Q54. How does the performer prove that the process to create the optical link is compatible with an active platform?

A54. The performer is not required to demonstrate active components, but the compatibility should be thoroughly described using supporting evidence.

Q55. Where can we find the Proposers Day presentations and Q&A?

A55. The slides presented as well as video recordings of the Gov. session will be made available at www.darpa.mil/work-with-us/opportunities.

The Q&A (this document) is available at the sam.gov website along with the HAPPI BAA and will be updated on a regular basis until the question period closes on October 22, 2024.

Q56. Can a proposing team propose to conduct fundamental research led by a university in Phase I and to conduct non-fundamental research and commercial transition led by a company in Phase II?

A56. No. Non-fundamental research refers to both program phases. Furthermore, the prime organization cannot be changed between phases.

Q57. The example provided in the BAA for integrated 3D interconnects outlines a PIC integrated on an interposer, appearing to represent a 2.5D integration scheme. Is full 3D integration, bypassing the interposer and using 3D interconnects, within the scope of the HAPPI program?

A57. Yes, 3D integration and direct chip-to-chip coupling are within scope.

Q58. For the 3D photonic routing “obstacle course” pinout maps(s), can you clarify what is considered a “node”? Is it expected that there is a source or detector or some other structure at the nodes?

A58. A “node” can be interpreted as a “location” on the map. Sources or detectors are not required at the nodes. The intent is to demonstrate routing networks of high complexity.

Q59. For the 3D photonic routing “obstacle course” pinout maps(s), are nodes defined only on the first and last layers, or can nodes be defined on any/all layers?

http://www.darpa.mil/work-with-us/opportunities

A59. Each link in the obstacle course will consist of a guided optical path originating in the waveguide fabric of one discrete chip and terminating in the waveguide fabric of another discrete chip stacked on the initial chip.

Q60. Since A19 in the FAQ states that reconfigurability is not required, does this imply that the fabricated 3D photonic system is intended to have static interconnections as defined in the pinout?

A60. Yes.

Q61. Is the automated testing in Phase 2 expected to assess performance of many 1000x1000 arrays, such as across a wafer, or just within a single 1000x1000 array?

A61. Testing a single array will satisfy the program requirement. Testing across the wafer to assess the uniformity and yield of the platform is desirable, but not required.

Q62. Is there a requirement for representative or total sampling for testing of link arrays?

A62. In both phases, the metrics should be reported as typical performance across the array obtained by uniform sampling and statistical analysis.

Q63. Does the program metrics for link array size suggest that for Phase 1, that an array pitch of ≤ 300 µm will be acceptable (10 x 10 array in an array area of 3 mm x 3 mm)?

A63. Yes.

Q64. The adjacent link crosstalk metric states that it would be measured at a 3 µm x 3 µm pitch, but this would be limited by the link array size/pitch achieved in Phase 1 and Phase 2. Should this pitch be scaled to the 10x10 array size in Phase 1 and 1000x1000 array size in Phase 2 for a 3 mm x 3 mm area?

A64. In Phase 1, the adjacent link crosstalk can be measured in a smaller separate array with a 3 µm x 3 µm pitch. In Phase 2, it will be measured in the 1000x1000 array.

Q65. Can an organization submit multiple proposals?

A65. Yes, the BAA does not restrict the number of proposals per organization. A42 above has been corrected. An amended version of the Proposers Day slides will be made available.

Q66. The metric for the minimum number of routing layer implies that PICs may have two or more routing layers. Do the interconnects within a PIC also have to meet the Table 1 metrics for link efficiency, array size and area, crosstalk, optical power handling, spectral bandwidth and operating environment?

A66. Yes.

Q67. In the BAA, Table 1, a minimum number of >4 seems to imply at least 5 layers. The FAQ implies at least 4 layers. Can you please clarify which is the correct interpretation?

A67. The minimum number of layers is ≥4. The BAA, Table 1 has been amended to reflect the clarification. Please see Amendment 2.

Q68. What size of die are required?

A68. The minimum die size is 3 mm x 3 mm capable of accommodating the 1000 x 1000 Phase 2 array. The BAA does not specify maximum die size. Approaches that can address die-to-die, die-to-wafer, or wafer-to-wafer manufacturing flows are of significant interest.

Q69. Is it a requirement to stack more than 2 chips vertically?

A69. For demonstration on the program, only two chips are required to be stacked. Approaches that enable the stacking of more than 2 chips are highly encouraged.

Q70. Does the out-of-plane waveguide need to traverse the substrate of one of the component photonic chips?

A70. Per the BAA, the out-of-plane waveguide traverses the photonic circuit substrate. Please, reference BAA pg. 6, Section B. Program Description, pg. 7, Section C. Program Structure, and Table 1, Program Metrics. The vision is also illustrated notionally in Fig. 2 on pg. 6. The out-of-plane waveguide purpose is to traverse the thickness of optical components (PIC or interposer) and enable out-of-plane routing through the substrates thickness.