4H-SiC Silicon Carbide (SiC) Integrated Circuit Processing on 100 mm Diameter SiC Wafers

NASA Glenn Research (GRC) is hereby soliciting information from potential sources for fabrication of particular integrated SiC device structures (JFETs and resistors) via a particular fabrication process flow to the desired specifications on NASA-provided 100 mm diameter 4H-SiC epilayered wafers using NASA-provided device-layout design files. 

The National Aeronautics and Space Administration (NASA) GRC is seeking capability statements from all interested parties, including all socioeconomic categories of Small Businesses and Historically Black Colleges and Universities (HBCU)/Minority Institutions (MI) for the purposes of determining the appropriate level of competition and/or small business subcontracting goals for 4H-SiC Silicon Carbide (SiC) Integrated Circuit Processing on 100 mm Diameter SiC Wafers. The Government reserves the right to consider a Small, 8(a), Women-owned (WOSB), Service-Disabled Veteran (SD-VOSB), Economically Disadvantaged Women-owned Small Business (EDWOSB) or HUBZone business set-aside based on responses received.

NASA is seeking fabrication of specific integrated SiC device structures (JFETs and resistors) via a particular fabrication process flow designated as the “Gen. 12b” prototype wafer fabrication run to the following specifications on NASA-provided 100 mm diameter 4H-SiC epilayered wafers using NASA-provided device-layout design files. After the SiC device structures are completed, the wafers will be delivered back to NASA for additional processing of bond pads and the back-side contact that will complete the formation of integrated circuits needed for NASA missions. The resulting IC chips produced will be used to implement prototype extreme-environment electronic systems and demonstrations. A technical primer (overview) of the IC technology being implemented is online at https://www1.grc.nasa.gov/research-and-engineering/silicon-carbide-electronics-and-sensors/jfet-ic-tech-guide/ . The posted “IC. Gen. 12” mask layout design rules and related IC Gen. 12 documentation within this website is to be used for this prototype wafer fabrication run. 

No solicitation exists; therefore, do not request a copy of the solicitation. If a solicitation is released, it will be synopsized on SAM.gov. Interested firms are responsible for monitoring this website for the release of any solicitation or synopsis.

Interested firms having the required capabilities necessary to meet the above requirement described herein should submit a capability statement of no more than two (2) pages indicating the ability to perform all aspects of the effort. The submitted capabilities statement should include at the minimum information regarding relevant semiconductor device fabrication equipment, facilities, and competence based on prior experience to successfully execute the above noted requirement. 

Please advise if the requirement is considered a commercial or commercial-type product. A commercial product and commercial service is defined in FAR 2.101, Definitions.

All responses shall be submitted electronically to Claude David via email to claude.e.david@nasa.gov no later than 5pm EDT on April 21st, 2025. Please reference 80GRC025R7012SS in any response.  

This synopsis is for information and planning purposes only and is not to be construed as a commitment by the Government nor will the Government pay for information solicited. Respondents will not be notified of the results of the evaluation.