THREADS_Proposers_Day_Package.pdf

Technologies for Heat Removal in Electronics at the Device Scale

(THREADS)

Dr. Thomas Kazior Program Manager, MTO

Proposers Day

November 30, 2022

The THREADS program aims to overcome thermal limitations and achieve robust transistors operating near the electronic limit of RF output power

1Distribution A: Approved for public release; distribution unlimited.

Distribution A: Approved for public release; distribution unlimited. 2

Agenda

0.1

O u tp u t P o w e r

D e n si ty

W /m m

GaAs

Power Amplifiers (PAs)

Today’s GaAs Today’s GaN GaN Electronic

Limit

>10X increase in output power is possible in GaN

GaAs = Gallium arsenide GaN = Gallium nitride

Today’s GaN Thermal Limit

3Distribution A: Approved for public release; distribution unlimited.

Why Not Today? Today’s GaN is Thermally Limited

For every 10 oC rise in channel temperature, device lifetime is cut in half

Hot Spot

Pout = 40 W/mm

Pout = 10 W/mm

Pout = 5 W/mm2X hours per 10oC

450 400 350 300 150 100250 200

M e a n T im e t o F a ilu re

H o u rs

Typical DoD Lifetime Requirement

Channel Temperature (°C)

RF Transistor Cross-section

DARPA

Distribution A: Approved for public release; distribution unlimited.

THREADS Objective o Performance o Pout= 81 W/mm o Thermal Resistance: 8X reduction o Robustness o Channel temperature: < 225 °C** o Final program demonstration o Robust high power density transistor and PA

PA = Power amplifier Pour = RF output power GaN = Gallium nitride

*Measured continuous wave (CW) at X-band (8 – 12 GHz) ** Equates to a Median Time to Failure (MTTF) > 106 hour

Efficient AlGaN/GaN HEMT Power Amplifiers, IEEE 2008

RF Transistor Cross-section

The THREADS program aims to develop technologies to overcome the thermal limits and realize robust transistors that operate near their electronic limit of RF output power

Power Amplifier

Specific Goals*

DARPA

Raytheon

5Distribution A: Approved for public release; distribution unlimited.

0.1

1 10 100

O u tp u t P o w e r

D e n si ty

W /m m

Thermal Resistance [oC-mm/W]

GaAs

GaN (>106 hours MTTF)

GaN (10 hours MTTF)

Thermal resistance must be reduced to dissipate waste heat to maintain reliable high power density operation

THREADS Goals

225oC channel temperature constraint assumptions:

• Transistor efficiency = 60%

• Max tolerable temp rise = 150oC

• Mean time to failure (MTTF) = 106 hours

Fundamental GaN Limit

Program Goal:

81 W/mm

MTTF = Mean time to failure GaN = Gallium nitride GaAs = Gallium arsenide

8X

THREADS Technical Challenges Overview

Achieving high output power and safe operating temperature requires reduced thermal resistance both within and outside of the device

1/RTotal = 1/Rwithin + 1/Routside

Transistor Thermal Resistance

Routside device

Rwithin device

Parallel Thermal Resistance

Model

Distribution A: Approved for public release; distribution unlimited.

Channel

Buffer

Waste Heat

Intrinsic: Within the active device (Rwithin)

Extrinsic: Outside of the device (Routside)

Distribution A: Approved for public release; distribution unlimited. 8

• Achieving good channel properties (e.g. μe > 1000 cm2/V-s) requires:

• Reducing defect density in channel

• Nucleation and thick buffer layers

• Additional layers increase thermal resistance, in part due to thermal boundary at interfaces

THREADS Technical Challenges Summary

Technical Challenge 1:

Reducing thermal resistance within the device while maintaining good channel current transport properties

Technical Challenge 2:

Moving heat away from high power transistors more efficiently without degrading RF performance

University of Bristol

Temperature rise in un-gated GaN device

• SoA approaches for spreading heat:

• Increase gate pitch

• Spread heat over larger area

• Degrades gain and efficiency

• Thermal via holes

• Spatially separated from hot spot

• Not efficient at heat spreading

0.2

0.4

0.6

0.8

No Thermal Vias

Thermal ViasN o rm a liz e d T h e rm a l

R e si st a n ce

Distribution A: Approved for public release; distribution unlimited. 9

• THREADS seeks to reduce interfacial and thin film thermal resistance within the intrinsic device (epitaxial layer stack)

• Approaches may include but are not limited to:

• Novel nucleation and buffer layer growth processes

• Phonon bridges

• Phonon engineering through the use of isotopes

• Graded channel GaN HEMTs

• Digital AlN/GaN alloys

• Alternate high thermal conductivity substrates

• Alternate high thermal conductivity buffer layers (e.g. AlN)

• Homoepitaxial growth (e.g. AlN/AlN)

Technical Challenge #1:

Reducing thermal resistance within the device while maintaining good channel current transport properties

Substrate

Channel

Buffer

Rchannel

Rbuffer+interface

Rsubstrate

Rwithin = Rchannel +Rbuffer+interface + Rsubstrate

RF Transistor Cross-section

Distribution A: Approved for public release; distribution unlimited. 10

Technical Challenge #2:

Moving heat away from high power transistors more efficiently without degrading RF performance

Heat spreading structure

Routside

THREADS Transistor Cross-section

• THREADS seeks to develop approaches to spread waste heat and reduce transistor thermal resistance to maintain channel temperature of 225 °C

• Approaches may include but are not limited to:

• Topside and/or embedded 2D and 3D cooling structures

• Novel gate layouts and multi-finger transistor topologies

Distribution A: Approved for public release; distribution unlimited. 11

• Approaches that reduce the amount of dissipated heat

• Example: increasing transistor efficiency while maintaining the same mode/class of transistor operation

• May be proposed as long as any additional metrics/goals proposed are consistent with the metrics/goals published in the BAA

• External packaging solutions (e.g., microfluidics/jet impingement cooling, flip chip, etc.) are not in line with the objectives of this BAA

• Immature semiconductor technologies, such as all-diamond transistors, are not in line with the objectives of this BAA

Other Considerations

• Phase 1 (base)

• Develop within the intrinsic device material structures (TC1) and outside of the intrinsic device heat spreading structures (TC2) to reduce transistor thermal resistance by 2.5X

• Demonstrate a reliable, efficient PA with a RF power density of 25 W/mm

• Phase 2 (option 1)

• Optimize within the intrinsic device material structures (TC1) and outside of the intrinsic device heat spreading structures (TC2) to reduce transistor thermal resistance by 5X

• Demonstrate a reliable, efficient PA with a power density of 50 W/mm

• Phase 3 (option 2)

• Scale the results of Phase 2 to demonstrate RF transistors and PAs with an 8X reduction in thermal resistance

• Demonstrate reliable, efficient transistors and PA with 16X increase in RF output power density (to 81 W/mm)

THREADS Has One Technical Area Focused On Addressing Both Technical Challenges

12Distribution A: Approved for public release; distribution unlimited.

DARPA

Raytheon

Distribution A: Approved for public release; distribution unlimited. 13

THREADS Program Metrics

Metric Units SOA Phase 1 Phase 2 Phase 3

Inside intrinsic device (material) thermal resistance1 oC-mm/W Proposer Defined2 TBD4 TBD4 TBD4

Outside of intrinsic device heat spreading thermal resistance3 oC-mm/W Proposer Defined2 TBD4 TBD4 TBD4

Transistor thermal resistance5 oC-mm/W X6 0.4X 0.2X 0.125X

Transistor/power amplifier Pout 7 W/mm 5 25 50 81

Transistor/PA robustness8 % < 5 < 5 < 5 < 2

1. Measured on proposer-defined material thermal resistivity test structure and with proposer-defined measurement approach (e.g., time domain thermal reflectance (TDTR), micro Raman spectroscopy). Test structures and measurement approaches should be coordinated with the with government IV&V team. Thermal resistance is measured from channel layer to bottom of substrate and includes thermal resistance of channel layer, buffer layer, substrate, and interfaces. Channel mobility > 1000 cm2/V-s.

2. Proposer-defined inside the device thermal resistance metric based on proposer’s mature baseline GaN device and required to achieve the THREADS transistor thermal resistance metrics.

3. Measured on proposer-defined outside the intrinsic device thermal resistivity test structure and with proposer-defined measurement approach. Test structures and measurement approaches should be coordinated with the with government IV&V team.

4. Proposer-defined outside the intrinsic device thermal resistance metrics based on proposer’s approach and required to achieve the THREADS transistor thermal resistance metrics.

5. Measured on multi-finger transistors using proposer defined transistor thermal resistance test structures and with proposer defined measurement approaches. Test structures and measurement approaches should be coordinated with the with government IV&V team. Thermal resistance measured from channel hot spot to bottom of substrate and includes within intrinsic device (material/epi stack) thermal resistance (TC1) and outside of intrinsic device heat spreading thermal resistance (TC2).

6. Proposer-defined value for thermal resistance based on proposer’s mature baseline GaN device technology.

7. Power density measured on multi-finger transistor cells and standard evaluation circuits (SECs, e.g., single-stage MMIC PA test vehicles); minimum total gate periphery =

600 mm (e.g., 6 x 100 mm) with a maximum gate pitch of 50 mm; Pout density at peak PAE; PAE > 60% at 10 GHz with 20% bandwidth; 30% duty cycle; peak channel temperature: 225oC; Average power density measured on a minimum of 20 transistor cells and SECs across a minimum of 2 wafers.

8. Change in Id, Pout after 1000-hour CW RF stress test measured on SECs; SECs biased for Pout = 25, 50, 81 W/mm (Phase 1, 2 and 3 respectively) and maximum PAE at 10 GHz with a 20% bandwidth and peak channel temperature: 225oC; Robustness measured on a minimum of 20 SECs across a minimum of 2 wafers.

Program Structure and Schedule

Program Kickoff

Aug ’23

Technical Area (TC1/TC2): Thermal optimization of materials and heat spreading structures for robust high RF power density transistors and PAs

Phase 1 (18 mo) Phase 2 (18 mo) Phase 3 (12 mo)

Material Design (TC1) and Advanced Heat Spreading Architecture (TC2) Development

Material Design (TC1) and Advanced Heat Spreading Architecture (TC2) Optimization

High Power Density PA Demonstration

FY 2026FY 2023

CY 2023

FY 2024

CY 2026

FY 2025

CY 2024 CY 2025

FY 2027

CY 2027

• 2.5X improvement in transistor thermal resistance

• Robust RF PA with 5X increase in power density (25 W/mm)

• 5X improvement in transistor thermal resistance

• Robust RF PA with 10X increase in power density (50 W/mm)

• 8X improvement in transistor thermal resistance

• Robust RF PA with 16X increase in power density (81 W/mm)

Interim test structures and transistor/PA

Thermal test structure / PA design review

KO, QPRs, Quarterly Technical and Financial Status Reports

Deliver test structures and transistor/PA & metrics eval

Deliver test structures and transistor/PA & metrics eval

Deliver test structures and transistor/PA & metrics eval

Interim test structures and transistor/PA

Thermal test structure / PA design review

Thermal test structure / PA design review

IV&V: AFRL Wright Patterson, NIST

• Detailed spend plan at program kickoff and execution of subsequent option awards

• Quarterly technical reports

• Monthly financial reports including updated expenditures.

• Briefing materials for periodic technical status reviews and program-wide (PI) reviews

• Design review packages including details of design, modeling, and simulation of all transistors, electrical and thermal test structures, and power amplifier/SEC test vehicles

• Test data packages for all hardware deliverables

• Hardware deliverables:

• Interim: Representative thermal test structures, multi-finger transistor cells, and PAs/SECs

• End of Phase: Minimum of twenty (20) of each of thermal test structures, multi-finger transistor cells, and PAs/SECs from more than one wafer

• End of Phase deliverables should be received by government no less than six (6) weeks before end of phase to allow time for IV&V

Deliverables

• Test articles include:

• Thermal test structures

• For evaluation of thermal resistance of:

• Intrinsic (within) device (TC1)

• Extrinsic (outside) device heat spreading structures (TC2)

• Multi-finger transistor thermal resistance (TC1 + TC2)

• Thermal metrology techniques may include:

• Raman spectroscopy

• Gate resistance thermometry

• Steady-state thermoreflectance (SSTR), time-domain thermoreflectance (TDTR), or frequency-domain thermoreflectance

(FDTR)

• Multi-finger transistor cells

• For evaluation of transistor small and large signal X-band performance

• Minimum of 6 fingers

• Gate width and pitch proposer defined

• SECs/PAs

• Contain multi-finger output stage transistors with input and output matching networks

• For PA demonstration and characterization of transistor robustness using 1000-hour RF stress test

• To ensure consistency in characterization, performers are expected to design appropriate thermal test structures, multi-finger transistor cells, and SECs and generate a test methodology and test plan in consultation and collaboration with the government IV&V team

Test Articles and Metrology

Key THREADS Dates

• Abstract Due Date: December 22, 2022 4:00 pm (ET)

• FAQ Submission Deadline: January 31, 2023 by 4:00 pm (ET)

• Proposal Due Date: February 17, 2023 4:00 pm (ET)

• Estimated period of performance start: August 2023 www.darpa.mil

18Distribution A: Approved for public release; distribution unlimited.

Technologies for Heat Removal in Electronics at the Device Scale (THREADS) Proposer’s Day

Mark Rosker, MTO Director

Briefing prepared for THREADS Proposer’s Day

30 November 2022

Approved For Public Release; Distribution Unlimited

C4ISR: Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance

PNT: Positioning, Navigation, and Timing

Disruptive Microsystems

Directed Energy Electronic WarfareC4ISR PNT

Microsystems ManufactureLocal Processing Spectrum Dominance

High-performance, intelligent microsystems and next-generation components

Spectrum Dominance: Key challenges

Reducing SWaP-C of front-end elements

Increasing tactical range Enabling robust operation in congested spectrum

Source: Adobe Stock

Bulky electronics and optics undermine ability to miniaturize sensors and systems

Range of EW, DE, and C4ISR is limited by inherent properties of current materials and devices

RF components are insufficiently adaptable or robust to operate in increasingly congested spectrum

C4ISR: Command, Control, Communications, Computers, Intelligence, Surveillance, and Reconnaissance

DE: Directed Energy EW: Electronic Warfare SWaP-C: Size, weight, power, and cost Approved For Public Release; Distribution Unlimited

Electronics Resurgence Initiative (ERI)

A convergence of the commercial and defense electronics communities driven by common trends and threats

PCAST Report on Semiconductor Leadership

ERI announced ERI 2.0 thrusts announced

ERI 2.0

starts

ERI starts

ERI ERI 2.0

Overcoming security threats across the entire hardware lifecycle

Optimizing design and test for complex circuits and prototypes

Securing communications

ERI / ERI 2.0

thrusts

Realizing heterogeneous 3D electronics

Accelerating innovation in artificial intelligence hardware to make decisions at the edge faster

Increasing information processing density and efficiency

Manufacturing complex 3D microsystems

Developing electronics for extreme environments

Source: Advanced Technology Services, Inc.

Source: Adobe Stock

FY18FY17 FY19 FY21FY20 FY22 FY23 FY25FY24 FY26 FY27

Source: Adobe Stock

3D: Three Dimensional

Field Plate Devices Have Demonstrated Record Power Densities

1996 1998 2000 2002 2004

C W

P o w er d en si ty

W /m m

SiC Substrate

& Passivation

Advanced

Structures Sapphire

Sapphire

SiC

Field Plate Devices

Non-Field Plate Devices

G

SiC GaN

AlGaN

2DEG

Field plateSiN

DrainSource

Gate

Electric field modification region

Field Plate Device Schematic

WBGS RF

Start

3 8 13 18 23 28

Pout

Gain

PAE

Pin (dBm) P o u t (d

B m

G a in d

B

P A

E

Device dimension

0.55 μm x 246 μmf = 4 GHz

Pout = 32.2 W/mm

PAE = 54.8%

CREE

CornellUCSB

HRL

CREE

UCSB

Cornell

UCSB

UCSB

Cornell

NEC

CREE

CREE

Originally presented at CS MANTECH:

April 2005

5Approved For Public Release; Distribution Unlimited

Technologies for Heat Removal in Electronics at the Device Scale (THREADS)

Efficient AlGaN/GaN HEMT Power Amplifiers, IEEE 2008Overcome the thermal limits of transistors to push them to their electronic limit

6Approved For Public Release; Distribution Unlimited

0.1

O u tp u t P o w e r

D e n si ty

W /m m

Today’s GaAs Today’s GaN GaN Electronic

Limit

Today’s GaN Thermal Limit

THREADS

Hot Spot

RF Transistor Cross-section

Source: DARPA

GaAs: Gallium arsenide GaN: Gallium nitride RF: Radio frequency www.darpa.mil

RF Device Limits Prof. Umesh Mishra, UCSB Donald W. Whittier Distinguished Professor, Electrical and Computer Engineering

See Proposers Day Recording minutes 49:00 - 60:00 https://www.youtube.com/watch?v=ptwt8sLLnmU

Characterizing Thermal Properties in WBG and UWBG Devices

Samuel Graham

Department of Mechanical Engineering

University of Maryland

Sam Graham Patrick Hopkins

W. Alan

Doolittle

Asif Kahn

Tengfei Luo

Mark Goorsky

Karl Hobart

Marko Tadjer

Travis Anderson

Jen Hite Asegun

Henry

ONR MURI Team (PMs: Lynn Petersen & Mark Spector)

Additional Acknowledgements

• Stanford: Srabanti Chowdhury

• Penn State: Sukwon Choi

• Bristol University: Martin Kuball

• AFRL: Shin Mou

• Meisei University: Tadatomo Suga

• Nagoya University: Hiroshi Amano

1. The formation of hotspots in the device can lead to concerns for device reliability….How Do We Measure Tj?

2. How do we manage the channel temperature?

3. Can we change device architectures to reduce thermal resistance within the device itself?

Thermal Issues in HEMT Devices

Singhal et al., Microelectron. Reliab., vol. 46, no. 8, pp. 1247–1253, Aug. 2006.

GaN HEMTs

A Challenge for UWBG Technology: Thermal Properties

• The thermal conductivity of of UWBG semiconductor ternary alloys are typically very low and provides challenges in designing high power devices:

▪ GaN: up to 180 W/mK for thin films, ~200 W/mK for bulk

▪ Ternary Alloys: AlxGa1-xN and (AlxG1-x)2O3.......Below 15 W/mK

▪ Superlattices of AlGaN/GaN ….. Below 5 W/mK

▪ Digital Alloys: Can we improve thermal properties?

ACS Appl. Mater. Interfaces 2021, 13, 32, 38477–38490

<30 <10

Thermal Issues in HEMT Devices Managing the device temperature rise comes down to managing the device thermal resistance.

This includes:

1) Material thermal conductivity

2) Thermal interface resistance

3) Heat spreading

4) Geometry of the device architecture.

Techniques For Thermal Characterization

Time-Domain and

Frequency Domain

Thermoreflectance

(TDTR, FDTR)

Measures film thermal conductivity and thermal conductance of interfaces

Steady State

Thermoreflectance

(SSTR)

Anisotropic thermal conductivity measurements and automated spatial-mapping thermal measurements

Electro-Thermal

Modeling

(Simulation)

Explore different thermal management techniques and device structures to lower operating temperatures

Heteroepitaxial, Heterointegrated, and Monolithic Semiconductor Architectures

▪ Heteroepitaxy: Creation of

Lateral Power Devices

▪ Necessitated by the lack of bulk substrates

▪ Introduces interfaces with defects and complex interfaces within the device.

▪ Heterointegration: (e.g., Diamond growth or bonding)

▪ Allows for integration that cannot be performed by heteroepitaxy

▪ Defects at interfaces

▪ Homointegration: Bulk

Crystals

▪ Eliminates some complex interfaces within the devices

▪ Heat transfer through contacts

Diamond

GaN

AlGaN SourceDrain

Gate

GaN HEMT

~10-100 kW/cm2

GaN on SiC heteroepitaxy GaN on diamond heterointegration

High Power RF GaN HEMTs

• GaN electronics:

Advanced RF devices and power electronics.

GaN (150-180

W/mK)

SiC (380

W/mK) (2000 W/mK)

SiC

Pressure Sapphire

GaN

UHV chamber :~5E-6Pa; Room temperature

[0001]

[0001]

4ooff

Bonding Laser lift off

248nm laser

Surface activation

Cutting, Thinning, w/o anneal @ 1000oC 10min Al deposition

TDTR, TEM-EELS

GaN

[000-1]

Al

Ar-beam

2” GaN template

3” SiC wafer

(a) (b)

Transferred GaN layer

Unbonded area

2” GaN template

3” SiC wafer

(a) (b)

Transferred GaN layer

Unbonded area

Mu et al., ACS Appl. Mater. Interfaces 2019, 11, 36, 33428-33434

Method For Heterogenous Integration: Surface Activated Bonding- Eliminate Need for AlN

GaN-SiC interface with annealing

TBC: 230 MW/m2K

TBR: 4.5 m2K/GW

Very high quality thermal interfaces

Thermal Boundary Conductance: GaN-SiC

• Heterogenous Integration may be a way for producing high quality semiconductor combinations that are difficult to grow without interfacial layers.

• Additional steps will be needed to maintain the proper surface polarization of the GaN substrate.

GaN-on-Diamond Technology

GaN

GaN

Carrier GaN

Carrier GaN

Direct Growth

GaN

Si/SiC/Al2O3

Carrier

Epitaxial Growth

Carrier

GaN

Si/SiC/Al2O3

Bonding to

Carrier Wafer

Carrier

GaN

Epitaxial Growth

Wafer Removal

Carrier Wafer

Removal

Transfer Bonding

GaN on Diamond GaN on SiC

3x smaller

Same

Temperature

DARPA Near Junction Thermal Transport (NJTT) Program (2011-2014)

GaN

Dielectric Layer H e a t F lo w

Improved Performance using GaN/Diamond HEMTs

GaN on SiC

3X

GaN on Diamond

50 mm gate-to gate 10 mm gate-to gate

The DARPA NJTT program demonstrated through experiments and modeling that it is possible to improve the performance of AlGaN/GaN HEMTs on diamond when compared to the same features measured on SiC substrates.

Diamond may be an effective material for pushing critical devices to higher power levels and smaller form factors.

The thermal conductivity of diamond near the interface with GaN is varies with depth.

The structure of the diamond near the interface is highly dependent on growth conditions.

Anisotropy and vertical gradient in conductivity exists!

GaN on Diamond Integration

Si, GaN, SiC

Transition Or Dielectric

Surface Roughness

Vertical Inhomogeneity

(Spatial inhomogeneity)

Anisotropy

TBR

GaN

DARPA Diamond Program

Thermal Conductivity of Diamond Films

Film

Thickness

(μm)

Cross-plane ĸ

(W/m-K)

Model

(W/m-K)

Bulk 1540 (± 6%) 1490

20 1414 (± 9%) 1342

15 1371 (± 8%) 1240

10 987 (± 11%) 1088

5 796 (± 3%) ___

• Within the first micron, the vertical thermal conductivity is ~10% of bulk value!

• Difficult to predict as it is dependent on nucleation and initial growth!

Silicon

Al Transducer 90nm NCD 1µm kz,diamond = 175 W/m-K kL,diamond = 85 W/m-K

TBRSi-diamond = 13.7 m²-K/GW

Other Features of Microstructure Near Interface

Sample A

Sample B

6 mm

Sample A:

grain size near interface

(PV)= 100 nm grain size near surface

(PV)= 160 nm

Sample B:

grain size near interface

(PV)= 130 nm grain size near surface

(PV)= 190 nm

Similar ratio (~1.5) of grain expansion

Microstructure depends heavily on how the diamond is nucleated and grown.

Near equal 111 and 220 crystallographic orientation

Preferred 111 crystallographic orientation

K = 90 W/mK

K = 150 W/mK

Impact of Interface on TBR: GaN/Diamond

• Interfacial layers are used to nucleate the diamond growth.

• Interfacial layers can add resistance and impact diamond morphology.

• Can we reduce TBR by controlling the interfacial layer?

GaN

Diamond Interfacial layer

L. Yates, et al., ACS Applied Materials and Interfaces, vol 10, 24302 – 24309, 2018.

Low TBR SiNx Interface

Diamond

SiNx

GaN

BF Image

EELS

SiNx survives the diamond deposition process.

If done carefully, it is very smooth and leads to a low TBR.

TBR 10-12 m2K/GW

(TBC 80 – 100 MW/m2K) L. Yates, et al., ACS Applied Materials and Interfaces, vol 10, 24302 – 24309, 2018.

Heterointegration: GaN Bonded To Diamond using SAB

Diamond substrate

Al

GaN

SiNx

Remove SiNx layer and perform surface activated bonding of GaN to diamond.

Modified SAB Process:

1) deposit thin layer of Si at interface

2) Mix Si in Ar ion beam during surface preparation

Si

Si is deposited simultaneously with Ar ion beam irradiation

Z. Cheng et al., ACS Appl. Mater. Interfaces 2020, 12, 7, 8376-8384

Effects of SAB on TBC at GaN/diamond Interface

10 nm, sample 1

4 nm, sample 2

10 nm, sample 1 4 nm, sample 2

Z. Cheng et al., ACS Appl. Mater. Interfaces 2020, 12, 7, 8376-8384

• Temperature independent TBC

• Si interlayer created by mixing Si precursor into plasma is effective bonding method

• Higher TBC in sample 2 because of thinner Si layer

• TBR in the range of high quality direct growth methods

• Wafer scale technology

Experimental advances in reducing thermal resistances in WBG thin films and across interfaces via defects

• Growth: Record setting high thermal conductivities in GaN, AlN and GaN/AlN-based superlattices and alloys

• Processing: Defect engineering thermal boundary conductance (TBC) across GaN interfaces via ion irradiation

Record low thermal resistances of GaN films and interfaces (Doolittle)

Koh, et al. Phys. Rev. Mat. 5, 104604

Doolittle

Ga Tech

Hite

NRL

• Homoepitaxially grown GaN films exhibit exceptionally larger thermal conductivities

• Convergence with theory (Luo)

Koh, et al. Phys. Rev. Mat. 5, 104604

• Homoepitaxially grown GaN films with in situ prepared metal contacts exhibit exceptionally lager thermal boundary conductance

• Convergence with theory

Record low thermal resistances of GaN films and interfaces (Doolittle)

Doolittle and Graham

AlN grown on AlN bulk substrate using Metal Modulated Epitaxy

AlN bulk substrates have a native oxide on the surface

(oxides…removed through Al Flashing)

Samples intentionally grown and measured without Flashing!

TDTR Measurements show that the thermal conductivity k = 260

W/mK. Best fit when TBC >500 MW/m2K between AlN and AlN

Homoepitaxy of AlN on AlN

Experimental Measurements of DAs

Simultaneously Fit

TDTR and SSTR Data

Use two techniques to measure both in-plane and cross-plane thermal conductivity of digital alloys

Kz

Kr

Kz = 9.6 ± 0.5 W/m-K

Kr = 39.2 ± 2.1 W/m-K

Heat tends to spread in-plane within AlN/GaN digital alloys AFRL

Metal-Dielectric TBC: Al-Sapphire

Multi-step annealing approach to clean sapphire surface

• highly ordered terrace-and-step structure over the sapphire surface

• Results in very sharp and clean interfaces

0.4 nm RMS

No Discernable Atomic Terraces

0.04-0.06 nm RMS

425-550 nm Atomic Terraces

Model Correlation with Al-sapphire TBC

• Data matches well with AGF and non-equilibrium Landauer predictions

• This represents a prediction of a well characterized interface

• Elastic scattering process dominates

• Inelastic process, electron-phonon coupling within Al, electron-phonon coupling across interface are not important.

AGF by Z. Tian, Cornell University

Interfacial modes can enhance TBC/reduce TBR

And interfacial defects can control the population and density of states of these modes

Appl. Phys. Lett. 112, 011603J. Appl. Phys. 119, 015101

The experiment to increase TBC at Al/GaN interfaces

Ion irradiation controls the defect density within Kapitza length of Al/GaN interface

80 nm Al

400 keV He+ implants:

end of range dep

GaN

Strain can enhance TBC: consistent with earlier results

• Same conclusion can be made from prior Al/AlN/sapphire interface study

• Deeper understanding enabled by XRD and TEM (Goorsky), and demonstrates thin strained layers (not too much scattering) leads to increased TBC

Al

AlN

Al2O3 Substrate d

Heat Dissipation Pathways

Shoemaker, et al., IEEE TCPMT, 2021

Top-side Diamond on GaN development Columnar Structure

(Conventional growth) Isotropic Structure

(Recent growth)

➢ 1.9 µm grain size with 2 µm thickness

SEM SEM

J. Appl. Phys. 119, 175103 (2016)

Increase in-plane phonon mean free path

1.9 µm µ m

0.5 µm

>5 µ m

M. Malakoutian et al., Record-Low Thermal Boundary Resistance between Diamond and GaN-on-SiC for Enabling Radiofrequency Device Cooling, ACS Applied Materials & Interfaces, Dec 2021.

ACS Applied Materials & Interfaces, (Dec 2021)

➢ 500 nm grain size with >5 µm thickness

Distance (µm) Distance (µm)

D is ta n ce µ m

C h an n el T e m p er at u re

K ) So u rc e

D ra in

G at e

No Diamond

Back Diamond

Top Diamond Top&Back Diamond

2D Heat Transport Map

Top-side Cooling Approach with Diamond on GaN

Conclusions

GaN RF

HEMTs

AlGaN Channel

GaN Buffer

SiC Substrate

Drain Source AlGaN Barrier

GateSiN Passivation

RT

100x

Laser

488 nm

100x

LED

530 nm

TTI

GRT

TiO2

PaRT

100x

Laser

488 nm

• Wide Bandgap semiconductors have a lot of promise for future RF.

• Knowledge of material structure –property relationships along with Co-Design methods will be key to pushing the technology forward.

• Manufacturing for heterogenous integration will be an enabler of future technologies.

• Validation using thermal metrology will be key.

• Will require true multidisciplinary teams of scientists and engineers to solve these issues.

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

AFRL/RYD IV&V Support for DARPA THREADS Program

30 November 2022

Dr. Nei l Moser

Mr. Brian Pol ing

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 2

Introduction

• AFRL/RYD is proving IV&V support of the DARPA THREADS program

• AFRL/RYDD will provide X-band RF power measurements

• AFRL/RYDT will provide thermal characterization

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 3

On-Wafer Measurement Systems at AFRL/RYDD

8 – 110 GHz noise parameters 94 GHz Scalar Load-Pull10 MHz – 110 GHz S-Parameters

8-50 GHz 75-110 GHz

140 – 220 GHz S-Parameters

170 – 260 GHz Active Load-Pull 50 GHz Pulsed Load-Pull

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 4

X-band CW and Pulsed IV – Pulsed RF Power Measurements

Typical pulsed IV – pulsed RF chronogram

• PNA-X based vector-receiver load-pull up to 50 GHz

• Passive and active LP capabilities

• CW and pulsed IV – pulsed RF capabilities

• Relevant hardware:

• Keysight N5247B PNA-X

• AMCAD 200 series PIV system

• Maury 8 – 50 GHz mechanical tuners

• High power handling RF probes

• High power handling bias tees

Gate pulse

Drain pulse

RF window

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5

High Power X-band Pulsed Load-Pull Measurements

• On-wafer high power (> 20 W) measurements pose considerable challenges

• Power handling bottlenecks include:

X-band probes (24 W power handling)

X-band bias tees (50 W power handling)AFRL will work closely with performers to ensure precision measurements of high power DUTs

A B

A

B

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 6

Thermal Characterization at AFRL

• Infrared and Transient IR

• Thermoreflectance

• uRaman

• Structure Function / Thermal Time Constant Spectrum

• Thermal resistance / profile

• Thermal modeling

• RF/DC Thermal Characterization

• Device operation temperature

• Failure Analysis

• Trojan / counterfeit detection

• Reliability / Aging degradation modeling

QFI

• IR: ~2 μm spatial resolution, ~0.01°C Temp.

Resolution

• Photo-emission (PE): ~1 μm and ~single photon.

• Large dark box with multi-use feed-throughs

• Variable temperature stage

• Large Signal RF Thermal and EL characterization

• Dual cold plate chuck

• Thermal response

• Thermal impedance

• Thermal Resistance

• Complex Locus

• Structure Functions

T3STER

• 1626x1236 CCD camera

• 5x, 20x, 40x, 60x 100x objectives

• 365 nm, 470 nm, 530 nm, 780 nm LED source

• Sub micron spatial resolution

• Integrated AMCAD capability for pulse thermal measurements

Microsanj

• Available Wavelengths: 325 nm(UV), 488 nm, 514 nm, 532 nm, 633 nm, 785 nm

• Objectives: 5x, 20x, 50x, 100x, 50xL, 100xL, 15xNUV, 40xNUV

• Spatial Resolution: 0.5 μm with 100x, 20 nm with TERS μRaman

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 7

Quantum Focus Instruments (QFI) Infrared (IR)

System Capability

‒ ~2um Spatial Resolution

‒ Large Signal RF Thermal Characterization

‒ 5x and 15x objectives, with digital zoom

‒ Full device thermal profile, hot spot detection, estimated Rth

Test Paradigm

‒ Tbp = 75C

‒ Bias point 1: ¼ * Idq

‒ Bias point 2: ½ * Idq

‒ Bias point 3: Idq

‒ Others of interest

Failure Analysis

Thermal Profile

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 8

Thermalreflectance – Microsanj & TMX

System Capability

‒ Submicron spatial resolution

‒ Two vendors – centered on GaN and Si

‒ GaN centric wavelength light source

‒ Pulse thermal characterization (Rth) integrated into AMCAD PIV

‒ Monochrometer light source for optimal

SNR

COTS GaN HEMT

– 60mA, 530nm

AFRL GaN140 RY 170 – 21V, 85mA, 470nm

Analysis

- Different GaN -> different light wavelength

- Rth calculations are different

- See next slide for in-depth on TTR

Microsanj, TMX not pictured

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 9

Thermalreflectance and Physics Operation - ROCS 2022

* Taken from: P. Hayes, Comparison of quantitative and qualitative thermal measurement techniques on commercially available GaN HEMT transistor,” Reliability of Compound Semiconductor Workshop, May 2022

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 10

Thermal Characterization Test Structures - Discussion

Standard RF GaN HEMT

‒ SEC design, representative of full MMIC and/or larger RF GaN HEMT

‒ Ideally no air bridges

‒ Can incorporate larger devices

GRT

‒ Correlation with group to optimize design to SEC, GRT structure should represent SEC

‒ Device is specific to measurement

‒ Accuracy is specific to smaller size

‒ Measurement across the gate finger

SEC Packaged device, typical stratedge 580286 mod 5

Gate Resistance Thermomotery (GRT) Temperature measurement differences as Pdiss increases

*G. Pavlidis, et. “Characterization of AlGaN/GaN HEMTs Using Gate Resistance Thermomotery,” IEEE Transaction on Electron Devices, Vol. 64, No. 1, Jan 2017.

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 11

Questions?

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 12

Backup

DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.

Reliability / Ageing

• 300+ Reliability Test Channels

• 150+ DC/Mixed-signal

• 150+ RF (L- to V-band)

• High Voltage Switch ALT (600V)

• Pulse and CW

• Higher Power / Active Cooling

• Discrete, SEC, MMIC, Fixture Capability

• Temperature-controlled Facility, UPS, Conditioned Power, Nitrogen-controlled Test Environment

• Reliability and Degradation Research on:

• Compound Semiconductors (GaN, GaAs, SiC, GoX, etc.)

• Trust and Assured (Advanced Si, 2OE, etc.)

• Emerging and Enabling Technologies

Reliability Assessment / Physics of Failure

J O S H UA M A RT I N , D Y L A N K I RS C H , A N D F E N G Y I

M AT E R I A L M EA S U R E M E N T L A B O R ATO RY | N AT I O N A L I N ST I T U T E O F S TA N DA R D S A N D T EC H N O LO GY | G A I T H E RS B U RG , M D

D A R PA / M TO T EC H N O LO G I ES FO R H EAT R E M OVA L I N E L EC T RO N I C S AT T H E D E V I C E S C A L E

T H R E A D S P RO P O S E RS D AY | N OV E M B E R 3 0 , 2 0 2 2

N I S T T H E R M A L C H A R A C T E R I Z AT I O N

N I S T : W H O A R E W E A N D W H AT D O W E D O ?

• NIST supplies industry, academia, government, and others with measurement techniques, calibration services, reference data, and over 1,300 Standard Reference Materials-selling over 30,000 units per year. In the Army alone, 58,000 different types of equipment require NIST-traceable calibration.

• In 1951, NIST researchers developed a preservation technique to encase the Charters of Freedom—the Declaration of Independence, the Constitution of the United States and the Bill of Rights

• 5 Nobel Laureates: Four Nobel Prizes for work in physics: William D. Phillips in 1997, Eric A. Cornell in 2001, John L. Hall in 2005 and David J. Wineland in 2012; in 2011 Dan Shechtman was awarded the Nobel Prize in chemistry for his work on quasicrystals

• NIST inventions include neon lights, advances in forensic science (first DNA profiling standards), the first atomic clock (the NIST internet time standard is accessed 12 billion times per day), the first Volt standard, laser cooling of atoms, creation of first Bose-Einstein condensate, close captioning TV (NIST received an Emmy for this)

NIST Main Campus, Gaithersburg, MD

M EA S U R E M E N T C A PA B I L I T I ES

T R A N S P O R T P R O P E R T Y M E A S U R E M E N T S F O R S E M I C O N D U C T O R S A N D E N E R G Y M AT E R I A L S

• Composition Spread Thin Film Electrical Properties (300 K ̶ 1000 K, multilayer films or bulk): custom high-throughput, autonomous, scanning probe that measures 4P electrical resistivity & Seebeck coefficient; up to 76 mm diameter wafers

• High Temperature Electrical Resistivity and Seebeck Coefficient (300 K ̶ 1000 K, bulk): custom designed instrument uniquely capable of in situ comparison of various characterization methodologies and probe arrangements; used for protocols studies, RRs, and SRM 3452 certification

• Modified Quantum Design PPMS (1.8 K ̶ 390 K, He reliquefier, bulk or film): measures electrical resistivity, Seebeck coefficient, thermal conductivity, heat capacity, AC resistivity, custom Hall effect/carrier concentration (9 T magnet), custom impedance spectroscopy probe

• Synthesis Capabilities:

• Dual Chamber DC Magnetron Sputtering/Pulsed Laser Deposition System (PLD to be converted from oxides to semiconductors) for composition-spread film growth

• Spark Plasma Sintering (SPS) Device for powder densification of traditional semiconductors, ceramics, wide band gap semiconductors, and sputter target fabrication; 100 kN hydraulic press, 10,000 A through sample current; installation underway

HT Electrical QD PPMS Combi HT Electrical Combi HT Electrical Probe (zoom) Combinatorial Data

Develop critical thermal and electrical transport measurement methods and reference materials for bulk and thin film semiconducting materials and devices.

Ca3Co4O9 (Ca2La)Co4O9

(Ca2Sr)Co4O9

S2s

FDTR Instrument

J. Martin, Rev. Sci. Instrum. 83, 065101 (2012) J. Martin, Meas. Sci. Instrum. 24, 085601 (2013)

C U S T O M I N S T R U M E N TAT I O N

H I G H T H RO U G H P U T S C A N N I N G T H E R M O E L EC T R I C P RO B E H I G H T E M P E R AT U R E B U L K S E E B EC K C O E F F I C I E N T & R ES I ST I V I T Y

Y.G. Yan, J. Martin, W. Wong-Ng, M.L. Green, X.F. Tang, Rev. Sci. Instrum. 84, 115110 (2013)

S R M 3 4 5 1

Lowhorn, Nathan D; Wong-Ng, Winnie; Lu, John Z.Q.; Martin, Joshua; Green, Martin L; Bonevich, John; Thomas, Evan L; Dilley, Neil; Sharp, Jeffrey, Development of a Seebeck Coefficient Standard Reference Material (SRM)™, Journal of Materials Research 26, 1983 (2011).

D E V E L O P M E N T O F S TA N D A R D R E F E R E N C E M AT E R I A L S A N D D ATA

S R M 3 4 5 1 L O W - T E M P E R AT U R E S E E B EC K C O E F F I C I E N T ( 2 0 1 1 )

• Certified data between 10 K to 390 K

• Material: Bi2Te3; nickel & gold bilayer end contacts

• Dimensions (≈): 3.0 mm x 2.0 mm 8.0 mm

• Differential steady-state technique (T < 0.01T), 2-probe arrangement

• Seebeck calculated from linear fit of multiple corresponding voltage-temperature difference points

J. Martin et. al., Journal of Materials Research 36(16), 3339-3352 (2021).

S R M 3 4 5 2 H I G H - T E M P E R AT U R E S E E B EC K C O E F F I C I E N T ( 2 0 2 1 )

• Certified data between 295 K to 900 K

• Material: p-type polycrystalline Si80Ge20:B2.5

• Dimensions: 2.5 mm x 2.5 mm x 14 mm bars

• Seebeck coefficient: ≈ 116 µV/K (batch homogeneity: σA ≈ 1 %)

• Electrical resistivity: ≈ 1 mΩ-cm

• Thermal conductivity: ≈ 6 W-m-1K-1

• NIST (2006-09) [1]:

• 12 international laboratories measured the Seebeck coefficient between 2 K and 390 K in two rounds for two materials: constantan alloy (55 at.%

Cu/45 at.% Ni), and n-type Bi2Te3.

• The interlaboratory standard deviation for the Seebeck coefficient was ≈ ± 4 % for Bi2Te3 and for ≈ ± 8 % for constantan throughout the temperature range.

• Oak Ridge National Laboratory (ORNL) and the International Energy Agency (IEA) - Implementing Agreement on Advanced Materials for Transportation (AMT)

(2013) [2]:

• 8 laboratories in the temperature range to 323 K to 498 K for both n- and p-type Bi2Te3 materials and included electrical resistivity measurements.

• The interlaboratory standard deviation was ≈ ± 6 % for the Seebeck coefficient throughout the temperature range.

• ORNL IEA-AMT (2015) [3]:

• 11 laboratories in the temperature range 300 K to 773 K compared the electrical resistivity and Seebeck coefficient of n-type Half-Heusler

(Hf0.50Ti0.25Zr0.25NiSn0.99Sb0.01) and included heat capacity and thermal diffusivity measurements.

• This is also the only round-robin study that differentiated 2- and 4-probe arrangements. The difference between the mean values of each arrangement ranges from 11.3 % to 13.6 % through the temperature range

[1] N. D. Lowhorn, W. Wong-Ng, W. Zhang, Z. Q. Lu, M. Otani, E. Thomas, M. Green, T. N. Tran, N. Dilley, S. Ghamaty, N. Elsner, T. Hogan, A. D. Downey, Q. Jie, Q. Li, H. Obara, J. Sharp, C. Caylor, R. Venkatasubramanian, R.

Willigan, J. Yang, J. Martin, G. Nolas, B. Edwards and T. Tritt, Applied Physics A 94, 231 (2009).

[2] Hsin Wang, Wallace D. Porter, Harald Böttner, Jan König, Lidong Chen, Shengqiang Bai, Terry M. Tritt, Alex Mayolet, Jayantha Senawiratne, Charlene Smith, Fred Harris, Patricia Gilbert, Jeff W. Sharp, Jason Lo, Holger Kleinke & Laszlo Kiss, Journal of Electronic Materials 42, 654–664 (2013).

[3] Hsin Wang, Shengqiang Bai, Lidong Chen, Alexander Cuenat, Giri Joshi, Holger Kleinke, Jan König, Hee Woong Lee, Joshua Martin, Min-Wook Oh, Wallace D. Porter, Zhifeng Ren, James Salvador, Jeff Sharp, Patrick Taylor Alan J. Thompson, and Y. C. Tseng, J. Elec. Mater. 44, 4482 (2015).

R O U N D R O B I N S T U D I E S

NIST FDTR Instrument

Beam Path Diagram & Instrument Schematic

F R E Q U E N C Y D O M A I N T H E R M O R E F L E C TA N C E ( F D T R ) I N S T R U M E N TAT I O N

• FDTR is an optical laser based, modulated pump-probe, thermal measurement technique

• An 80 nm Au (2 nm Ti) transducer layer is sputter-deposited on the material of interest

• A modulated laser periodically heats the surface and the multilayer stack, inducing a corresponding periodic change in surface reflectivity; the relative phase from a reflected probe beam is measured using a lock-in amplifier

• Thermal conductivity, volumetric specific heat capacity, and thermal interface conductance can be obtained through modeling a fit of the phase of the reflected probe beam vs. the modulation frequency of the pump beam, where the probe and pump are coaxially focused on the sample film/Au transducer layer

• Sample stage accommodates 76.2 mm DIA thin films, multilayer systems, or bulk samples (@ RT); property maps can be obtained using the XY scanning platform

• The entire measurement is automated using custom LabVIEW code, optical component flippers, and motorized stages

Custom LabVIEW interface

F R E Q U E N C Y D O M A I N T H E R M O R E F L E C TA N C E ( F D T R ) M O D E L

𝐇 𝑟 , 𝜔 = 𝜅 ∥ 𝑟

𝜕𝑟

𝜕𝜃

𝜕𝑟 + 𝜅⊥

𝜕 2𝜃

𝜕𝑟 2 = 𝜌𝐶𝑝

𝜕𝜃

𝜕 𝑡 𝜌 𝐶 𝑝 : Volumetric specific heat capacity 𝜅 ⊥ : Cross-plane thermal conductivity 𝜅 ∥ : In-plane thermal conductivity d: Layer thickness

G: Thermal boundary conductance

E. Ziade, Rev. Sci. Instrum. 91, 124901 (2020) A.J. Schmidt et. al., Rev. Sci. Instrum. 80, 094901 (2009)

J. Yang et. al., Rev. Sci. Instrum. 84, 104904 (2013)

• After being matched at 40 MHz, the pump reference phase is recorded at each frequency

• The TR signal is then measured over the frequency range

• The leak pump phase is subtracted from the TR signal and the corrected data is then used for thermal modeling

• Each layer is modeled with a volumetric heat capacity, cross-plane and in-plane thermal conductivities, layer thickness, and thermal boundary conductance to the next layer. The surface temperature is numerically solved using the heat diffusion equation.

T R A N D U C E R D E P O S I T I O N : 4 W A V E I B D / B T D C L U S T E R S P U T T E R D E P O S I T I O N S Y S T E M

• Ion Beam Sputtering (also Ion Beam Deposition), is a thin film deposition process that uses an ion source to sputter a target material (metal or dielectric) onto a substrate.

• Because the ion beam is monoenergetic (ions possess the equal energy) and highly collimated, it enables extremely precise thickness control and deposition of very dense, high-quality, pinhole-free and very smooth films as compared to other PVD (physical vapor deposition) processes.

• Transfer robot and cassette elevators reduce contamination and allow fast cycle times.

• Cryo-pumped process with a base vacuum of 2.6 x 10-6 Pa (2 x 10-8 Torr)

• Rotating stage for high uniformity deposition of thin films

• Uniformity: 2 % (1 sigma)

• Quartz crystal thickness monitor

• Residual gas analyzer

• Ion guns for wafer pre-clean

• 12 fixed sputtering targets

• Maximum wafer diameter: 200 mm (8 in)

• Load capacity: 50 wafers

• Reproducible recipes

I O N B E A M S P U T T E R D E P O S I T I O N

NIST IBD Tool

2 1

3 4 𝜌 = 𝑅𝑆𝑡

I. Miccoli, J. Phys.: Condens. Matter 27, 223201 (2015).

L. J. Swartzendruber, NBS Technical Note 199 (1964).

D. E. Vaughan, Br. J. Appl. Phys. 12, 414 (1961).

𝑅𝑆 = 𝑅 𝐹 Τ(𝑡 𝑠) 𝐹 Τ(𝑠 𝑟, Τ∆ 𝑟)

s/2 s/2 s/2 s/2

Δ r 𝑒 −2𝜋𝑅𝑥

𝑅 + 𝑒 −2𝜋𝑅𝑦

𝑅 = 1

𝐹( Τ𝑠 𝑟, Τ∆ 𝑟) =

1 + 𝜂 𝜂 =

2ln(2) ln 𝛽1 2𝛽2

4𝛽3𝛽4𝛽5𝛽6 𝛽1 = 𝑦2 − 𝑦3 2 + 𝑥2 + 𝑥3 𝛽2 = 𝑦2 + 𝑦3 2 + 𝑥2 + 𝑥3 𝛽3 = 4𝑥3 𝛽4 = 4𝑥3 2 + 4𝑦3 𝛽5 = 4𝑥2 𝛽6 = 4𝑥2 2 + 4𝑦2 𝑥2 = Τ𝑠 𝑟

𝐷3 𝑥3 = Τ𝑠 𝑟

𝐷4 𝑦2 = 1 −

Δ 𝑟 − 𝑠 2𝑟 𝑠 𝑟

𝐷3 𝑦3 = 1 −

Δ 𝑟 + 𝑠 2𝑟 𝑠 𝑟

𝐷4

𝐷3 = 1 + Δ 𝑟 𝑠

2𝑟 𝑠 𝑟

𝐷4 = 1 + Δ 𝑟 𝑠

2𝑟 𝑠 𝑟 x y

𝐹( Τ𝑡 𝑠) → 1 𝑓𝑜𝑟 𝑡 ≪ 1𝜇𝑚

𝑅𝑥 = 𝑅12,43 + 𝑅21,34 + 𝑅43,12 + 𝑅34,21 𝜅𝑒 = 𝐿𝑜𝜎𝑒𝑇, E S T I M AT I N G T R A N S D U C E R T H E R M A L C O N D U C T I V I T Y F R O M E L E C T R I C A L R E S I S T I V I T Y

S Q UA R E 4 - P O I N T P RO B E ( C I RC U L A R SA M P L E ) C O R R EC T I O N FAC TO RS

𝐿𝑜 = 2.45 · 108 𝑊Ω𝐾2Wiedemann-Franz law:

T H I C K N E S S M E A S U R E M E N T S U S I N G X - R AY R E F L E C T O M E T R Y

• X-Ray Reflectometry is widely used for characterizing the thickness, roughness, and density of nanometer scale thin films.

• Best for thicknesses between 2 nm to 200 nm.

• Because it uses wavelengths of a similar or smaller scale relative to the thicknesses of the layers being studied, the resulting data has a relatively direct connection to the structure and therefore has straightforward SI traceability.

• This is a significant advantage over other techniques like spectroscopic ellipsometry (SE), whose results are somewhat more difficult to interpret.

• Different instrumentation and analysis software often produce divergent modeling results; NIST is addressing this problem by developing SRM thickness standards that can be used to calibrate XRR laboratory and Fab-line instrumentation.

• Access to other tools in our nanoFab (micron and mm scale layers):

• Filmetrics F50-UV Mapping Reflectometer

• Optical Profilometer: Sensofar

• Reflectometer: Nanometrics Nanospec

• Spectroscopic Ellipsometer: J.A. Woollam M-2000 DI

• Four Point Probe: Four Dimension 280DI

X - R AY R E F L EC TO M E T RY

Layer Thickness (nm) Density (g/cm3) Roughness (nm)

Au 78.855(13) 19.3 1

Ti 2.14(2) 4.5 0.75

N A N O C A L O R I M E T R Y

• Fully custom instrumentation

• Nanocalorimetry is capable of thermal measurements of very small samples at very fast rates with nanojoule sensitivity:

• Heat capacity

• Cross-plane thermal conductivity of thin films

• Reaction/phase transformation

• Fast heating/cooling rate, up to 106 K/s

• Small sample size – thin film or nanomaterials

• Fast thermal cycling, 1 s for a cycle; 10,000s of cycles in a day

• Measurement procedure: a current pulse is applied and measured through a precision resistor; the voltage drop across the heater provide an instantaneous measure of chip resistance and power.

• The acquired data are post-processed to calculate apparent heat capacity by subtracting the heat loss from applied power and then subtracting the heat capacity of the bare chip.

• Nanocalorimeter fabrication: The nanocalorimeter sensor has a 100 nm thick platinum heater suspended on a 100 nm thick silicon nitride membrane in a silicon frame with a 10 nm Ta as adhesion layer. The low stress SiNx membrane was deposited by low pressure chemical vapor deposition (LPCVD), the metal layer was patterned by lift-off photolithography and e-beam evaporation, and the silicon is back etched leaving an unsupported SiNx membrane following backside patterning and reactive-ion etching (RIE) through the SiNx membrane.

0.5 mm

Feng Yi, David LaVan, Appl. Phys. Rev. 6, 031302 (2019)

N A N O C A L O R I M E T R Y + F D T R

Feng Yi, David LaVan, Appl. Phys. Rev. 6, 031302 (2019)

• Nanocalorimeters are small and can be readily modified to integrate with most modern instruments such as FDTR, X-ray, SEM, TEM, etc. Only electrical feedthroughs are required to function.

• Nanocalorimetry chips are fabricated in-house, so custom and unique designs/shapes/capabilities are possible.

• We are developing compatible chips to combine our nanocalorimetry measurements with FDTR, providing:

• Measured thermal properties of transducer films rather than literature values for fixed FDTR model parameters

• Measured thermal properties of some layers in a multilayer stack

(step fabrication directly on different membranes)

• Accelerate the thermal cycles of a multilayer sample stack, in combination with FDTR and structural analysis, would enable studies on interface adhesion/bond integrity and thermal interface property changes under rapid thermal cycling conditions.

NIST Nanocalorimeter Instrument and Sample Holder

The phase transitions of DPPC (lipid coating) measured in air with an interval between cycles of 0.2 s.

The phase transitions of DPPC (lipid coating) measured in air with an interval between cycles of 3.1 s.

A rapid chip-based thermal measurement that allows repeated cycles to probe thermal stability and kinetics of materials.

The data shown here is from multiple cycles acquired within a few seconds to extract the kinetics of hydration for a

DPPC lipid coating; it is too rapid to be quantified by conventional DSC.

• Continue developing Frequency Domain Thermoreflectance (FDTR) measurements that provide reliable in situ thermal property data for wide bandgap semiconductors, metals, thermal interface materials, and heat spreaders, by developing new relevant calibration reference materials

• Conduct foundational information gathering needed to develop an interlaboratory study for thin film thermal measurements

• Upgrade FDTR instrument with selectable dual wavelength probe configuration (for Au and Al transducers)

• Design new temperature dependent vacuum sample chamber for FDTR instrument

• Combine nanocalorimetry measurements with FDTR, providing:

• Measured thermal properties of transducer films rather than literature values for fixed FDTR model parameters

• Measured thermal properties of some layers in a multilayer stack (step fabrication directly on different membranes