THREADS_FAQ_20230106.pdf

Technologies for Heat Removal in Electronics at the Device Scale (THREADS)

HR001123S0013

Frequently Asked Questions (FAQs) Updated as of 1/6/2023

1. Does DARPA believe that Phase 3 power density metrics can be achieved with today’s gallium nitride (GaN) electrical characteristics, or are emerging GaN device structures and materials (DREAM, H2) required?

a. It is anticipated that device engineering may be required to support the high voltage and current density required to meet the power density objective. It is anticipated that this may be achieved through electro-thermal codesign/co-optimization to meet the transistor RF performance and robustness metrics.

2. Is heterogeneous integration in scope and in the spirit of the program?

a. It depends on how you define heterogeneous integration (HI). If you define HI as using different materials within the transistor, then HI is in the spirit of the program.

3. From the manufacturability perspective, would phasing in epitaxial structure changes over time be acceptable?

a. Yes, as long as you can meet the program metrics defined in Table 1 of the Broad

Agency Announcement (BAA) (page 14).

4. How much phonon engineering modelling do you want to see?

a. The development of phonon engineering modelling techniques is not within the spirit of the program, but using them to design the transistor is within the spirit of the program.

5. Should proposers define approaches and milestones for validating/verifying thermal resistance at interfaces?

a. Proposers may define approaches and proposed defined milestones for validating/verifying/reducing thermal boundary resistance, since thermal boundary resistance is one of the elements required to reduce transistor thermal resistance.

6. Does the fabrication process need to be at wafer scale? For example, is a 1 cm2 epi test article material OK as opposed to an entire wafer?

a. The fabrication process does not need to be wafer scale. A small test article is appropriate if there is a path to a reproducible wafer scale process.

7. Any constraint on wafer size to be delivered?

a. No

8. Is there any requirement on die thickness?

a. No

9. Why is there no metric for spreading resistance in addition to thermal resistance? Thinning the buffer makes the thermal resistance smaller but does deteriorate spreading resistance.

a. Thermal resistance is three dimensional (in plane/spreading and out of plane). Per Table 1 of the BAA (page 14), these are proposer defined metrics so it is acceptable to include a spreading resistance metric.

10. Although the BAA focuses on thermal improvements, the test vehicle requires a transistor with

81 W/mm output power, which has implications in gain, bandwidth and non-thermal reliability (stressors like high current or high fields). Is process development related to non-thermal failures such as thick metal, airbridges, electromigration, and passive components, such as thin film resistors and capacitors, within the spirit of the BAA?

a. Yes, while the BAA’s primary focus is thermal, it is in the context of achieving robust, high power density radio frequency (RF) performance. Per the BAA (page 12), it is anticipated that electro-thermal co-design/co-development/co-optimization approaches will be required to guide device optimization. This includes addressing the thermal and non-thermal failure mechanisms required to meet the robustness metric.

11. Why is the W/mm BAA metric the same for a transistor and the power amplifier? Can we de-embed for output matching network loss in the power amplifier (PA) to calculate transistor W/mm?

a. 81 W/mm is a transistor metric. When a PA is measured, de-embedding of the output matching network loss would be acceptable.

12. Is DARPA expecting a fully designed MMIC with 50-ohm matching networks that account for material differences of a THREADS device by Month 18? End of Phase deliverables include thermal test structures, multi-finger transistor cells and PAs/standard evaluation circuits (SECs) -do we need a MMIC as a deliverable too?

a. No, a 50-ohm PA MMIC is not required. However, as stated in the BAA (page 16), an SEC deliverable is required, which will be used for robustness testing.

13. Will AFRL be providing common electrical and test structures to all performers for fabrication?

a. No, AFRL will not provide a test coupon. Per the BAA (page 13), development of electrical and test structures should be performed in collaboration with AFRL.

14. For the intrinsic and extrinsic thermal paths that you discussed, what is included in each path?

For example, is the substrate resistance part of the intrinsic or extrinsic thermal resistance?

a. Intrinsic is the epilayer structure and includes the substrate, per Table 1, footnote 1 in BAA (page 14). Extrinsic is transistor topology (e.g., gate pitch, segmented gate, etc.)

and 2D/3D cooling structures that are part of the transistor. DARPA is not looking for a packaging-type solution in the THREADS program.

15. What is considered external packaging? For example, does die singulation and encapsulation in a high thermal conductivity material constitute external packaging?

a. External packaging is outside of the transistor and epilayer/substrate stack. For example, embedding completed transistors in a high thermal conductivity material constitutes external packaging.

16. Are heat sinks appropriate?

a. External heat sinks are not within the spirit of the BAA.

17. Would thermoelectric coolers be considered a viable program approach?

a. Yes, as long as thermoelectric cooling can be done within the transistor or epilayer stack and not at the transistor package level. Package-level cooling approaches are not within the spirit of the THREADS program.

18. Is an approach based on a liquid-cooled substrate acceptable?

a. No, the THREADS program is focused on transistor level reduction of thermal resistance (i.e., moving heat away from the transistor channel hotspot to the back of the chip).

19. Are wafer bonded substrates appropriate?

a. Yes

20. In the past years, a lot of work has been done in the GaN-on-diamond area. If we choose to work in this area, do we have to propose something new?

a. Yes. You would need to justify how you would reduce the thermal boundary resistance between GaN and diamond, in addition to other approaches needed to meet BAA metrics.

21. What do you mean by “immature transistor technologies” in the context of the program scope?

a. Transistor technologies that do not meet state -of-the-art (SOA) as defined in the metrics table. As stated in the BAA (page 12), one example would be an all-diamond transistor.

22. Do we have to measure the thermal resistance of the epi stack and outside device prior to proposal submission, or is this done in the first phase of the program?

a. No, the measurement is encouraged but not required at the proposal stage. However, the proposer defined baseline measurement will be expected by the first quarterly phase review (QPR).

23. Is the proposal team required to propose thermal characterization work? Do proposers need to include AFRL and NIST as part of their team?

a. Yes, per BAA, thermal characterization work must be proposed and during the program should be coordinated with the independent verification and validation (IV&V) team.

Proposers do not need to include AFRL/NIST as part of their team since they will be performing IV&V of performer results.

24. In Table 1, footnote 1, it says channel mobility > 1000 cm2/V-s. Is this a strict requirement for devices?

a. Yes

25. Are there any constraints on voltage? For example, AFRL is set up for a maximum voltage of 250

V. What if the required voltage is higher than that, especially for 81 W/mm.

a. No, there are no constraints on voltage. DARPA will work with AFRL to upgrade test capabilities, as required.

26. Is 1000-hour RF stress test required?

a. Yes, however this test does not have to be completed for all 20 deliverable devices.

AFRL will perform robustness validation testing on select delivered devices.

27. Would high voltage test bench development of the 1000-hour RFOLT stress test be within scope?

a. Yes, but proposers must justify development costs required to meet program metrics.

28. Within the presentation today, it was stated that the multi-finger transistor cells should have a minimum of 6 fingers, and the gate width and pitch can be proposer defined. On page 14 of the BAA it does not specify a minimum # of fingers, only that total gate periphery is 600 µm. Should we follow BAA guidance?

a. Follow BAA guidance. Multi-finger transistors are required. In Table 1, footnote 7, 6 fingers are used as an example.

29. What is base plate temperature used in the document?

a. 75oC

30. If new approaches to electrical are required, why are transistor/PA power density and reliability go/no-go metrics used after only 18 months of development? Most approaches addressing TC1 and TC2 will impact electrical modeling of the transistor and PA matching that appear very aggressive after 18 months.

a. The Phase 1 goals are a modest stretch from what has been demonstrated today.

Go/No-Go metrics were established to track progress.

31. Are the THREADS transistors, test vehicles, and SECs required to meet export/import controls due to power density level?

a. The performer will be required to identify export controls. DARPA is not responsible for making those claims. Performers will need to develop a CUI Control Plan (CCP) to outline their relationship with vendors and how the company will protect CUI from disclosure.

DARPA will not issue ITAR guidance, and the performers will be expected to review the USML, and identify the ECCN or other specific triggers. If the program crosses those thresholds, the performance will be restricted in accordance with the USML.

32. You mentioned a dollar threshold that triggers certain additional documentation and regulations. Can you please clarify the amount and documentation required? Does the $7.5M threshold apply to all potential awards in aggregate — in the event two awards are made to one small business?

a. Refer to Note 1 in the BAA (pages 28-29). For any procurement contract greater than or equal to $2M, proposers are required to submit certified cost and pricing data. There is an exception for small business and non-traditional defense contractors, who are exempt from the requirement up to $7.5M (Class Deviation 2022-O0005, Revision 1 – Pilot Program for Streamlining Awards for Innovative Technology Projects). These thresholds are contract-specific and do not apply in aggregate should multiple awards be made to a singular entity.

33. Can a proposer partner with a Government lab?

a. Yes, refer to Section III. Eligibility Information of the BAA (page 18) and Section IV.

Application and Submission Information of the BAA (pages 20 – 37) for proposal preparation guidance.

34. Are non-US companies or non-US universities allowed to participate or be subcontractors in

THREADS?

a. Yes, but per Section III. Eligibility Information of the BAA (page 19) such participants must comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

35. Can we use our foundry of choice?

a. Yes.

36. Can a proposer be on two proposing teams?

a. Yes, each proposal will be evaluated independently against the evaluation criteria specified within the BAA.

37. Can you describe in more detail the prohibition against flip-chip and packaging development? Flip chip and packaging is explicitly excluded in the BAA (page 12). However, 2-D and 3-D cooling structures are sought. Is it permitted to use wafer bonding or die to wafer bonding as part of a device-level fabrication process to make 2-D or 3-D cooling structures?

a. Flip chip and packaging are next level (post transistor) assembly solutions and per the BAA (page 12) are not in line with the objectives of this BAA. We are looking for 2D and 3D structures/solutions that are part of the transistor/epi-layer stack to move waste heat from the channel (hot spot) to the next level of assembly. In that regard, wafer bonding as part for the device fabrication process would be considered an acceptable proposed solution.

38. Can you describe in more detail how the gate periphery is calculated? The BAA (page 14) states “minimum total gate periphery = 600 mm (e.g., 6 x 100 mm) with a maximum gate pitch of 50 mm”. How is the gate periphery calculated for a device with multiple, stacked 2DEG channels?

a. Gate periphery is total effective physical / electrically active gate width and is independent of the number of stacked channels for a multi-channel FET. A single channel or multi-channel FET would have the same gate width/periphery.

39. In Figure 4 of BAA (page 15), the Technical Status reports are listed as quarterly. In section F immediately below (page 15), technical status reports are listed as monthly. Could you please clarify if the technical status reports were to be monthly or quarterly?

a. Monthly technical status updates and quarterly technical reports are both required for the THREADS program according to the F. Deliverables section in the BAA (page 15). The monthly updates could be in the form of bullets sent via email. The quarterly reports are more comprehensive and could be the briefing materials submitted for and presented during the quarterly progress reviews.

40. On page 30 of the BAA it says: “University proposers requesting a grant, cooperative agreement, or Other Transaction for Research do not need to use the MS Excel DARPA Standard Cost

Proposal Spreadsheet. Instead, a proposed budget and justification may be provided using the SF-424 Research & Related Budget forms provided via https://www.grants.gov.” Does this mean that we can utilize Research & Related Budget forms instead of the DARPA spreadsheet? Can subcontractors utilize the Research & Related Budget forms?

a. The potential award instruments for the THREADS program are procurement contracts and Other Transactions (OT). Any university prime proposers requesting an OT for Research may use the Research and Related Budget forms provide via grants.gov, but all subcontractors must complete the DARPA cost excel spreadsheet.

41. If we use the Research & Related Budget forms, is there a preferred way that we meet the task/month summary requirements mentioned above since this budget template does not breakdown into months/tasks? Could that information be included in separate graphics/summaries while still providing the Research & Related Budget?

a. Yes, that information may be included in a separate document.

https://www.grants.gov/