HR001123S0013.pdf

HR001123S0013

Broad Agency Announcement Technologies for Heat Removal in Electronics at the Device

Scale (THREADS) Microsystems Technology Office

November 18, 2022

Table of Contents

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description A. Background B. Program Description C. Program Structure D. Technical Areas E. Schedule/Milestones F. Deliverables G. Government Furnished Equipment/Property/Information H. Intellectual Property

II. Award Information A. General Award Information B. Fundamental Research

III. Eligibility Information A. Eligible Applicants

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

2. Other Applicants B. Organizational Conflicts of Interest C. Cost Sharing/Matching

IV. Application and Submission Information A. Address to Request Application Package B. Content and Form of Application Submission

1. Abstract Format

2. Full Proposal Format

3. Proprietary Information

4. Security Information

a. Program Security Information

b. Controlled Unclassified Information (CUI)

i. CUI Proposal Markings

ii. CUI Submission Requirements

c. Unclassified Submissions

5. Disclosure of Information and Compliance with Safeguarding Covered Defense

Information Controls

6. Human Subjects Research (HSR)/Animal Use

7. Approved Cost Accounting System Documentation

8. Section 508 of the Rehabilitation Act (29 U.S.C. § 749d)/FAR 39.2

9. Small Business Subcontracting Plan

10. Intellectual Property

a. For Procurement Contracts

b. For All Non-Procurement Contracts

11. Patents

12. System for Award Management (SAM) and Universal Identifier Requirements

13. Funding Restrictions

C. Submission Information

1. Submission Dates and Times

a. Abstract Due Date

b. Full Proposal Date

c. Frequently Asked Questions (FAQ)

2. Abstract Submission Information

3. Proposal Submission Information

a. For Proposers Requesting Technology Investment Agreements

b. For Proposers Requesting Contracts or Other Transaction Agreements

c. Classified Submission Information

4. Other Submission Requirements

V. Application Review Information A. Evaluation Criteria

1. Overall Scientific and Technical Merit

2. Potential Contribution and Relevance to the DARPA Mission

3. Cost Realism

B. Review and Selection Process

1. Review Process

2. Handling of Source Selection Information

3. Federal Awardee Performance and Integrity Information (FAPIIS)

VI. Award Administration Information A. Selection Notices

1. Abstracts

2. Proposals

B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. Solicitation Provisions and Award Clauses, Terms and Conditions

3. Controlled Unclassified Information (CUI) and Controlled Technical Information

(CTI) on Non-DoD Information Systems

4. Representations and Certifications

C. Reporting D. Electronic Systems

1. Wide Area Work Flow (WAWF)

2. i-Edison

3. Vault

4. DARPA Embedded Entrepreneurship Initiative (EEI)

VII. Agency Contacts VIII. Other Information

A. Proposers Day B. University Student and Researcher Funding

ATTACHMENT 1: Cost Volume Proposer Checklist ATTACHMENT 2: Proposal Summary Slide Template ATTACHMENT 3: General MTO Controlled Unclassified Information Guide (CUIG)

ATTACHMENT 4: Other Transactions (OT) Certifications Template ATTACHMENT 5: DARPA Standard Cost Proposal Spreadsheet

PART I: OVERVIEW INFORMATION

Federal Agency Name: Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title: Technologies for Heat Removal in Electronics at the Device Scale (THREADS)

Announcement Type: Initial Announcement Funding Opportunity Number: HR001123S0013 Catalog of Federal Domestic Assistance Numbers (CFDA): 12.910 Research and

Technology Development Dates: (All times listed herein are Eastern Time) o Posting Date: November 18, 2022 o Proposers Day: November 30, 2022 o Abstract Due Date: December 22, 2022 o FAQ Submission Deadline: January 31, 2023 o Proposal Due Date: February 17, 2023 o Estimated period of performance start: August 2023

Concise description of the funding opportunity: The THREADS program seeks to develop technologies that overcome transistor thermal limitations and realize robust high-power density devices that operate near their fundamental electronic limit of radio frequency (RF) output power.

Anticipated Funding Available for Award: Approximately $60M of total funding is anticipated for awards made against this BAA.

Anticipated individual awards: Multiple awards are anticipated.

Anticipated funding type: 6.2 Types of instruments that may be awarded: Procurement contract or Other

Transaction Agency contact:

o Dr. Thomas Kazior, Program Manager BAA Coordinator: HR001123S0013@darpa.mil

DARPA/MTO

ATTN: HR001123S0013

675 North Randolph Street Arlington, VA 22203-2114 mailto:name@darpa.mil

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using the procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016 and 2 C.F.R. § 200.203. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing. Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the System for Award Management (SAM) website, under the Contract Opportunities link, at https://sam.gov/, and, as applicable, the grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA.

The Microsystems Technology Office at DARPA seeks innovative proposals to develop technologies that will overcome the thermal limitations preventing transistors from operating reliably at RF output power density close to their fundamental electronic limit. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

A. Background

Radar and communication systems are ubiquitous in both military and commercial applications.

Performance of these systems depends on the signal-to-noise (S/N) ratio achievable at the receiver, which is proportional to the RF output power of the transmitter. In Department of Defense (DoD) platforms, where the RF aperture is often limited in size, the only practical approach for improving system performance (e.g., increasing radar or communication system range) therefore is by increasing the RF output power of the transmitter power amplifier (PA). The latter is directly proportional to the output power density of the PA transistor (i.e., transistor output power divided by transistor periphery width).

The operating output power densities achieved in today’s DoD RF transmitters are thermally limited to values substantially below theoretical electronic limits. Wide bandgap (WBG) transistors, such as gallium nitride (GaN), were developed specifically to improve output power density in PAs. Indeed, GaN provides a 5X improvement in RF power output (Pout) compared to the previous generation transistor technology, gallium arsenide (GaAs). But while it is known that a further order-of-magnitude increase in Pout is possible in GaN,1,2 this cannot be realized in sustained operation today due to excessive waste heat in the transistor channel layer. The waste heat, generated because DC-to-RF conversion efficiency in GaN transistors is less than unity (e.g., 1 Prof. Umesh Mishra (UCSB), private communication based on work funded by ONR and DARPA.

2 Hollis, M., et al., “Ultrawide-Bandgap Semiconductors: Materials, Devices, and Applications,” DARPA 2021 Electronics Resurgence Initiative Summit, Oct. 2021.

~60% at X-band),3 causes elevated channel temperatures (see Figure 1) and results in rapid transistor performance and lifetime degradation (device lifetime is cut in half for every 10 oC rise in channel temperature4). As illustrated in Figure 1, the maximum channel temperature for safe operation in GaN is 225 oC.

Figure 1. Lifetime limitation of GaN transistor technology5

While GaN transistors has been shown to operate in pulsed mode at high power (Pout = 40 W/mm),6 operating these devices in PAs under real-world waveforms (long pulse-width, ~30% duty cycle) would result in unacceptably high channel temperature (>450 °C,7 equating to a five orders of magnitude reduction in transistor lifetime). Achieving the transistor output power near the GaN fundamental electronic limit while maintaining a channel temperature below the nominal maximum temperature (225 oC) requires a significant reduction in thermal resistances of the transistor (to improve heat removal from the channel) while preserving the superior electronic properties of WBG semiconductors.

Through its investment in prior programs like Dynamic Range-enhanced Electronics and Materials (DREaM),8,9 DARPA has successfully increased transistor power density, leading to even greater concerns over thermal dissipation. Programs like Thermal Ground Plane (TGP) developed novel packaging approaches (e.g., phase change heat spreaders) to improve thermal management, but

3 Wolfspeed, “50-W; 7.9 – 9.6-GHz; 50-ohm; Input/Output-Matched GaN HEMT,” CGHV96050F2 datasheet, Feb.

2021.

4 DARPA Thermal Management Technologies (TMT) Program Completion Report (PCR).

5 Derived with permission based on data from DARPA performer 6 Wu, Y.F., et al., “40-W/mm Double Field-plated GaN HEMTs” 2006 64th Device Research Conference, 2006, pp.

151-155.

7 Internal calculation, DARPA MTO.

8 Chen, Y.K., et al., “Dynamic Range-enhanced Electronics and Materials (DREaM),” CS MANTECH, 2019.

9 Kazior, T., Jones, G., Chang, T. H., "Emerging Millimeter-Wave Device Technology - Next Generation GaN and Beyond," 2022 IEEE/MTT-S International Microwave Symposium - IMS 2022, 2022.

these techniques did not address thermal resistance within the transistor.10 On the other hand, the Near Junction Thermal Transport (NJTT) and Intrachip/Interchip Enhanced Cooling (ICECool) programs provided device-level cooling by incorporating high thermal conductivity substrates (e.g., GaN on diamond) as well as microfluidic cooled backplanes, to moderate channel temperature at high power density.11 But while promising, NJTT enabled just a 3X increase in power density12 and did not improve thermal resistance of the GaN transistor epilayers stack or at the interface to the diamond substrate.

In contrast, THREADS will focus on achieving high power density through reduction in transistor thermal resistance, both within and outside the intrinsic device, as shown in Figure 2. In this example, the intrinsic device consists of the epilayer stack and individual gate finger, whereas the extrinsic (i.e., outside the intrinsic) device consists of a multi-finger transistor and includes the gate, drain and source fingers, pads, and buses. The extrinsic device includes heat spreading layers or structures next to the intrinsic device. The combined thermal resistance of the device is modeled as the parallel combination of the intrinsic (within) and the extrinsic (outside) thermal resistances.

Figure 2: Schematic layout and cross section of (left) extrinsic and (right) intrinsic device regions. The red areas along the gate fingers indicate regions of waste heat generation.

In particular, THREADs will address the following two key (2) technical challenges (TCs):

TC 1: Reducing thermal resistance within the device while maintaining good channel current transport properties.

Transistor epilayer design is currently optimized to achieve good channel current transport properties (e.g., GaN HEMT electron mobility >1500 cm2/V-s), as this is a key requirement in a PA for high Pout and high efficiency. State-of-the-art (SoA) approaches achieve such mobility by epi-layer designs that focus on reducing channel defect density. In particular, GaN transistors are grown on SiC or other heterogeneous substrates, requiring nucleation layers and thick buffer

10 Bar-Cohen, A., et al., “Near-Junction Thermal Management for Wide Bandgap Devices,” 2011 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2011.

11 Bar-Cohen, A., et al., "Near-junction microfluidic thermal management of RF power amplifiers," 2015 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS), 2015.

12 Tyhach, M., et al., “S2-T3: Next generation gallium nitride HEMTs enabled by diamond substrates,” 2014 Lester Eastman Conference on High Performance Devices (LEC), 2014.

layers between the channel and substrate in order to achieve high electron mobility. But these layers inherently increase thermal resistance, in large part due to the thermal boundary resistances (TBR) between layers that inhibit heat flow between dissimilar materials. For example, the large TBR between the GaN buffer and SiC substrate has been shown to increase peak channel temperature by over 100 oC.13 As a result, the thermal resistance of a typical SOA GaN-on-SiC transistor is 3X higher than that of the underlaying SiC substrate.14

TC 2: Moving heat away from high power transistors more efficiently without degrading RF performance. Heat spreading is the means by which the waste energy produced by the transistor is conducted away from the transistor channel “hot spots.” Two approaches are typically used:

1. Increased gate pitch in a multi-finger transistor cell spreads the waste heat over a larger area reducing thermal resistance and hot spot temperature. Increasing gate pitch from 20 μm to 60 µm reduces thermal resistance by 2X from 20 oC-mm/W to 10 oC-mm/W but degrades power density proportionally.15

2. Thermal via holes16 provide a parallel path for spreading waste heat from the channel to the backside heatsink, reducing thermal resistance by 20%, albeit at a reduced heat conduction efficiency since thermal vias are not located near the transistor hot spots.

Both approaches require increasing the footprint of a multi-finger transistor, which increases parasitic resistance and capacitance, resulting in degradation of transistor gain and efficiency.

Thus, approaches that increase heat spreading without degrading RF performance are necessary.

B. Program Description

The THREADS program seeks to develop technologies that overcome transistor thermal limitations and realize robust high-power density devices that operate near their fundamental electronic limit of radio frequency (RF) output power. Specifically, the THREADS program will demonstrate:

High efficiency, X-band (8-12 GHz) transistors and PA test vehicles whose output stage transistors have an output power density of 81 W/mm;

8X reduction in transistor thermal resistance (see Figure 3 below); and, Reliable operation with a predicted mean-time-to-failure (MTTF) of 106 hours at 225 oC channel temperature (comparable to today’s production GaN operated at ~5 W/mm output power density).

13 Riedel, G., et al., “Reducing Thermal Resistance of AlGaN/GaN Electronic Devices Using Novel Nucleation Layers,” IEEE Electron Device Letters, Vol. 30, No. 2, Feb. 2009.

14 Prof. Samuel Graham, University of Maryland, based on work from ONR MURI: Leveraging a New Theoretical Paradigm to Enhance Interfacial Thermal Transport in Wide Bandgap Power Electronics 15 Darwish, Al., et al., “Thermal Resistance Calculation of AlGaN–GaN Devices,” IEEE Transactions, Vol. 52, No.

11, Nov. 2004.

16 Mohanty, S., et al., “Thermal Management of GaN-on-Si High Electron Mobility Transistor by Copper Filled Micro-Trench Structure,” Nature, Scientific Reports, vol. 9, Dec. 2019.

As shown in Figure 3, the thermal resistance of SoA devices limits the ability of wide bandgap transistors to operate with high power density.

Figure 3. THREADS output power density and thermal resistance goals compared to typical GaN and GaAs transistors.

Significant advances have recently been made in WBG and ultra-wide bandgap (UWBG) semiconductor materials, thermal interface engineering and advanced three-dimensional heat spreading. The THREADS program seeks to apply these recent insights to realistic submicron transistor geometries to reduce transistor thermal resistance and enable operation at high power density while maintaining a maximum channel temperature of 225 oC. Through a combination of material thermal resistance improvements, novel transistor topologies and heat spreading layer(s)/structures, the THREADS program will demonstrate a net 8X reduction of transistor thermal resistance.

TC 1: Reducing thermal resistance within the device while maintaining good channel current transport properties.

THREADS seeks to reduce interfacial and thin film thermal resistance within the intrinsic device (epitaxial layer stack). Approaches may include but are not limited to:

Novel nucleation and buffer layer growth processes to reduce defect density at substrate-epilayer (e.g., GaN-SiC) interfaces and enable the use of thin buffer layers;17

17 Chen, D-Y., et al., “Microwave Performance of ‘Buffer-Free’ GaN-on-SiC High Electron Mobility Transistors,” IEEE Electron Device Letters, Vol. 41, No. 6, June 2020.

Phonon bridges (e.g., controlled defect incorporation at heterointerfaces;18 nano-structuring techniques at heterogeneous interfaces;19 ballistic thermal injection;18 strain-enhanced thermal boundary conductance19);

Phonon engineering through the use of specific isotopes (such as nitrogen-15 vs.

nitrogen-14)20 during epitaxial growth;

Graded channel GaN HEMTs that uniformly spread the electrons in the channel to reduce scattering, lower electron temperature, and enhance saturation velocity;21

Digital AlN/GaN alloys to increase channel bandgaps while reducing alloy scattering, channel/buffer thermal resistance and interface scattering and lowering thermal boundary resistance;19

Alternate high thermal conductivity substrates (e.g. diamond,10 AlN) in combination with approaches that reduce interfacial thermal resistance;

Alternate high thermal conductivity buffer layers (e.g. AlN);22 and, Homoepitaxial growth (e.g. AlN/AlN).23

TC 2: Moving heat away from high power transistors more efficiently without degrading RF performance.

THREADS seeks to develop approaches to spread waste heat and reduce transistor thermal resistance to maintain channel temperature of 225 °C. Approaches may include but are not limited to:

Topside and/or embedded 2D and 3D cooling structures with high thermal conductivity (e.g.

diamond, AlN, c-BN) and low thermal boundary resistance that do not degrade RF performance;24 and, Novel gate layouts and multi-finger transistor topologies, such as a segmented gate25 or ring HEMT,26 uniform, nonuniform and honeycomb geometries, combined with 3D thermal conduction geometries and heterogeneous material integration to spread heat efficiently reducing hot spot peak temperatures.

DARPA anticipates that THREADS proposals may incorporate a variety of approaches to solve TC1 and TC2 to provide an overall 8X reduction in transistor thermal resistance. For example, a

18 Hopkins, P., “Thermal transport in UWBG materials and interfaces: Challenges in measurements and understanding,” GOMAC 2022, Miami, Fl, March 2022.

19 “Leveraging a New Theoretical Paradigm to Enhance Interfacial Thermal Transport in Wide Bandgap Power Electronics,” ONR MURI, Year 4 Review, June 2022.

20 Khurgin, et al., “Isotope disorder of phonons in GaN and its beneficial effect on high power field effect transistors,” Applied Physics Letter, Vol. 93, 2008.

21 Moon, J-S., et al, “W-Band Graded-Channel GaN HEMTs With Record 45% Power-Added-Efficiency at 94 GHz,” IEEE Microwave and Wireless Components Letters, 2022.

22 Hickman, A., et al., “First RF Power Operation of AlN/GaN/AlN HEMTs With >3 A/mm and 3 W/mm at 10 GHz,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 121-124, 2021.

23 Alvarez-Escalante, G., et al., “High thermal conductivity and ultrahigh thermal boundary conductance of homoepitaxial AlN thin films,” APL Mater., Vol. 10, 2022.

24 Malakoutian, M., et al., “Development of Polycrystalline Diamond Compatible with the Latest N-Polar GaN mm- Wave Technology,” Cryst. Growth Des., Vol. 21, No. 5, 2021.

25 Darwish, A., et al., “AlGaN/GaN HEMT With Distributed Gate for Channel Temperature Reduction,” IEEE Trans. on MTT, Vol. 60, No. 4, April 2012.

26 Darwish, A., et al., “A Ring-HEMT for Improved GaN MMIC Thermal Dissipation,” 2013 IEEE MTT-S International Microwave Symposium Digest (MTT), 2013.

3X improvement in intrinsic thermal resistivity of the epilayers and thermal interfaces (TC1) would require an additional 5X reduction of extrinsic thermal resistance due to device thermal improvements (TC2) (i.e., 3X reduction in parallel with 5X reduction). Alterations to materials in the epilayer stack that allow for a greater reduction (e.g., 4X) in intrinsic thermal resistivity would only require a smaller (e.g., 4X) additional reduction of extrinsic thermal resistance using device improvements. The methodology and rationale of the materials and device proposed are up to the proposers, but must meet or exceed the transistor thermal resistance reduction goals for each phase.

Because of the potential trade-offs between electrical and thermal performance, proposers are expected to incorporate electro-thermal co-design, modeling, and simulation to guide device optimization.

In addition to approaches that reduce transistor thermal resistance, approaches that reduce the amount of dissipated heat in high power density transistors (e.g., by increasing transistor efficiency while maintaining the same mode/class of transistor operation, such as class AB, as the baseline device) may be proposed, as long as clear calculations/simulations are provided to show that any additional metrics/goals proposed are consistent with the metrics/goals published in this BAA.

However, approaches such as external packaging solutions (e.g., microfluidics/jet impingement cooling, flip chip, etc.) and immature semiconductor technologies, such as all-diamond transistors, are not in line with the objectives of this BAA. In addition, proposers are encouraged to develop thermal management approaches that may be generalizable to future material systems (e.g., ultra-wideband semiconductors). Finally, while THREADS transistor and PA test vehicle metrics are set at X-band frequencies, the thermal solutions offered should be applicable to a broad range of frequencies. Proposers are encouraged to discuss the degree to which their technical approaches would be applicable to transistors and PAs operating at frequencies other than X-band.

C. Program Structure

THREADS is a 48-month, 3-phase program with an 18-month Phase 1 (base), 18-month Phase 2 (option), and 12-month Phase 3 (option) with one technical area. At the end of Phase 1 and Phase 2, options may be exercised, at the Government’s sole discretion, based on technical progress and funding availability. It is anticipated that the number of performers may diminish as options are exercised for progression into Phases 2 and 3 of the program.

D. Technical Areas

The THREADS program has one technical area that will focus on addressing the two major technical challenges. Performers must address both technical challenges in their proposal, showing how all metrics will be met simultaneously. Performance metrics are specified in Table 1. Note that Table 1 includes required proposer-defined metrics for inside and outside the intrinsic device thermal resistance.

The goal of Phase 1 (18 months) is to develop within the intrinsic device material structures (TC1) and outside of the intrinsic device heat spreading structures (TC2) to reduce transistor thermal resistance by 2.5X and demonstrate a reliable, efficient PA with a RF power density of 25 W/mm.

The goal of Phase 2 (18 months) is to optimize within the intrinsic device material structures (TC1) and outside of the intrinsic device heat spreading structures (TC2) to reduce transistor thermal resistance by 5X and demonstrate a reliable, efficient PA with a power density of 50 W/mm.

The goal of Phase 3 (12 months) is to scale the results of Phase 2 to demonstrate robust RF transistors and PAs with an 8X reduction in thermal resistance and 16X increase in RF output power density (to 81 W/mm).

DARPA expects to incorporate an independent, government-sponsored verification and validation (IV&V) team into the program. To ensure consistency in characterization, performers are expected to coordinate with this IV&V team and develop appropriate thermal test structures, multi-finger transistor cells, and SECs. Additionally, performers are expected to work with the IV&V team to identify associated thermal and electrical metrology techniques to characterize these test structures and devices. Thermal metrology techniques may include Raman spectroscopy, gate resistance thermometry, transient thermoreflectance, steady-state thermoreflectance (SSTR), time-domain thermoreflectance (TDTR), or frequency-domain thermoreflectance (FDTR). Table 1, footnote 7 provides an example of multi-finger transistor cells and SECs design and measurements minimum requirements. Transistor robustness will be evaluated using a 1000-hour RF stress test measured on multiple SECs (Table 1, footnote 8). Proposers should provide detailed information in their proposal on how they plan to develop and characterize the thermal test structures, multi-finger transistor cells, and SECs under this program.

Table 1. THREADS Metrics

Metric TC Units SOA Phase

Phase

Phase

Inside intrinsic device (material) thermal resistance1

1 o C-mm/W

Proposer Defined2 TBD4 TBD4 TBD4

Outside of intrinsic device heat spreading thermal resistance3

2 o C-mm/W

Proposer Defined2 TBD4 TBD4 TBD4

Transistor thermal resistance5 1, 2 o

C-mm/W X6 0.4X 0.2X 0.125X

Transistor/power amplifier Pout

7 1, 2 W/mm 5 25 50 81

Transistor/PA robustness8 2 % < 5 < 5 < 5 < 2

1. Measured on proposer-defined material thermal resistivity test structure and with proposer-defined measurement approach (e.g., time domain thermal reflectance (TDTR), micro Raman spectroscopy).

Test structures and measurement approaches should be coordinated with the government IV&V team.

Thermal resistance is measured from channel layer to bottom of substrate and includes thermal resistance of channel layer, buffer layer, substrate and interfaces. Channel mobility > 1000 cm2/V-s.

2. Proposer-defined inside the device thermal resistance metric based on proposer’s mature baseline GaN device. and required to achieve the THREADS transistor thermal resistance metrics.

3. Measured on proposer-defined outside the intrinsic device thermal resistivity test structure and with proposer-defined measurement approach. Test structures and measurement approaches should be coordinated with the government IV&V team.

4. Proposer-defined outside the intrinsic device thermal resistance metrics based on proposer’s approach and required to achieve the THREADS transistor thermal resistance metrics.

5. Measured on multi-finger transistors using proposer defined transistor thermal resistance test structures and with proposer defined measurement approaches. Test structures and measurement approaches should be coordinated with the government IV&V team. Thermal resistance measured from channel hot spot to bottom of substrate and includes within intrinsic device (material/epi stack) thermal resistance (TC1) and outside of intrinsic device heat spreading thermal resistance (TC2).

6. Proposer-defined value for thermal resistance based on proposer’s mature baseline GaN device technology.

7. Power density measured on multi-finger transistor cells and standard evaluation circuits (SECs, e.g., single-stage MMIC PA test vehicles); minimum total gate periphery = 600 m (e.g., 6 x 100 m) with a maximum gate pitch of 50 m; Pout density at peak PAE; PAE > 60% at 10 GHz with 20% bandwidth; 30% duty cycle; peak channel temperature: 225oC; Average power density measured on a minimum of 20 transistor cells and SECs across a minimum of 2 wafers.

8. Change in Id, Pout after 1000-hour CW RF stress test measured on SECs; SECs biased for Pout = 25, 50, 81 W/mm (Phase 1, 2 and 3 respectively) and maximum PAE at 10 GHz with a 20% bandwidth and peak channel temperature: 225oC; Robustness measured on a minimum of 20 SECs across a minimum of 2 wafers.

E. Schedule/Milestones

The THREADS program structure is shown in Figure 4. THREADS is a 48-month program with an anticipated start in August 2023. Program kickoff and quarterly review sessions or technical interchange meetings are mandatory and represent an opportunity to interact with the Government on planned work, specifics of the technical approaches, and any technical or programmatic items of concern.

The performers will construct a research program to meet or exceed all the metrics outlined in the metrics table. The program plan should include:

Program kickoff meeting to be held in-person at program start in Arlington, Virginia Quarterly Program Reviews, either via teleconference or at the performer’s site at the discretion of DARPA Design Reviews, held via teleconference, for electrical and thermal test structures and power amplifier (PA) test vehicles / standard evaluation circuits (SECs) including electrical and thermal test plans

Interim and end of phase delivery of appropriate electrical and thermal test structures and PAs/SECs for independent verification and validation by the government

Figure 4. THREADS Program Structure

F. Deliverables

It is expected that any resultant awards will require performers to deliver a detailed spend plan at program kickoff and execution of subsequent option awards, quarterly technical reports, monthly technical status updates, and monthly financial reports including updated expenditures. It is further expected that performers shall prepare and submit briefing materials and participate in quarterly progress reviews, either via teleconference or at the performer’s site at the discretion of DARPA.

All performers shall participate in and support an in-person kickoff meeting and in-person program-wide reviews held at least annually and scheduled at the Program Manager’s discretion.

Performers also will be expected to deliver design review packages including details of design, modeling, and simulation of all transistors, electrical and thermal test structures, and power amplifier test vehicles / SECs.

For end of phase deliverables, performers will deliver a minimum of twenty (20) of each of thermal test structures, multi-finger transistor cells, and PAs/SECs from more than one wafer for IV&V by government SMEs. All hardware deliverables must include test data showing that the metrics have been achieved. To ensure consistency in characterization, the performer, in consultation and collaboration with the government IV&V team, will design and fabricate appropriate thermal test structures, multi-finger transistor cells, and SECs and generate a test methodology and test plan.

This includes appropriate on-wafer test structures. End of Phase deliverables will be expected to be received by the government no less than six (6) weeks before end of phase to allow time for

IV&V.

G. Government Furnished Equipment/Property/Information

No Government Furnished Equipment, Property, or Information is expected to be provided for the effort solicited in this BAA.

H. Intellectual Property

Any use of proposer-defined intellectual property (patents, proprietary information, etc.) should be clearly marked as such within the proposal. Include all proprietary claims to the results, prototypes, intellectual property, or systems supporting the effort and/or necessary for the use of the research, results and/or prototype. It is desired that all technical data generated by the THREADS program be provided as deliverables to the Government with Unlimited Rights, or as applicable, Government Purpose Rights (GPR), and all hardware designs and documentation with a minimum of GPR. If there are no proprietary claims, this should be stated. For forms to be completed regarding intellectual property, see Section IV.B.10 and Section IV.B.1, “Section III.

Other Transaction Request”, if applicable.

II. Award Information

A. General Award Information

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers.

The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options.

Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases, as applicable.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information,” Sec. V.), and program balance to provide overall value to the Government. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications (see Section VI.B.4., “Representations and Certifications”). The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information. Proposals identified for negotiation may result in a procurement contract, grant, cooperative agreement, or other transaction, depending upon the nature of the work proposed, the required degree of interaction between parties, whether or not the research is classified as Fundamental Research, and other factors.

Proposers looking for innovative, commercial-like contractual arrangements are encouraged to consider requesting Other Transactions. To understand the flexibility and options associated with Other Transactions, consult http://www.darpa.mil/work-with-us/contract-management#OtherTransactions.

In accordance with 10 U.S.C. § 4022(f), the Government may award a follow-on production contract or Other Transaction (OT) for any OT awarded under this solicitation if: (1) that participant in the OT, or a recognized successor in interest to the OT, successfully completed the entire prototype project provided for in the OT, as modified; and (2) the OT provides for the award of a follow-on production contract or OT to the participant, or a recognized successor in interest to the OT.

In all cases, the Government contracting officer shall have sole discretion to select award instrument type, regardless of instrument type proposed, and to negotiate all instrument terms and conditions with selectees. DARPA will apply publication or other restrictions, as necessary, if it determines that the research resulting from the proposed effort will present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Any award resulting from such a determination will include a requirement for DARPA permission before publishing any information or results on the program.

For more information on publication restrictions, see the section below on Fundamental Research

B. Fundamental Research

It is DoD policy that the publication of products of fundamental research will remain unrestricted to the maximum extent possible. National Security Decision Directive (NSDD) 189 defines fundamental research as follows:

‘Fundamental research’ means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

http://www.darpa.mil/work-with-us/contract-management#OtherTransactions http://www.darpa.mil/work-with-us/contract-management#OtherTransactions

As of the date of publication of this solicitation, the Government expects that program goals as described herein may be met by proposed efforts for fundamental research and non-fundamental research. Some proposed research may present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Based on the anticipated type of proposer (e.g., university or industry) and the nature of the solicited work, the Government expects that some awards will include restrictions on the resultant research that will require the awardee to seek DARPA permission before publishing any information or results relative to the program.

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to determine whether the proposed research shall be considered fundamental and to select the award instrument type. Appropriate language will be included in resultant awards for non-fundamental research to prescribe publication requirements and other restrictions, as appropriate. This language can be found at http://www.darpa.mil/work-with-us/additional-baa.

For certain research projects, it may be possible that although the research to be performed by a potential awardee is non-fundamental research, its proposed subawardee’s effort may be fundamental research. It is also possible that the research performed by a potential awardee is fundamental research while its proposed subawardee’s effort may be non-fundamental research.

In all cases, it is the potential awardee’s responsibility to explain in its proposal which proposed efforts are fundamental research and why the proposed efforts should be considered fundamental research.

III. Eligibility Information

A. Eligible Applicants

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA.

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities, Small Businesses, Small Disadvantaged Businesses and Minority Institutions are encouraged to submit proposals and join others in submitting proposals; however, no portion of this announcement will be set aside for these organizations’ participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities.

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

a) FFRDCs http://www.darpa.mil/work-with-us/additional-baa

FFRDCs are subject to applicable direct competition limitations and cannot propose to this solicitation in any capacity unless they meet the following conditions. (1) FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector. (2) FFRDCs must provide a letter, on official letterhead from their sponsoring organization, that (a) cites the specific authority establishing their eligibility to propose to Government solicitations and compete with industry, and (b) certifies the FFRDC’s compliance with the associated FFRDC sponsor agreement’s terms and conditions. These conditions are a requirement for FFRDCs proposing to be awardees or subawardees.

b) Government Entities

Government Entities (e.g., Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations. Government Entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority and contractual authority, if relevant, establishing their ability to propose to Government solicitations and compete with industry. This information is required for Government Entities proposing to be awardees or subawardees.

c) Authority and Eligibility

At the present time, DARPA does not consider 15 U.S.C. § 3710a to be sufficient legal authority to show eligibility. While 10 U.S.C.§ 4892 may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider FFRDC and Government Entity eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the proposer.

2. Other Applicants Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

B. Organizational Conflicts of Interest

FAR 9.5 Requirements In accordance with FAR 9.5, proposers are required to identify and disclose all facts relevant to potential OCIs involving the proposer’s organization and any proposed team member (subawardee, consultant). Under this Section, the proposer is responsible for providing this disclosure with each proposal submitted to the solicitation. The disclosure must include the proposer’s, and as applicable, proposed team member’s OCI mitigation plan. The OCI mitigation plan must include a description of the actions the proposer has taken, or intends to take, to prevent the existence of conflicting roles that might bias the proposer’s judgment and to prevent the proposer from having unfair competitive advantage. The OCI mitigation plan will specifically discuss the disclosed OCI in the context of each of the OCI limitations outlined in FAR 9.505-1 through FAR 9.505-4.

Agency Supplemental OCI Policy

In addition, DARPA has a supplemental OCI policy that prohibits contractors/performers from concurrently providing Scientific Engineering Technical Assistance (SETA), Advisory and Assistance Services (A&AS) or similar support services and being a technical performer.

Therefore, as part of the FAR 9.5 disclosure requirement above, a proposer must affirm whether the proposer or any proposed team member (subawardee, consultant) is providing SETA, A&AS, or similar support to any DARPA office(s) under: (a) a current award or subaward; or (b) a past award or subaward that ended within one calendar year prior to the proposal’s submission date.

If SETA, A&AS, or similar support is being or was provided to any DARPA office(s), the proposal must include:

The name of the DARPA office receiving the support;

The prime contract number;

Identification of proposed team member (subawardee, consultant) providing the support; and An OCI mitigation plan in accordance with FAR 9.5.

Government Procedures In accordance with FAR 9.503, 9.504 and 9.506, the Government will evaluate OCI mitigation plans to avoid, neutralize or mitigate potential OCI issues before award and to determine whether it is in the Government’s interest to grant a waiver. The Government will only evaluate OCI mitigation plans for proposals that are determined selectable under the solicitation evaluation criteria and funding availability.

The Government may require proposers to provide additional information to assist the Government in evaluating the proposer’s OCI mitigation plan.

If the Government determines that a proposer failed to fully disclose an OCI; or failed to provide the affirmation of DARPA support as described above; or failed to reasonably provide additional information requested by the Government to assist in evaluating the proposer’s OCI mitigation plan, the Government may reject the proposal and withdraw it from consideration for award.

C. Cost Sharing/Matching

Cost sharing is not required; however, it will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument. Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

For more information on potential cost sharing requirements for Other Transactions for Prototype, see http://www.darpa.mil/work-with-us/contract-management and https://acquisitioninnovation.darpa.mil.

IV. Application and Submission Information

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

A. Address to Request Application Package http://www.darpa.mil/work-with-us/contract-management https://acquisitioninnovation.darpa.mil/

This announcement, any attachments, and any references to external websites herein constitute the total solicitation. If proposers cannot access the referenced material posted in the announcement found at www.darpa.mil, contact the administrative contact listed herein.

B. Content and Form of Application Submission

All submissions, including abstracts and proposals must be written in English with type not smaller than 12 point font. Smaller font may be used for figures, tables, and charts. Copies of all documents submitted must be clearly labeled with the DARPA BAA number, proposer organization, and proposal title/proposal short title.

1. Abstract Format

Proposers are strongly encouraged to submit an abstract in advance of a full proposal. Abstracts should follow the format described below in this section. The cover sheet should be clearly marked “ABSTRACT” and the total length of Section II must not exceed 4 pages (excess pages will not be reviewed).

Section I. Administrative

A. Cover sheet to include:

(1) BAA number (HR001123S0013);

(2) Lead Organization submitting abstract;

(3) Type of organization, selected among the following categories:

Large Organization, Small Disadvantaged Organization, Other Small Organization, HBCU, MI, Other Educational, Other Nonprofit;

(4) Proposer’s internal reference number (if any);

(5) Other team members (if applicable) and type of organization for each;

(6) Proposal title;

(7) Technical point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(8) Administrative point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(9) Total funds requested from DARPA, and the amount of cost share (if any); AND

(10) Date proposal abstract was submitted.

(Note: An official transmittal letter is not required when submitting a Proposal Abstract.)

Section II. Abstract Details

A. Innovative Claims Summary of innovative claims for the proposed research. This section is the centerpiece of the abstract and should succinctly describe the uniqueness and benefits of the proposed approach relative to the current state-of-art alternate approaches.

http://www.darpa.mil/

B. Technical Approach Technical rationale, technical approach, and constructive plan for accomplishment of technical goals in support of innovative claims and deliverable production.

C. Deliverables Deliverables associated with the proposed research and the plans and capability to accomplish technology transition and commercialization.

D. Cost and Schedule Provide a cost estimate for resources (e.g. labor, materials) and any subcontractors over the proposed timeline of the project, broken down by Government fiscal year.

2. Full Proposal Format

All full proposals must be in the format given below. Proposals shall consist of two volumes:

Volume I – Technical and Management Proposal (3 sections), and Volume II – Cost Proposal (4 sections). The submission of supporting materials other than those specifically referenced as being applicable to Volume I and Volume II is strongly discouraged and will not be considered for review. Section II of Volume I, Technical and Management Proposal, shall not exceed 20 pages.

The page limitation for full proposals includes all figures, tables, and charts. There is no page limit for Volume II, Cost Proposal.

A summary slide of the proposed effort, in PowerPoint format, should be submitted with the proposal. A template slide is provided as Attachment 2 to the BAA. Submit this PowerPoint file in addition to Volumes I and II of your full proposal. This summary slide does not count towards the total page count.

a. Volume I, Technical and Management Proposal – {20 Page Limit}

Section I. Administrative

A. Cover sheet to include:

(1) BAA number (HR001123S0013);

(2) Lead Organization submitting proposal;

(3) Type of organization, selected among the following categories:

Large Organization, Small Disadvantaged Organization, Other Small Organization, HBCU, MI, Other Educational, Other Nonprofit;

(4) Proposer’s internal reference number (if any);

(5) Other team members (if applicable) and type of organization for each;

(6) Proposal title;

(7) Technical point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(8) Administrative point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(9)…