Questions and Answers.docx

Questions and Answers

Question 1:

What kind of input signals are supplied to the system? Are both clock and data signals provided, and are the signals digital and reasonably free of noise? If digital signals are being provided, what signal levels can be expected – TTL, RS422, LVDS? This question tries to establish whether bits can be reliably captured digitally, potentially with clock recovery in the case of data-only signals, at the clock transitions, or whether some filtering or signal processing is required. Note that SoW item 2.1.8 appears to mention bit sync-related parameters, but otherwise the SoW does not explicitly call out bit sync capability as a requirement. Absent an explicit requirement, we need information about the signals in order to assess this.

Answer 1:

The input to the FEP is a digital PCM signal coming out of a TMoIP to PCM converter over approximately 3 feet of cable. The signal should be fairly free of noise. Both Data and Clock are present. The signal is TTL. Very minimal, if any at all, filtering or digital signal processing should be required.