3_20156882_98747_TP_NULL_0001_NULL_NULL_0001_752_U_N_Y_N_N_Y_D.PDF

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This is a Select-At-Test Component Procedure document for an Enhanced Signal Data Converter (ESDC) Circuit Card Assembly used in F-16 aircraft. The document specifies procedures for selecting and testing six critical resistor values required to manufacture qualification or production ESDC Circuit Card Assemblies (P/N 201126351-10 and -30) and ESDC Assembly (P/N 201414042-10).

The procedure details the process for selecting resistor values to achieve correct voltage outputs, with default values provided for six SUSUMU Co. RG2012P Series resistors. Testing must be performed at room temperature (21°C ± 3) to verify voltages are within tolerance specifications. The document includes specific measurement points, tolerances, and testing requirements including a "Unit Reset" test that verifies operation between 16.00-16.25 VDC. The procedure requires use of identical digital multi-meters for accurate voltage measurements and includes detailed equipment setup instructions and a component report template (DSN 1004) for documenting test results. The document is designated Distribution Statement D, limiting distribution to Department of Defense and DOD contractors only.

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20156882

DISTRIBUTION STATEMENT D - DISTRIBUTION AUTHORIZED TO DEPARTMENT OF DEFENSE AND DOD CONTRACTORS ONLY; CRITICAL TECHNOLOGY. 2015-02-26 OTHER REQUESTS FOR THIS DOCUMENT SHALL BE

REFERRED TO 416 SCMS/GUEAA, 6070 GUM LANE, HILL AFB, UT 84056-5819.

WARNING - THIS DOCUMENT CONTAINS TECHNICAL DATA WHOSE EXPORT IS RESTRICTED BY THE ARMS EXPORT CONTROL ACT (TITLE 22, U.S.C. SEC 2751 ET SEQ.) OR EXECUTIVE ORDER 12470. VIOLATIONS OF THESE EXPORT LAWS ARE SUBJECT TO SEVERE CRIMINAL PENALTIES. DISSEMINATION OF THIS DOCUMENT

IS CONTROLLED UNDER DOD DIRECTIVE 5230.25 AND AFI 61-204.

DESTRUCTION NOTICE - FOR UNCLASSIFIED, LIMITED DOCUMENTS, DESTROY BY ANY METHOD THAT WILL

PREVENT DISCLOSURE OF CONTENT OR RECONSTRUCTION OF THE DOCUMENT.

F-16 FINAL

REVISION

STATUS

OF SHEETS

REV

SHEET

REV - - - - - -

SHEET 1 2 3 4 5 6

SELECT-AT-TEST COMPONENT PROCEDURE

FOR ENHANCED SIGNAL DATA CONVERTER

Brian Randall 03/16/15

Rodney Gould

N/A

Brian Randall

Michael Laudato

Scott Kingsford

416 SCMS/GUEAA

416 SCMS/GUMAE

AFLCMC/LZPEF

03/17/15

03/17/15

02/20/15

03/06/15

03/17/15

SELECT-AT-TEST COMPONENT PROCEDURE

Enhanced Signal Data Converter (ESDC) Circuit Card Assembly (CCA) SRU Part No. 201126351-30

Enhanced Signal Data Converter (ESDC) LRU Part No. 201414042-10

Select-At-Test Component Procedure Document No. 20156882

1.1) SCOPE

This document specifies the Select-At-Test Component Selection Procedures necessary to manufacture qualification or production Enhanced Signal Data Converter (ESDC) Circuit Card Assemblies (CCAs), ESDC CCA without connectors, P/N 201126351-10, ESDC with connectors, P/N 201126351-30, and/or the Enhanced Signal Data Converter (ESDC) Assembly, P/N 201414042-10. The correct Select-At-Test Components must be used to insure the ESDC will meet performance requirements and output and characteristic tolerances are met and held over the required temperature range.

1.2) APPLICABLE DOCUMENTS

USAF, Ogden Air Logistics Drawing

Number 201126351

USAF, Ogden Air Logistics Gerber File Number 201126351-10

USAF, Ogden Air Logistics Drawing

Number 201414042

T.O. 8C11-8-29-3

MIL-STD-45662A

MIL-STD-2164

20156881

Assembly, Printed Circuit Board, Enhanced Signal Data Converter, Drawing

Gerber File, Manufacturing Requirements, Specifications and data.

Modification of, Converter, Enhanced Signal Data, Drawing

Technical Manual, Operation and Maintenance Instructions, Enhanced Signal Data Converter

Calibration Systems Requirements

Environmental Stress Screening Processes for Electronic Equipment

Acceptance Test Procedure

1.3) SELECT-AT-TEST COMPONENTS

Six resistor values must be selected to achieve the correct voltage output at specified measurement points. The ESDC Bill of Materials (BOM) includes default values for the six select-at-test resistors listed below (see Table 1). All resistors are specified as SUSUMU Co.

RG2012P Series resistors or equivalent. The specified measurement points should then be measured at room temperature (i.e. 21°C ± 3) to determine if measured voltages are within tolerance. If a measured voltage is found to be out of tolerance specification different resistor values must be selected to achieve measured voltages within tolerance. A “Unit Reset” test must also be performed. The ESDC operates with a supply voltage of 28 VDC. The ESDC must be able to continue to operate with a supply voltage decrease to 16.00 to 16.25 VDC at which point a unit reset will occur. To conduct a “Unit Reset” test adjust the ESDC supply voltage to 28 VDC and slowly decrease voltage. The ESDC UUT should continue to operate to between 16.00 and 16.25 VDC at which point The ESDC will power off when 28VDC is restored the ESDC will reset and continue to operate. Complete Select-At-Test Report (DSN 1004). Two identical digital multi-meters must be used to measure APLA Out and RVT Secondary voltages.

Removing the meter or using meters with differing loads may cause inaccurate voltage measurements.

Table 1

SELECT-AT-TEST COMPONENTS

Component Default Value

Measurement Point (with respect to APLA Ground, J1 Pin 3) Tolerance

Voltage Measured

New Value

New Voltage Measured

R128 392 Ω J2 Pin 1 7.000 VAC ± 0.100

R209 240 Ω U201 Pin 7 J2 Pin 1 VAC ± 0.020

R231 499 Ω J1 Pin 4 30.15*(RVT Sec/RVT Exc) ± 0.031VDC

R215 5.11 kΩ U201 Pin 14 -(APLA Out)VDC ± 0.030

R319 64.9 kΩ U300 Pin 2 12.400 VDC ± 0.150

R308 6.8 kΩ Unit Reset Reset @ 16.00 to

16.25 VDC

1.4) SELECT-AT-TEST COMPONENT SELECTION PROCEDURE

Use a decade box to connect to the UUT at R128 location. Set decade box to the corresponding default value. Slowly adjust decade box until desired output within tolerance is achieved. Repeat this process for the remaining select-at-test components.

1.5) EQUIPMENT SETUP

See figure 1 for equipment setup (Temperature Chamber and decade box not shown).

Figure 1

SELECT-AT-TEST COMPONENT REPORT

Date:

DSN 1004 Vendor:

Test Engineer:

Measured Temperature (21°C ± 3) =

RVT Excitation (VAC) (7.000 ± 0.100) =

RVT Secondary (VDC) =

APLA Out (VDC) =

Transfer Function, 30.15*(RVT Sec / RVT Exc) =

Error % = 100*(APLA Out - Transfer Function) / APLA Out =

With no-load, set APLA

= 12.300 VDC

@3 kΩ Load, APLA =

@350 Ω Load, Does APLA Latch out?

i.e APLA <= 0.600

VDC:

YES

NO

APLA

Out(VDC)=

Component Default Value

Measurement Point Tolerance

Voltage Measured

New Value

New Voltage Measured

R128 392 Ω J2 Pin 1 7.000 VAC ± 0.100

R209 240 Ω U201 Pin 7 J2 Pin 1 VAC ± 0.020

R231 499 Ω J1 Pin 4 30.15*(RVT Sec/RVT Exc) ± 0.031VDC

R215 5.11 kΩ U201 Pin 14 -12.300 VDC ± 0.030

R319 64.9 kΩ U300 Pin 2 12.400 VDC ± 0.150

R308 6.8 kΩ Unit Reset Reset @ 16.00 to

16.25 VDC

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