FA8650-18-S-1201-Atch6.pdf

FA8650-18-S-1201

Attachment 6

Assured and Trusted Microelectronics Solutions (ATMS)

Statement of Objectives (SOO)

8 September 2017

1.0 BACKGROUND

The rapid improvement cycle for semiconductor technology and Systems on a Chip (SoC) has made process and equipment upgrades very expensive, triggering State-Of-The-Art (SOTA) foundry operations to consolidate into a few large companies mainly residing in Asia. The resulting lack of trusted, U.S.-based foundries has become a significant concern for the

Department of Defense (DoD) because commercial SOTA foundries for defense-related

Application Specific Integrated Circuit (ASIC) development may not meet security requirements. The DoD is interested in solutions that enable the use of commercial foundries while ensuring critical defense technologies and intellectual property (IP) are trusted (confidence there is no malicious content), assured (verified function with no extra functions), and protected

(prevention of unauthorized disclosure).

Assured and Trusted Microelectronics Solutions (ATMS) encompasses efforts to make sure that legacy (currently fielded technology no longer in production), state-of-practice (technology nodes in production and available for manufacture/purchase), and future (next generation cutting-edge capability) microelectronics:

Are sustainable and reliable across military mission lifetimes

Are acquired exactly as specified and without additions or alterations

Maintain robust IP protection during manufacturing and after fielding

The desired end-state is the ability to incorporate commercially available ASIC, SoC, and Field

Programmable Gate Array (FPGA) capabilities without sacrificing the integrity or security of national defense systems. This will enable rapid modernization and flexibility, increased performance, and a reduction in the need for unique DoD systems. In order to manage the development of long-term assurance and trust solutions, the Office of the Secretary of Defense

(OSD) established the Joint Federated Assurance Center (JFAC). As the hardware assurance

(HwA) lead for the JFAC, the Air Force Research Laboratory (AFRL) is charged with determining viable capabilities, tools, and techniques that are applicable to the trusted and assured microelectronics problem set, whether currently available or under development.

2.0 PURPOSE

The purpose of this effort is to research and develop innovative HwA solutions that broaden the utility of commercial technology from global foundries for DoD applications.

3.0 OBJECTIVES / SCOPE

The DoD is interested in developing technology-based solutions with built-in trust measures, technologies that accelerate military-relevant circuit development, and techniques that ensure robust performance for DoD systems in accordance with the following focus areas:

3.1 Design Assurance

Methods and approaches to ensure that the DoD maintains access to advanced and legacy integrated circuit (IC) technology nodes through the implementation of assurance technologies embedded within an IC, beyond functional analysis of consumed third party intellectual property (soft, hard, and semi) and cloud technologies. All R&D activities in this topic area would contribute to a holistic assurance approach to protect the DoD’s microelectronics supply chain as IC’s are designed and/or replaced. Examples include

(but are not limited to):

Innovative design techniques that promote assurance

Technologies that provide traceability throughout the IC lifecycle

Cloud environments and ecosystems to enable provenance

IP analysis and verification environments to perform beyond functional analysis

Development & demonstration of qualitative & quantitative metrics for this topic area

3.2 FPGA Assurance

Develop novel mechanisms to provide assurance for COTs FPGA's at the hardware, bitstream and software levels to enable a comprehensive FPGA assurance framework across the lifecycle of the FPGA. Areas of interest include (but are not limited to):

3PIP analysis, tools and techniques of the FPGA hardware and bitstream

Qualitative and quantitative metrics for FPGA assurance

Enhanced verification methods to ensure functions as desired

S&T to enable traceability throughout the supply chain

Enhanced security circuit implementations and architectures

3.3 Validation & Verification

Microelectronics test and verification methodologies in support of verifying the trust and assurance of components and systems. Areas of interest include (but are not limited to):

Embedded ASIC structures to assist in post fabrication analysis

High volume technologies for rapid characterization for supply chain risk management (SCRM)

Non-destructive physical analysis techniques

Highly accurate analysis technologies

Algorithms to improve assessment technology throughput and reducing processing time or expertise required to perform analysis

Low cost evaluation techniques

Fusion technologies that leverage multiple data sets

3.4 Enhanced Fabrication

Advanced node microelectronics fabrication and packaging capabilities at existing state-of-the-practice (SOTP) foundries with a focus on high-mix, low-volume alternatives.

Areas of interest include (but are not limited to):

SOTA for 3D and 2.5D packaging and how these commercial solutions could be used to the DoD's advantage for both protecting IP and assuring Trust.

Advanced integrated photonics

Flexible Hybrid manufacturing

New novel technologies that may provide additional security measures

3.5 Radiation Hardened

Innovative design, manufacturing, and assessment approaches for trusted, strategic radiation-hardened electronics in advanced technology nodes for next-generation strategic systems. Areas of interest include (but are not limited to):

Development of Rad Hard by Design (RHBD) libraries and/or techniques in SOTA foundries that can be leveraged to meet strategic radiation levels.

Dose rate radiation effects testing performed on COTS devices.

Radiation testing capabilities of SOTA FPGAs.

Techniques and methodologies for leveraging commercial technology and/or COTS devices for use in high reliability, strategic hardened applications.

4.0 DELIVERABLES

Data shall be delivered in accordance with the Contracts Data Requirements Lists (CDRLs).

Specific hardware/software deliverables as well as residual hardware that are procured or developed under this effort shall be delivered as applicable. The contractor shall propose additional deliverables as appropriate in a format acceptable to both parties. The contractor shall identify, within the proposal, any restrictions on the type of rights to be provided with software and hardware delivered but not developed for this effort with full disclosure of any dependencies upon third party software/hardware.

5.0 SAFETY

The Contractor shall comply with all Air Force, federal, state, and local safety and environmental regulations. An approved safety plan in accordance with AFI 91-202 AFRL Supplement 1 shall be obtained before any experiment can be conducted at Wright-Patterson AFB and shall comply with all Air Force safety and environmental regulations. The contractor shall comply with system safety requirements contained in MIL-STD 882E, section 4, "General Requirements" for any deliverable systems or hardware and software interfaces with those components. The contractor shall test and verify the safety-critical hardware and software for safety acceptance.

6.0 SECURITY

General Operations Security (OPSEC) procedures, policies and awareness are required in an effort to reduce program vulnerability from successful adversary collection and exploitation of critical information. OPSEC will be applied throughout the life cycle of the contract. The Critical

Information List (CIL) will be provided upon request by AFRL/ RYOY Information Protection

Office. While working on the government installation, OPSEC guidance will be provided by

AFRL/RYOY Information Protection Office.