CALL 001 Atch 3 SIRF Factsheet.pptx

SIRF Radiation Requirements:

Total Dose 300-1,000 krad(Si) Dose Rate Latchup 1E10 rad/s Dose Rate Upset 1E9-5E9 rad/s Single Event Latchup – None Single Event Upset -1E-2 data err/chip-day -1E-4 config err/chip-day

Design Hardening Strategy: The SIRF design hardening strategy maintains Virtex-5™ functionality and allows use of standard commercial fabrication processes.

Layout Hardening Techniques:

-Hardened transistor layout for total dose resistance -Beefed-up power and ground for dose rate effects

Circuit Hardening Techniques:

-Redundant memory elements --Space/Time redundancy, error correcting schemes --Extra efforts for bulletproof configuration memory -State machines re-engineered to eliminate SEFI -Fabricated on epitaxial wafers

Productization Plans: SIRF will be directly comparable to the Xilinx V5 FX130T, and will be sold and supported as an off-the-shelf Xilinx part. Availability as a space qualified part is scheduled for Sep 2010.

Single Event Immune Reconfigurable FPGA (SIRF) Overview: Future Air Force satellites will require massive increases in data processing capabilities. Unfortunately, nonrecurring engineering costs for custom processing chips make them unaffordable for most satellite programs. The affordable answer for custom data processing hardware is the Field Programmable Gate Array (FPGA). The AFRL/Xilinx Single Event Immune Reconfigurable FPGA (SIRF) brings FPGA technology to the space avionics market.

Description: SIRF is a re-engineered version of the Virtex-5™ FPGA that is hardened to the radiation environment in space. SIRF will have the same features and capabilities as the leading-edge Virtex-5 commercial chip, but has been redesigned to operate reliably under conditions that would cause data errors and unstable operation in commercial chips.

Current as of May 2009

SIRF CHIP LAYOUT

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