Att 7-6340_26_tib_chp46_vol46.pdf

NSN 0056-00-480-0357 TI 6340.26

FINAL

INSTRUCTION BOOK

SITE-REPLACEABLE LRU

SCHEMATICS AND DESCRIPTIONS

ARSR-4 SYSTEM

COLLECTOR AND PREAMPLIFIER

POWER SUPPLIES

(FROM UNIT 9)

CHAPTER46, VOLUME 46

CONTRACT DTFA01-88-C-00037

CONTRACTOR

WESTINGHOUSE ELECTRIC CORPORATION

BALTIMORE, MARYLAND

MADE FOR

U.S. DEPARTMENT OF TRANSPORTATION

FEDERAL AVIATION ADMINISTRATION

(1 MARCH 1995)

I FI 634026 [

RECORD OF CHANGES o,eE=,VENO,Vol. 46

......... WESTINGHOUSE WARRANTY OF THE ARSR-4 SYSTEM UNDER PERFORMANCE SPECIFICATIONS AND DESIGN CRITERIA i CHANGE SUPPLEMENT CHANGE SUPPLEMENTS Ca) DefinitionsT

TO OPTIONAL TO ___ OPTIONAL

BASIC BASIC i l I (1) "Correction," as _sed in this clause, means the ehmination o_ a defect at no additiona_ cost to the Government,

(2) "Defect,"as used inthisclause,means any conditionor characteristicinany suppliesor servicesfurnishedby the contractor under thiscontractthatisnot incornpliancewiththe performance requirements ofthiscontract,Routine repairsassociated with maintenance of each system after acceptance is considered to be outside the scope of the warranty provided that the system is meeting the performance requirements under this contract.

(3) "Supp es," as used in this clause, means the end items, including software furnished by the contractor and related services i required under this contract.

_S m....J (4) yste , as used mth s clause, means the integrated and operatlona product(s) that _s(are) to be dehvered by the contractor under this contract. A "system "includes all of its elements or components including software.

(5) "Acceptance," as used in h s clause, means the execution of an official document (e.g., FAA Form 256) by an authorized representative of the Government by which the Government assumes for itself, or an agent of another, ownership of existing and identified supplies, or approves specific services rendered, as partial or complete performance of the contract.

The warranty is considered accepted for the purposes of payment at the time of final acceptance of the system under warranty.

(b) Contractor's Obligation:

(1) The contractor warrants that each item furnished under this contract shall be free from defects discovered by either the Government or the contractor for a minimum period of 12 months after acceptance, even if the field reliability requirements of H.20* are met eadier. (" H.20" refers to the Field Reliability Verification clause of contract DTFA01-88_C- 00037.) However, if the field reliability requirements of H.20 are not demonstrated within 12 months of the acceptance of each system, the warranty shall be extended for that system until these requirements are verified.

(2) In the event that a defect in any warranted item of supplies/system is the result of a deficiency in the design of such supplies/system, then any resulting modification of the affected supplies necessary to correct the design deficiency shall also be incorporated into all items of supply previously accepted without regard to the above 12 month limitation. Such modifications shall be done at no increase in contract price. The contractor's obligations under this design warranty subparagraph shall apply until 12 months following acceptance of the the last ARSR-4 system under warranty.

(3) if the contractor becomes aware at any time before acceptance by the Government (whether before or after tender to the Government) that a defect ex sts in any supplies or services, the contractor shall:

(i) Promptly correct the defect, or

(ii) Promptly not fy the Contracting Officer, in writing, of the defect, using the same procedures prescribed in paragraph (b)(4) of this clause,

(4) if the contractor determines that a defect exists in any of the supplies or services after acceptance by the Government under this contract, the contractor shall submit to the Contracting Officer, in writing, within 30 days, a recommendation for corrective actions, together with supporting information in sufficient detail for the Contracting Officer to determine what corrective action, if any, should be taken. This recommendation shall be submitted as a no cost ECP. If the defect is a design defect, the corrective action/modification shaII be effected at all sites accepted under this contract.

(5) The contractor shall promptly compIy with any timely written direction from the Contracting Officer to correct or partially correct a defect, at no increase in the contract price.

(6) The contractor shall also prepare and furnish to the Contracting Officer data and reports applicable to any correction required under this clause (including review and updating of all the affected data called for under this contract) at no increase in the contract price.

I I (7) In the event of timely notice of a decision not to correct or only partially correct a defect, the contractor shall submit aI technical and cost proposal, within 30 days from the time notified, to amend the contract to permit acceptance of the affected supplies or services in accordance with the revised requirement and an equitable reduction in the contract priceshall promptly be negotiated by the parties and be reflected in a contract modification.

I (8) Any supplies or parts thereof corrected or furnished in replacement, and any services reperformed, shall also be subject to the conditions of the clause to the same extent and for the remaining duration of the warranty applicable to the supplies or services initially accepted, I (9) The contractor shall not be responsible under this clause for the correction of defects in Government-furnished property, I except for defects in installation, unless the contractor performs, or isobligated to perform, any modifications or other work on such property, in that event, the contractor shall be responsible for corrections of defects that resulted from work performed by the contractor for modifications or other work.

I (10) If the Government or contractor returns supp es for correction or replacement under this clause, the contractor shall be 1 liable for transportation charges up to an amount equal to the cost of transportation by the usual commercial met hod of

-- shipment from the place of delivery specified in the contract (irrespective of the F.O.8. point or the _oint of acceptance) to the contractor'S p)ant and return to the place of delivery specified in this contract. The contractor shalt also bear the risk of loss for the supplies while in transit.

(11) All implied warranties of merchantability and "fitness for a particular purpose" are excluded from any obligation under this

,,,1 I contract.

FAA Form 1320-5 trio) USE PREVIOUS EDITION rl 6340.26

I I iNSERT LATEST CHANGED PAGES. DESTROY SUPERSEDED PAGES.) LISTOF EFFECTIVEPAGES I Dates of issue for original and changed pages are:

Original...0... 1 March 1995

TOTAL NUMBER OF PAGES IN THIS PUBLICATION IS 11g CONSI_ING OF THE FOLLOWING:

Page *Change Page *Change Page *Change NO. NO. No. No, No. No.

A B Blank i ii Blank iii- v vi Blank 46-I - 46-17 46-18 Blank 46-19 46-20 Blank 46-21 46-22 Blank 46-23

} 46-24Blank 46-25 46-26 Blank 46-27 46-28 Blank 46-29 46-30 Blank 46-31 46-32 Blank 46-33 46-34 Blank 46-35 46-36 Blank 46-37 46-38 Blank A-I - A-60 B-I ............... O B-2 Blank B-3 B-4 Blank

* Zero in this column indicates an original page, Vol. 46 (IMarch1995) A/B

TI 6340.26

INTRODUCTION

The contents of this book are arranged as follows. Page-size text and tabular material appear first. Illustrations that support the text and tabular material appear next in an 11-inch by 17-inch flat-pak format. Engineering schematic diagrams, also in an 11-inch by 17-inch flat-pak format, appear next in

Appendix A. A page-size list of acronyms and abbreviations appears last in

Appendix B.

(1 March 1995) i/ii

TABLE OF CONTENTS

Paragraph Title Page

CHAPTER 46 - COLLECTOR AND PREAMPLIFIER POWER SUPPLIES

46.1 Introduction. . . . . . ....... 46-I

46.2 SchematicDiagrams. , . . . . . . . 46-I

46.3 Collector Power Supply {CPS)"Technical Description 46-2

46.3.I AssemblyOverview. . 46-2

46.3.1.1 Step-StartRectifier 46-2

46.3.1.2 Step-UpConverterA5 46-2

46.3.I.3 Switcher-Converter 46-3

46.3.1.4 CPSControlA31 . . 46-3

46.3.I.5 HouseSupply........ 46-3

46.3.2 Detailed Description . 46-3

46.3.2.I Step-StartRectifier 46-3

46.3.2.2 Step-StartControlAI 46-4

46.3.2.3 Step-UpConverterA5 . 46-4

46.3.2.4 Step-UpConverterControlA2 46-4

46.3.2.5 Switcher-ConverterModules 46-5

46.3.2.5.I Components...... 46-5

46.3.2.5.2 Controland Output ........ 46-5

46.3.2.5.2.I SwitcherControlA37 .... 46-6

46.3.2.5.2.2 MotherBoardA43 . .......... 46-6

46.3.2.5.2.3 SwitcherModule A8 ............. 46-6

46.3.2.6 Switcher Controls A37 through A41 .......... 46-6

46.3.2.7 Switcher Modules AS, A13, A18, A23, and A28 ..... 46-7 46.3.2.7.I SwitcherBridge ........... 46-7

46.3.2.7.2 SwitcherModuleOutput ....... 46-7

46.3.2.8 CPS ControlA31 .......... 46-7

46.3.2.8.I TimingGenerationand Distribution 46-7

46.3.2.8.2 Enable Distribution . . . . 46-8

46.3.2.8.3 Switcher-ConverterCurrentMonitor 46-8

46.3.2.8.4 FeedbackEnableControl . . 46-9

46.3.2.8.5 FuseMonitorCircuit . . . 46-9

46.3.2.8.6 OvervoltageMonitor . . . 46-9

46.3.2.9 HouseSupply....... 46-10

46.3.2.9.I HouseSupplyControlA36 46-10 46.3.2.9.I.I OvercurrentShutdown . 46-II 46.3.2.9.I.2 OvervoltageSenseShutdown 46-11

46.3.2.9.1.3 House Supply Control Internal +15-Volt Regulator 46-12

46.3.2.9.2 SwitchAssemblyA32 ........... 46-12

46.3.2.9.3 +15/+12-Volt Regulator A35 ...... 46-12

46.3.2.9.4 -15-VoltRegulatorA34 ...... 46-12

46.3.2.9.5 +5-Volt RegulatorA33 ............... 46-13

46.4 Preamplifier Power Supply (PPS) Technical Description 46-13 46.4.I AssemblyOverview ............ 46-13 46.4.I.I Step-Start Rectifier _ssembly .... 46-13 46.4.I.2 Step-UpConverterA5 ............. 46-13 46.4.I.3 Switcher-Converter............. 46-14

46.4.1.4 PPSControlA31 ......... 46-14

46.4.I.5 HouseSupply .................. 46-14

Vol. 45 (1 March1995) _ii

TABLE OF CONTENTS--Continued

Paragraph Title Page

46.4.2 DetailedDescription ............... 46-14

46.4.2.I Step-StartRectifier ............... 46-14

46.4.2.2 Step-StartControlAI ......... 46-14

46.4.2.3 Step-UpConverterA5 ........... 46-14

46.4.2.4 Step-UpConverterControlA2 ...... 46-14

46.4.2•5 Switcher-Converter 46-14* . . . . • * • • • , • • • • . . .

46.4.2.6 Switcher Controls A37 through A41 .......... 46-15

46.4.2.7 Switcher Modules A8, A13, A18, A23, and A28 ..... 46-15

46.4.2.8 PPS ControlA31 ................... 46-15

46.4.2.8•I Timing Generation and Distribution ....... 46-15

46.4.2.8.2 Enable Distribution . .............. 46-15

46.4.2.8.3 Switcher-ConverterCurrent Monitor ....... 46-15

46.4.2.8.4 FeedbackEnable Control ......... 46-15

46.4.2.8.5 Fuse MonitorCircuit .......... 46-15

46.4.2.8.6 OvervoltageMonitor ........ 46-15

46.4.2.9 HouseSupply ....... 46-15

46.4.2.9.I HouseSupply ControlA36" . ....... 46-15

46.4.2.9.2 SwitchAssemblyA32 ............. 46-16

46•4.2.9.3 +15/+12-Volt Regulator A35 .......... 46-16

46.4.2.9.4 -15-VoltRegulator A34 .............. 46-16

46.4.2.9.5 +5-VoltRegulatorA33 .............. 46-16

APPENDIXES

A EngineeringSchematics ................ A-I B List of Acronymsand Abbreviations ............ B-I

Vol, 46 iv (IMarch1995)

LIST OF ILLUSTRATIONS

Figure Title Page

46-I Collector Power Supply, Functional Block Diagram ..... 46-17

46-2 Step-Up Converter A5, Waveform Diagram ......... 46-23

46-3 Switcher Module Control and Output, Functional Block

Diagram ................. 46-25

46-4 Switcher Module Assembly, Waveform Diagram ...... 46-27

46-5 Timing and Control Waveform Diagram .......... 46-29

46-6 PAL TimingDiagram ............... 46-31

46-7 Preamplifier Power Supply, Functional Block Diagram . . 46-33

Vo| 46

(I March 1995) v/_i

TI 6340_26

CHAPTER 46

COLLECTORANDPREAMPLIFIERPOWERSUPPLIES

46.1 INTRODUCTION.- This chapter provides schematic diagrams and technical descriptions for a collector power supply, part number 3D56068GOI, and for a preamplifier power supply, part number 3D56068G02. The collector power supply (CPS) is used in nine locations in the Radar Transmitter (Unit 9) where it has reference designations AIPSI through AIPS4, A2PSI and A3PSI through A3PS4. The preamplifier power supply (PPS) is used in one location in unit 9 where it has reference designation A2PS3. For maintenance purposes both power supplies are classified as site replaceable units repaired at the depot. Refer to chapter I for general information, signal information, conventions, and definitions.

46.2 SCHEMATIC DIAGRAMS.- The collector and preamplifier power supplies schematic diagrams are provided in the Engineering Schematics Appendix A.

General reference data for microcircuits shown in the schematic diagrams is provided in the Integrated Circuit Data book, TI 6340.25.

46.2.1 Diagram 3D60270 is an overall schematic diagram of the collector power supply which shows how the subassemblies are connected to each other and to the assembly input/output connectors. The subassembly schematic diagrams provided are listed as follows:

Subassembly DiagramNo.

Step-startcontrolAI 3D60127

Step-up converter control A2 3D60234

CPS controlA31 3D60302

Switch assemblyA32 3D60220

+5-volt regulator A33 3D60460

-15-volt regulator A34 3D60461

+15/+12-volt regulator A35 3D60462

House supply control A36 3D60221

Switcher control A37 through A41 3D60250

NOTE

For the collector power supply, there are no separate schematics for subassemblies A3 through A30 and mother board A43.

46.2.2 Diagram3D60277is an overallschematicdiagramof the preamplifier power supply which shows how the subassemblies are connected to each other and

(1 March1995) 46-1 to the assembly input/output connectors. The subassembly schematic diagrams provided are listed as follows:

Subassembly DiagramNo.

PPS controlA31 3D60419

NOTE

The preamplifier power supply subassembly schematics are the same as for the collector power supply, except for subassembly A31.

46.3 COLLECTOR POWER SUPPLY (CPS) TECHNICAL DESCRIPTION.- The technical description of the collector power supply (CPS) begins with an assembly overview which identifies the major circuit functions and describes its basic operation.

The overview is followed by a detailed description, where the major circuit functions are described in depth, with the schematic diagrams serving as references.

46.3.1 Assembly Overview.- The CPS, in conjunction with other CPSs and the bus regulator, conditions collector power for the solid-state radio frequency (RF) amplifiers. The CPS converts ac to dc, provides energy storage for bridging of short-time power interruptions, and regulates voltage by controlling the restoration of charges to storage capacitor banks in the RF amplifiers. The CPS operates as a feedback-controlled, on-off current source in supplying this voltage. The storage capacitor banks are in parallel with other CPSs to precisely restore and regulate the RF panel storage voltage between transmitter

RF pulses. Samples of the dc storage voltages in the RF panels are averaged between the bus regulator and each CPS to obtain a single voltage sample. This sample is compared with a reference voltage in each CPS to control its operation. Primary power input is nominally 208 volts ac, three phase at 60 Hz.

Collector power supply output is nominally 60 amperes (average) at a selected voltage between +28 and +40 volts dc. Timing and enabling signals come from the bus regulator. A functional block diagram, figure 46-I, shows the major circuit functions and serves as reference for the overview.

46.3.1.1 Step-Start Rectifier.- A three-phase, full-wave bridge rectifier rectifies the input of 208 volts ac line-to-line (167 - 243 vac), three-phase primary power. The rectifier output is +280 volts dc (+15 percent, -25 percent) and limits surge current during start-up. When this power line is initially energized, surge-limiting resistors, in series with the positive half-wave rectifiers, limit the surge current. Following a 40-millisecond delay after input power is applied, the resistors are bypassed by gated silicon-controlled rectifiers (SCRs) to remove current limiting.

46.3.1.2 Step-Up Converter A5.- An inductive boost circuit operates at a switching frequency of 43.33 kHz to raise the dc voltage from +280 volts dc

(+15 percent, -25 percent) to +350 volts dc (+/-I percent). In addition, the step-up converter (up-converter) includes energy storage which is sufficient to sustain full-performance CPS operation for primary power interruption for up to

Vol 46

46-2 (I March1995)

20 milliseconds. Inputs to the up-converter are the +280 volts dc from the rectifieranda 43.33-kHzclock(UCCLK)timinginputfromCPScontrolA31.

46.3.1.3 Switcher-Converter.- See functional block diagram 46-3. Five switcher-converter modules operate in parallel to transform and regulate voltage, and to control power flow from the up-converter output bus to the RF panels. Each switcher-converter consists of an inverter circuit which converts +350 volts de to 86.7 kHz, transforms voltage, and rectifies the result to produce a system-seleetable voltage of between +28 and +40 volts de on the output power bus. The switcher-converter modules act as on-off controlled, constant-current sources, each of which supplies 50 amperes peak to the output bus as it operates. On-off control of the switcher-converter module is by feedback from RF panel de voltage samples, via the bus regulator and CPS control A31. All five switcher-converter modules operate in parallel for coarse regulation of voltage charge, and a single module operates for fine regulation near the end of the regulation period. Typically, the switcher-converter circuit consists of a switcher control, mother board A43, a switcher module, and an output rectifier. Inputs to switcher control A37 (for example) are a 172.5 kHz clock and switcher module A8 current-sense feedback signals SWISAMI and SWISAM2. The 172.5 kHz clock is used to synchronize UI and U2 outputs.

Current-sense signals SWISAMI and SWISAM2 are rectified at the input to amplifier UI with the 172.5-kHz clock switching the resultant through amplifier UI. As long as switcher module A8 provides current-sample feedback within tolerance, U2 continue to trigger control driver FETs Q3 through Q6. The 172.5-kHz clock input to PWM U2, ensures that control driver FET output signals SWCTLOUT+ and SWCTLOUT- are synchronized with the switched current sense input and clock. If either current sense feedback signal SWISAMI or SWISAM2 is lost or dropsoutof tolerance,transistorQ2 sensesthefaultandsendsa highto the SHUTDOWN port on PWM U2. PWM U2 output signals are shut off, all drive to switcher module A8 is stopped, and the power supply is shut down.

46.3.1.4 CPS Control A_I.- CPS control A31 distributes timing and control signals, processes CPS feedback control, and interprets CPS performance for built-in-test equipment BITE. Inputs from the bus regulator are: a 2.6-MHz clock, reference voltage level, RF panel dc voltage sample, and a system enable signal. The system enable signal stops the inverter during RF pulse time.

Outputs are appropriately timed inverter triggers, inverter enable signals which control regulation, and up-converter and house power supply timing signals.

46.3.1.5 House Supply.- Three small integral regulators provide low-voltage operating power to the CPS and the bus regulator. In conjunction with a common inverter, control, and transformer system, the regulators comprise an internal supply with outputs of +15/+12 volts de, +12 volts dc, +5 volts dc, and -15 volts dc.

46.3.2 DETAILED DESCRIPTION.- The following paragraphs describe details of the operations previously summarized in the assembly overview. The descriptions are referenced to applicable sheets of schematic diagrams listed in Appendix A.

46.3.2.1 Step-Start Rectifier.- See schematic diagram 3D60270, sheet 2. The power input is three-phase, 208 volts ac at 47 to 63 Hertz. Power is applied via input/output connector PI pins I through 4, to the step-start rectifier

I assembly.The step-startrectifierassemblyis a full-wave,three-phase rectifier bridge assembly consisting of diodes CRI through CR6, which provides dc operating voltage to the CPS. Three 4.02-ohm, 30-watt current-limiting

Vo[ 46 (IMarch1995) 46-3

Ti 6340.26 resistors RI, R2 and R3 are in series with diodes CRI through CR6 in the positive half-wave side of the bridge, to limit the initial surge current when power is applied. Each of the three resistor legs of the bridge is bypassed by a thyristor SCR, QI, Q2 and Q3, which is fired by the step-start rectifier assembly approximately 40 milliseconds after application of primary power to the rectifier input. The ON state SCRs bypass the step-start resistors and remove surge current limiting. The output of step-start rectifier assembly is 210 to

322 volts dc, which is applied to step-up converter A5.

46.3.2.2 Step-Start Control At.- See schematic diagrams 3D60270, sheets 2 and

3. Step-start control AI enables step-up converter A5 operation 40 milliseconds after thyristor SCRs QI, Q2 and Q3 fire. A sample of CPS three-phase primary power input, taken from secondary A2/B2/C2 of house supply transformer T6, is applied to AI terminals El, E2, and E3. This sample is full-wave rectified by diodes CRI through CR6, regulated to +15 volts de, and applied to 40 millisecond time delay circuit QI, Q2 and Q3 and to SCR driver circuit Q4 through Q7. When time delay capacitor C2 charges to +4 volts dc, SCR gates Q4, Q5 and Q6 are driven on. This applies +15 volts de to the gate circuits of thyristor SCRs QI, Q2 and Q3 in the step-start rectifier assembly, via AI terminals E7, E8 and E9.

See schematic diagram 3D60127, sheet 2. Optoeoupler UI, across AI terminals E4 and E5, enables step-up converter A5 when turned on by a current flow between optocoupler UI pins 5 and 7.

46.3.2.3 Step-Up Converter A5.- See schematic diagram 3D60270, sheet 2 and waveform diagram, figure 46-2. The step-up converter A5 (up-converter) employs an inductive boost to increase and regulate the 220-to-322 volts dc input to an output of +350 volts dc +/-I percent. The principle of operation of the up-converter is illustrated in figure 46-2. Field-effect transistors (FETs) Q4, QS, and Q6 are switched on and off at the rate of 43.33 kHz, for a feedback-controlled duration, to control current (IL) through the windings of inductor LI. Current flow through the FETs is designated IFET. During the first half of the duty cycle (FET on-time), inductor current IL builds up the inductor field. The voltage charge (VC) in the capacitor banks is partially depleted during this time (due to RF pulses), as is shown in the VC waveform.

No current (ID) flows through diodes CR8, CR9 and CRIO to six capacitor assembly A3, eight capacitor assembly A4, or four capacitor assemblies A6, A11, A16, A21, and A26, hereafter referred to as capacitor banks. When the FETs (thus IFET) turn off at the next half of the duty cycle, the inductor field collapses, forcing inductor current IL through diodes CR8, CR9 and CRIO. Diode current ID flows into the capacitor banks, restoring and increasing the VC depleted during

FET on-time. The cycle then repeats. Regulation, via drive to the switching transistors, is developed in a current mode controller in step-up converter control A2.

46.3.2.4 Step-Up Converter Control A2.- See schematic diagrams 3D60270, sheet 2 and 3D60234. The step-up converter control A2 circuit employs a current mode controller to regulate the output voltage across the energy storage capacitor banks at +350 volts dc by controlling on-drive duration to the up-converter FETs

Q4, Q5 and Q6.

46.3.2.4.1 See schematic diagrams 3D60234, sheets 2 and 3. A +350VSENSE input to operational amplifier U2 (capacitor bank voltage), and a sample of the total

FET switching current (CURRENTIN) to pulse width modulator UI, are inputs to step-up converter control A2. A clock input of 43.33 kHz to transformer T6 from

CPS control A31, synchronizes step-up converter A5 to radar system timing. In

46-4 (IMarch1995) the absence of this input, an internal clock in pulse-width modulator UI controls operation. Signal ENABLE from step-start control AI permits step-up converter A5 to operate only when gate drive is applied to the SCRs in the step-start rectifier assembly (when the step-start resistors are bypassed, as described in paragraph 46.3.1.1). Voltages of +5 volts dc and +14 volts dc are developed for A2 from 60 Hz inputs ACI and AC2 by rectifiers CR6 through CR9, filter network C13, C14 and C15 and R37, and regulator U4, in conjunction with zener diode VRI.

46.3.2.4.2 See schematic diagrams 3D60234, sheet 2. Signal +350VSENSE is applied to voltage divider R25, R26, R17 and R15, developing a feedback voltage

(Vfb) which is proportional to the voltage on the storage capacitor banks. The circuit of transistor Q6 is an adjustable constant current drain, which provides an adjustable offset via potentiometer R28 as a means for adjusting the sample input Vfb to pulse width modulator UI. Transistor Q6 draws approximately 6 mA at the junction of resistors R26 and R17 to provide the offset. The input current sample (signal CURRENTIN) is the output of current transformer A5AITI, which samples the total current pulse from FET switches A5Q4, A5Q5, and A5Q6 (schematic diagram 3D60270, sheet 2). The slope compensation circuit consisting of transistors QI and Q2 compensates for peak-to-average current differences as a function of duty cycle (schematic diagram 3D60234, sheet 3).

46.3.2.4.3 Integrated circuit UI is a current-mode pulse-width modulator and controller which generates an error voltage by comparing a precision trimmed +2.5 volts dc reference with a proportional voltage input from the storage capacitor banks at UI pin 2 (Vfb).

46.3.2.5 Switcher-Converter Modules.- See schematic diagrams 3D60270, sheets 4 to 12 and 3D60250, and waveform diagram figure 46-4. Five identical switcher-converter circuits operate in parallel to transform and regulate dc voltage and provide power to the RF panels and drivers.

46.3.2.5.1 Components.- Each switcher-converter module consists of the following: a switcher module (A8, A13, A18, A23, or A28), which converts dc to

172.5 kHz via a full-wave inverter bridge; a current sense transformer (A9TI, A14TI, AI9T1, A24T1 or A29T1) for sampling of inverter current; an output step-down transformer (TI, T2, T3, T4 or T5) for reducing voltage; an output rectifier assembly (AIO, A15, A20, A25 or A30), for converting 172.5 kHz to dc;

and a current-smoothing inductor (L2, L3, L4, L5 or L6). Each module acts as a current-limited source of 50 amperes, nominally. Regulation of output voltage (i.e., voltage across the storage capacitors in the RF panels) is accomplished by turning the switcher modules ON and OFF as required to restore capacitor charge and maintain operating voltage. Each switcher-converter module operates in response to driven input from its dedicated switcher control circuit A37 through A41.

46.3.2.5.2 Control and Output.- See figure 46-3 and waveform diagram figure 46-4. Typically, the switcher-converter circuit consists of a switcher control, mother board A43, a switcher module, and an output rectifier. The following is a description of switcher-converter circuit number one, with the remaining four switch-converter circuits being identical in operation, except for component reference designation and signal identification. Mother board A43 is common to allfiveswitcher-convertercircuits.

(IMarch1995) 46-5

46.3.2.5.2.1 Switcher Control A$7.- See schematic diagram 3D60250, sheets 2 and 3. Inputs to switcher control A37 are a 172.5 kHz clock and switcher module

A8 current-sense feedback signals SWISAMI and SWISAM2. The 172.5 kHz clock is applied to current-sensing amplifier UI and to pulse-width modulator U2, and is used to synchronize their outputs. Current-sense signals SWISAMI and SWISAM2

(shown on schematic diagram 3D60250, sheet 2 as signals ISENSI and ISENS2.)are rectified at the input to amplifier UI, with the 172.5-kHz clock switching the resultant through amplifier UI. The output circuit of amplifier UI develops a ramp voltage, with the current-sense resultant riding on it. The output of amplifier UI is applied to the RAMP input of pulse-width modulator (PWM) U2, where it is developed into a latch inhibit signal. As long as switcher module A8 provides current-sample feedback within tolerance, the U2 internal latch circuit is held OFF, and U2 outputs CTLI and CTL2 continue to trigger control driver FETs Q3 through Q6. The 172.5-kHz clock, at the CT input to PWM U2, also synchronizes signals CTLI and CTL2 to the control drivers, ensuring that control driver FET output signals SWCTLOUT+ and SWCTLOUT- are synchronized with the switched current sense input and clock. If either current sense feedback signal SWISAMI or SWISAM2 is lost or drops out of tolerance, transistor Q2 senses the fault and sends a high to the SHUT port on PWM U2. PWM U2 output signals CTLI and CTL2 are shut off, all drive to switcher module A8 is stopped, and the power supply is shut down.

46.3.2.5.2.2 Mother Board A45.- See figure 46-3. Mother board A43 inputs, two each of SWCTLOUT+ and SWCTLOUT-, are name-changed to outputs SWIDRIA, SWIDRIB, SWIDR2A and SWIDR2B, and applied to switcher module A8.

46.3.2.5.2.3 Switcher Module A8.- See schematic diagram 3D60270, sheet 4.

Inputs to switcher module A8 are as follows: (I) +350 volts dc from capacitor banks A3 and A4, and, (2) switcher control FET outputs SWIDRIA, SWIDRIB, SWIDR2A, and SWIDR2B. The +350 volts dc is applied to switcher FETs QI through

Q4, where it is modulated as FETs QI through Q4 are triggered on and off by inputs SWIDRIA, SWIDRIB, SWIDR2A and SWIDR2B. The resulting output from the A8 switcher FETs are pulsating dc signals SWIOUTIB and SWIOUT2, at the primary of step-down transformer TI. Figure 46-4 waveforms for the TI primary are output signals VPRI and iPRI. These outputs combine to produce what is seen as ac voltage by step-down transformer TI. The secondary output of TI is rectified and filtered to produce a precision output of +40 volts dc. Figure 46-4 waveforms for the T| secondary are signals IDI and IOUT. Current-sensing transformer A9TI feeds current-sample signals SWISAMI and SWISAM2 back to switcher control A37. Switcher control A37 either shuts down the power supply or allows it to operate. These signals are a continuous monitor of the correct operation of the CPS.

46.3.2.6 Switcher Controls A$7 through A41.- See schematic diagram 3D60250, sheets 2 and 3 and waveform diagram, figure 46-4. The switcher control senses current signal feedback sample from the switcher module and determines whether the power supply stays on-line or off-line. A separate switcher control (A37 through A41) drives each switcher module (A8, A13, A18, A23 or A28), respectively. Inputs are the 172.5 kHz inverter clock from CPS control to voltage follower QI, and the inverter current samples SWISAMI and SWISAM2 from the current sense board (A9, A14, A19, A24 or A29) (schematic diagram 3D60270, sheet 4), to operational amplifiers UI and U3. Outputs are alternating PWM controller U2 drive signals CTLI and CTL2 to control driver FETs Q3 through Q6, and a current sample for BITE out of operational amplifier U3 (schematic diagram 3D60250, sheet 2). Current samples SWISAMI and SWISAM2 from current transformer

46-6 (IMarch1995)

TI are rectified by diodes CRI and CR2 and fed to pin 3 of operational amplifier UI (schematic diagram 3D60250, sheet 2). For current-mode control, a portion of the clock pulse is integrated and coupled at pin 3 with the current sample. The output of operational amplifier UI is a current-sample ramped voltage, pulsing on and off at the clock rate. This ramp voltage drives the RAMP input to PWM controller U2 (pin 7). Integrated circuit U2 is a high speed PWM controller which is used in current mode control of the converter module.

46.3.2.7 Switcher Modules A8, AI_, A18, A2_, and A28.- See schematic diagrams 3D60270, sheets 4 through 10 and 3D60250, and waveform diagram, figure 46-4.

The switcher module converts the pulsed outputs of the switcher control, via mother board A43, into an alternating voltage by PET switching. It also feeds back a current sense signal to the switcher control.

46.3.2.7.1 Switcher Bridge.- See schematic diagrams 3D60270, sheets 4 and 9.

FETs QI through Q4, in a full-wave bridge configuration, make up the switcher bridge. The FETs are driven ON in alternating pairs (QI and Q4 together, then Q2 and Q3 together) via drive transformers A8AITI and ASAIT2, with a controlled off-time between the alternating drive pulses. This causes the dc input voltage to appear at current-sense assembly A9 and output-rectifier assembly AIO as an alternating voltage, with pulse-width control of the switch on-time determining the switcher output voltage level. Each switcher bridge, part of switcher module A8, A13, A18, A23 or A28, obtains its input drive from dedicated switcher control A37 through A41, respectively.

46.3.2.7.2 Switcher Module Output.- See schematic diagram 3D60270, sheets 4 through 10 and switcher module waveform diagram, figure 46-4. The output of the switcher bridge, consisting of FETs QI through Q4, is stepped down by output transformer TI, T2, T3, T4, or T5 from 350 volts ac (peak) to 55 volts ac (peak). This is rectified by output rectifier AIO, A15, A20, A25, or A30 and applied through current smoothing output inductor L2, L3, L4, L5, or L6, respectively, to the load bus. Pulse width control, by switcher control A37, A38, A39, A40 or A41, results in a controlled pulsed dc voltage across the output inductor and a proportional direct current (IOUT) through it. Switcher current is sampled on the primary of the output transformer TI (via current sensor A9, A14, A19, A24 or A29) and fed back to the appropriate switcher control. The switcher control controls the width of the pulse-drive signal to bridge FETs QI through Q4 and the output current. The resulting current flow through the inductor, and the primary of transformer TI, is directly proportional to the voltage output and inversely proportional to input pulse-width. This current is limited, through the current sense feedback loop (signals SWISAMI and SWISAM2), to a preset level of 50 amperes (nominal) per switcher module when the switcher bridge is operating.

46.3.2.8 CPS Control A_I.- See schematic diagram 3D60302, timing and control waveform diagram, figure 46-5, and PAL timing diagram, figure 46-6. CPS control A31 is a central processing board for most of the timing, control, and BITE data signals involved in CPS operation. Timing and control waveform diagram, figure 46-5, relates these signals to CPS dc voltage output. PAL timing diagram, figure 46-6, specifies operation of PAL U20.

46.3.2.8.1 Timing Generation and Distribution.- See schematic diagram 3D60302, sheets 2, 3, 4, 6 and 8 and figure 46-6. All CPS timing or clock signals are derived from the system 5.2 MHz clock input to CPS control A31. Clock and enable inputs, signals CLOCKINA and CLOCKINB, and signals ENINA and ENINB, (1 March1995) 46-7 respectively, are applied to differential receivers UI9. The outputs of UI9 are signals 2.6MHZ and CHARGEEN-, applied to stagger programmable array logic (PAL) U20. The buffered outputs of PAL U20 are: (I) five staggered 346.66-kHz switcher-converter timing signals SWICL- through SW5CL-, (2) the up-converter timing signal UCSYNCOUT, (3) the 86.66-kHz house power supply timing signal HSSYNCH, and (4) the 43.33-kHz bus regulator syne signal SYNCSAMPLE. PAL U20 output TTL clock signals SWICL- through SW5CL- are applied to staggered pulse drivers U16 and U17, and to connector P1 pins 32 through 36 as clock signals SWICL through SW5CL for CPS timing. PAL U20 clock output signal UCSYNCOUT is applied to sync driver transistor U23 pin 9, and is sent to step-up converter A2, via connector J2 pin 18, as clock signal UCCLK. Timing signal HSSYNCH is applied to sync driver transistor U23 pin 13, and is sent to house supply control A36, via connector J2 pin 2, as clock signal HSCLOCK. Sync output signal SYNCSAMPLE is applied as follows: (I) to PAL U21 pin 10 as the syne pulse for the generation of enabling signals, (2) to differential receiver U18 pin I, which develops signals SYNCSAMA and SYNCSAMB and applies them as sync sample outputs, via connector J1 pins 12 and 13, respectively, and (3) to pin 8 of operational amplifiers U5 and U6, as sync pulses for the capacitor bank coarse and fine charging circuits.

46.3.2.8.2 Enable Distribution.- See schematic diagram 3D60302, sheets 2 through 5. Enable generation PM_ U21 identifies whether switcher module A8 or A13 is to be the single run-on module and controls enable signal distribution.

Enabling outputs to switcher modules AS, A13, A18, A23 and A28 are developed in PAL U21 in response to signal SYNCSAMPLE from PAL U20 and several status monitor inputs. If any of the following status monitor inputs fail, a fault signal is sent to PAL U21, and enabling pulses to the switcher modules are switched off:

(I) at PAL U21 pin 13, fault output signal OTFLT from over-temperature monitors A8SI and A28SI in switcher modules A8 and A28, respectively, via comparator U7 pin 14, (2) at PAL U21 pin 14, fault output HSFLT- from house +12 and +15-volt dc supplies, (3) at PAL U21 pins 5 through 9, voltage fault signals SWIVLTFLT-through SW5VLTFLT- from over-voltage monitors UIO and U14, (4) at PAL U21 pin 16, fuse fault signal FUSEFLT- from fuse detect optoisolator U8, (5) at PAL U21 pin 11, signal CHARGEENBQ- from PAL U20, (6) at U21 pins I and 2, switcher number I (module A8) and 2 (module A!3) signals SWIOK- and SW2OK- from operational amplifiers U14 pin 14 and U14 pin 13, respectively and, (7) at PAL U21 pin 15, signal 350VDCFLT, from operational amplifier UIO pin 2. As long as the input at U9 pin 3 is above +270 volts do, the low 350VDCFLT output at UI0 pin 2 ensures that step-up converter control A2 is operating properly. All outputs are buffered by PAL U21 internal components.

46.3.2.8.3 Switcher-Converter Current Monitor.- See schematic diagram 3D60302, sheets 2 and 5. Samples of switcher bridge current (SWII through SWSI), from each of the five switcher modules, are combined in operational amplifiers U9 and U13. The resultant of combined currents from switcher bridge numbers one and two is at output pin 7 (signal SAM12BR) of operational amplifier U13, the resultant of combined currents from switcher bridge numbers three and four is at output pin 8 (signal SAM34BR) of operational amplifier U13, and the resultant of current from switcher bridge number five is at output pin 14 (signal SAM5BR) of U13. Current-sample signal SAM12BR is applied via connector A31J2, pin 7 to CPS connector J1 pin 8 as signal SAM12; current sample SAM34BR is applied via connector A31J2, pin 24 to CPS connector J1 pin 7 as signal SAM34; current sample SAM5BR is applied via connector A31J2, pin 25 to CPS connector J1 pin 9 as signal SAM5. The switcher current samples are sent to the bus regulator for transmission to the BITE system for interpretation. Parallel samples of

46-8 (1 March1995) current, signals SWISAMFIL and SW2SAMFIL, from switcher numbers one (AS module) andtwo (A28module),are sentto comparatorU14. Theoutputsof comparatorU14pins 14 and 13, signals SWIOK- and SW2OK-, respectively, send enabling signals to PAL chips U20 and U21 when switcher numbers one and two are operational.

46.3.2.8.4 Feedback Enable Control.- See schematic diagram 3D60302, sheets 2 and 8. The purpose of feedback enable control is to provide CPS control board A31 with the timing for recharging the capacitor banks. When the RF transmitter fires, capacitor bank charges are reduced, sending a decaying voltage sample to the regulator bus. This is averaged and compared to the RF amplifier reference voltage in the feedback enable control circuit.

46.3.2.8.4.1 The bus regulator-decoded RF amplifier reference voltages RFINA and RFINB, at unity gain operational amplifier UI pins 2 and 3, respectively, pass through operational amplifier UI to sample-and-hold U5 (schematic diagram 3D60302, sheet 8). A tap-off from the junction of resistors R8 and R9 sends the reference voltage back to the bus regulator, via unity gain operational amplifier U2 pin 6 and connector J1 pin 3, as signal RFOUTBR. The bus regulator-averaged RF amplifier sample voltage VSAMINA and VSAMINB at unity gain operational amplifier U3 pins 2 and 3, respectively, passes through amplifier U3 to sample-and-hold U6. A tap-off from the junction of resistors R35 and R36 sends the averaged voltage back to the bus regulator via unity gain operational amplifier U4 pin 6 and connector Ji pin 5, as signal VSAMOUT. The two sample-and-hold amplifiers are gated by signal SYNCSAMPLE, from stagger PAL U20, to set the sample and reference outputs at a periodic fixed point in time.

46.3.2.8.4.2 Reference sample output from U5 pin 7 is fed directly to ) comparatorU7 pin 4,whereit i_ comparedwiththevoltagesampleat pin5, to produce low output signal FINECHG- for fine charge enable at U7 pin 2. This is the enabling signal applied as the capacitor bank approaches full charge. The reference sample at U7 pin 6 is also reduced by voltage divider resisters R22 and R23, compared with the voltage sample at comparator U7 pin 7, and produces low output signal COARSECHG- for coarse charge enable at U7 pin I. Both enabling signals are initially applied when the capacitor bank charge drops from iu±i charge. AS une capacitor banks approach full charge, signal COARSECHG-diminishes toward zero first, removing coarse charge enabling. As full capacitor bank charge is reached, signal FINECHG- diminishes toward zero, removing fine charge enabling. The cycle repeats after each transmitter pulse.

46.3.2.8.5 Fuse Monitor Circuit.- See schematic diagram 3D60302, sheet 6.

Fuse detect circuit optoisolator U8 interprets the presence of an input voltage (voltage across a fuse) as an indication of a blown fuse. When the fuse blows, zener diode VR5 limits the input voltage to 5.1 volts dc and the U8 LED portion conducts between pins 5 and 7. The LED puts a voltage on pin 2 of the transistor portion of U8 and turns it on and switches resistor R47 pin 2 to ground potential, via pins 3 and I of the transistor. Signal FUSEFLT-, at +5 volts de, drops to practically zero volts dc, sending a fault signal to enable distribution PAL chip U21 and shuts off all enabling outputs. Signal FUSEFLT-is also sent to the bus regulator for BITE processing.

46.3.2.8.6 Overvoltage Monitor.- See schematic diagram 3D60302, sheets 6 and

7. The output voltages of switcher modules AS, A13, A18, A23 and A28 are sampledby operationalamplifiersU12 SWIVOUT,U12 SW2VOUT,U12 SW3VOUT,U12 SW4VOUT, and U13 SW5VOUT, respectively. Ccmparators UIO SWIVLTFLT-, UIO SW2VLTFLT-, UIO SW3VLTFLT-, U14 SW4VLTFLT-, and U14 SW5VLTFLT- are set by

(IMarch1995) 46-9 potentiometer R167 to detect voltages in excess of 42 volts dc from any switcher module. If that event occurs, an output low fault (SWIVLTFLT-) is sent to the enable PAL U21, which stops operation of the switcher module and protects the RF panel from excessive voltage. All five circuits work as described for switcher number A8 inputs as follows: signals SWl (40 volts do) and SW_÷40V (80 volts

dc) are applied to CPS control board A31, eonnecto_ J2 pins 12 and 29, respectively. Voltage divider RI05, RIO9, and R110 reduce the voltage at SWIVOUT comparator U12 pin 3 to approximately 42 volts do, with U12 pin 2 voltage at 40 volts dc. With a resultant output of approximately 3 volts dc at

U12 pin I and SWIVLTFLT- comparator UIO pin 6, and with _167 set to hold a fixed

+3 volts dc on pin 7 of UIO, the fault output (SWIVLTFLT-) from comparator UIO to enabling PAL U21 is high (no fault). If signal SWIV at A31J2 pin 12 increases to 42 volts dc, the voltage at A31J2 pin 29 increases to 82 volts do, the voltage at SWIVOUT comparator U12 pin 3 increases from 42 volts dc to 43 volts do, and the voltage at U12 pin 2 is also at 42 volts dc. This reduces output signal SWIVOUT at U12 pin I to about I volts dc (43V -42V). With the fixed +3 volts dc at SWIVLTFLT- comparator UI0 pin 7 now comparing with +I volt dc at UI0 pin 6, the 2 volt dc input differential produces a low fault output

(signal SWIVLTFLT-) from UIO to enable PAL U2_, stopping operatio_ of the faulty switcher-converter module. The remaining four overvoltage monitor, circuits operate identically, with the only differences being in signal inp_t nomenclature and component reference designators.

46.3.2.9 House Supol_.- See schematic diagrams 3D60770, 3060_! _!_ee%s _ and

3, 3D60270 sheet 3 and functional block diagram, fJgu_ $6_I. Ti_c l_ouse supply consists of three small regulators which provide io_ voltage po_e_ _o the CPS and to the bus regulator. The house supply consists ¢f pr_ma_'y p<_;_;

transformer T6 and three regulators, with outputs (_f _15 a_d _2 J_kts do, -15 volts do, and +5 volts dc. The regulators are driven from a eo_o_ swi[¢_ assembly, operating at 86.66 kHz from house supply coY_tcsl _36_ _h_o_gh _hree separate windings of transformer TT.

46.3.2.9oi House Supply Control A$6.- House supply control A36 (schematic diagram 3D60270, sheet 3) provides switching drive to FFFrs QI and Q2 _f_ switcher

A32 (schematic diagram 3D60221, sheets 2 and 3), in response to the following inputs: (I) signal +19VSENSE feedback from the +15-volt/+12-volt dc regulator to

+19VSENSE comparator U3 pin 7, (2) signal +5VSENSE to +5VSENSE comparator U3 pin

9 and, (3) switcher transformer TI current sense, signal IXFMRIN, to iXFMRIN comparator U3 pin 4. The voltage inputs are applied via the house control A36

+19-volt overvoltage sensor and +5-volt overvoltage sensor, and the current sense input is applied via the A36 over-current sensor. If all of these parameters are within their design tolerances a low appears at PWM UI SHUT pin

10 and does not allow PWM UI shutdown° The output drive from A36 is synchronized with the 86.66-kHz clock (signal SYNCIN) via CPS control A31.

Signal SYNCIN is applied to PWM UI SYNC port, via a NAND gate buffer U2 pin 8.

PWM UI output at pins 11 and 14 (signals OUTA and OUTB, respectively) is applied to output transformer TI, which provides four outputs, signals DRIVEl+, DRIVEl-, DRIVE2+ and DRIVE2- to switch assembly A32. If any of the three previous inputs exceeds its normal tolerance, a low is applied to the other NAND gate U2 pin I or 5, sending a high shutdown signal to pin 10 (SHUT) on PWM U_. Output signals

DRIVEl and DRIVE2 are removed from switch assembly A32 which, in turn, shuts off all house power supply regulators. Normal operation is in effect when all inputs to SHUT driver NAND gate U2 are HIGH, thus the NAND gate output is LOW to

46-10 (IMarch1995) pin 10 (SHUT) on PWM UI. Under these conditions, there is no shutdown of the house supply. Signal REMOTEON, via connector PI/T, also shuts down PWMUI.

46.3.2.9.1.10vercurrentShutdown.-CurrentsensesignalIXFMRIN,from transformer TI on switch assembly A32, is applied to IXFMRIN comparator U3 pin

4. Positive excursions of transformer TI input are half-wave rectified and filtered to give a positive voltage between +2.5 and +4.0 volts dc at comparator U3 pin 4 (high). A reference voltage on amplifier U3 pin 5, from P'_ UI pin 16, is set between +2.35 to +4.1 volts dc by potentiometer R4 to balance the over-current voltage input at pin 4 (high). This is normal operation, providing a non-inverted high output at amplifier U3 pin 2. Positive feedback to amplifier U3 pin 5 is blocked by reverse biased diode CR4. If transformer TI current increases (overcurrent), voltage at U3 pin 4 increases and changes the balanced inputs. The output at amplifier U3 pin 2 goes low, sending negative feedback to amplifier U3 pin 5, via forward biased diode CR4. This cancels out the positive reference and maintains the low output. This low is applied to SHUT NAND gate U2 pin 5, sending a high output to PWM UI pin 10 (SHUT), and the house supply shuts down.

46.3.2.9.1.2 Overvoltage Sense Shutdown.- VOLTAGE ADJUST potentiometer R30 is set to apply a reference voltage of 4.1 volts dc, from UI pin 16, to +19VSENSE comparator U3 pin 6 and +5VSENSE comparator U3 pin 8. Signal +19VSENSE from connector PI pin M is applied to voltage divider RI0 and R11, tapping off 4.1 volts dc to +19VSENSE comparator U3 pin 7. Signal +5VSENSE from connector PI pin S is applied to voltage divider R12 and R13, tapping off 4.1 volts dc to +5VSENSE comparator U3 pin 9. The inputs to the +19VSENSE and +5VSENSE comparators are balanced at 4.1 volts dc, and outputs of the two comparators are low near ground potential and Q2 is held cutoff. A high from pull-up resistor R18 isat transistorQ2 collectorpin3 andon NANDgateU2 pin I,withhigh high inputs to all four pins of SHUT NAND gate U2 the output pin 6 of U2 is low;

this satisfies the requirement for normal operation of PWM, a low input at pin 10 (no shutdown). If any overvoltage input to NAND gate U2 goes low, its output goes high at PWM UI pin 10, and shutdown of all house supply regulators occurs, as follows: A +19-volt dc overvoltage sense or a +5-volt dc overvoltage sense which causes an increase in input voltage divider potential above 4.1 volts dc, causes a high at its respective amplifier output (+19VSENSE comparator U3 pin I or +5VSENSE comparator U3 pin 14). When transistor Q2 conducts, SHUT NAND gate U2 pin I is switched to ground potential (low). This low sends a high output trigger to UI pin 10 (SHUT), and the house supply shuts down. The current through resistor R16, produces a positive potential at the base of transistor Q2 and turns transistor Q2 on by either of the following paths:

I. Voltage divider action from resistor R14, diode CR6, and resistor R16 puts a positive potential, developed across resistor R16, on transistor Q2 base;

2. Voltage divider action from resistor R15, diode CRT, and resistor R16 puts a positive potential, developed across resistor R16, on transistor Q2 base;

The current through resistor R16 causes conduction of…