Amendment 0004 - Attachment J-1 - CMM Control Signals.pdf

Attachment J-1 Clutter Map Memory CCA

Control Signals

FAA SIR

693KA7-18-R-0010

Amendment 0004

TI 6310.26

2--214 compares the values of the two ZVFs and outputs the Greater Zero Velocity Filter (GZVF) to both map-update paths. The alternate magnitudes and GZVFs are multiplexed on the ND0 through ND9 and CCRPZVF0 through CCRPZVF9 lines. The filter allocation to map-update paths A and B is as follows:

Update Data Lines CPI A Filters CPI B Filters

A ND0--9 --0 GZVF +1 +3 --4 --2 --0 GZVF +1 +3 --2

B CCCRPZVF0--9 +0 GZVF +2 +4 --3 --1 +0 GZVF +2 --3 --1

2.3.2.5.2.1.2.1.1.1 Peak ZVF Controls. System batch control signals initiate the peak ZVF select logic to input data and select the peak ZVF. The following batch control signals are used:

Signal Description

BCCTLCC00 data capture enable signal for map-update A

BCCTLCC01 data capture enable signal for map-update B

BCCTLCC02 minus zero filter interval indicator

2.3.2.5.2.1.2.1.2 Previous Scan Data Storage. See figure 11--24, sheet 2. Mass memory, consisting of 55 dynamic RAMs on clutter map A4A110, provides storage for updated filter magnitudes for a complete 256--CPIP antenna scan. The memory stores the magnitudes and sends them to the clutter map control board when the next scan magnitudes are available for updating. The memory transceiver serves as the interface between the memory and map-updates A and B. When a new map value is available, the transceiver transfers the value from map-update A or B (CCCMDATIA0 through CCCMDATIA7 or CCCMDATIB0 through CCCMDATIB7) to memory. When map-update A or B begins to update a new scan, the transceiver transfers the previous scan magnitude (CCCDATIA0 through CCCMDATIA7 or CMCMDATOB0 through CCCMDATOB7) from memory to the update circuit.

The mass memory is divided into a clutter map for ZVF magnitudes, and a residue map for NZVF magnitudes.

2.3.2.5.2.1.2.1.2.1 ZVF Clutter Map. The ZVF clutter map covers the entire scan area: 512 CPIs by 9 filters by 32 RCs, and 512 CPIs by 1 filter by 941 RCs.

2.3.2.5.2.1.2.1.2.2 NZVF Residue Map. The NZVF residue map covers the scan area from 0 to 2 nmi: 512 CPIs by 14 filters by 32 RCs.

2.3.2.5.2.1.2.1.2.3 Memory Map Controls. See figure 11--24, sheet 2. All memory map control and address signals are generated in the timing and control logic on clutter map control A4A112.

The control signals are generated in a microcode sequencer and memory map address logic network, which are controlled by system clocks and batch control signals from the synchronizer. The microcode sequencer consists of a PROM look-up table and PROM address counter. The PROM sequentially generates control and address signals for the memory map as shown in figures 2--65 and 2--66.

Table 2--34 lists and defines the signals shown in figures 2--65 and 2--66.

2--215

MR--

WRITE

INHIBIT

LOGIC

6568--SP--190B

ORENBL

BCCTLCC04

CCMEMADDR0--7

BCCTLCC05

ADDRSEL--CAS

RNGCTE

ADDRESS

SA1.3TST

10.35MH

BCCTLCC07

CCEDCSEL

CCTI/OSEL--

CCTREDCEN--

CCCHBTGEN--

CCEDCOLEN

CCEDCDTOE--

CCIRENBL

CCIROENBL--

RAS

WE

ROW ADDR

COLUMN ADDR

CCMEMWENB--

CCRAS--

CCSCAS 0--4

MEMORY

ROW/

COLUMN

MUXR

MICROCODE SEQUENCER

MEMORY

MAP

TIMING

LOGIC

STCTALD--PROM

ADDRESS

COUNTER

LOGIC PROM

CCORENBL

MEMORY

BANK

DECODE/

SELECT

BANK SEL CODE

MEMORY

MAP

ADDRESS

COUNTER/

LOGIC

FIGURE 2--65. MEMORY MAP ADDRESS AND CONTROL SIGNALS

2--216

6568--SP--191B

26252423222120191817

10.35 MHZ

STCTRLD--

RAS

CAS

WE

CCIROENBL--

CCIRENBL

CCTI/OSEL--

CCEDCDTOE--

CCEDCOLEN

CCCHBTGEN--

CCEDCSEL--

RNGCTE

ORENBL

ADDRSEL--

10.35 MHZ

STCTRLD--

RAS

CAS

WE

CCIROENBL--

CCIRENBL

CCTI/OSEL--

CCEDCDTOE--

CCEDCOLEN

CCEDCSEL--

RNGCTE

ORENBL

ADDRSEL--

CCTREDCEN--

CCCHBTGEN--

CCTREDCEN--

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

27 28 29 30 31 32

PROM ADDRESS COUNTER CLOCK

PROM ADDRESS COUNTER CLOCK

FIGURE 2--66. MEMORY MAP MICROCODE SEQUENCER TIMING DIAGRAM

2--217

TABLE 2--34. MEMORY MAP ADDRESS AND CONTROL SIGNALS

Signal Description

SA1.3TSTG1 System 1.3--MHz stagger clock

10.35 MHz System 10.35--MHz clock

MR-- System power-up reset

BCCTLC07 Batch start signal

STCTRLD-- Resets microcode sequencer PROM counter

CCEDCSEL-- Select signal for input data to the memory map transceiver

CCTI/OSEL-- Memory map transceiver input/output enable

CCTREDCEN-- Memory map transceiver to EDAC bus enable

CCCHBTGEN-- EDAC check bits generation control signal

CCEDCOLEN EDAC input latch enable

CCEDCTOE-- EDAC output latch enable

CCORENBL Output register latch enable

CCIROENBL-- Clutter map input register enable and error register input latch enable

WE Memory map write enable

BCCTLCC04 Memory map output buffer enable

BCCTLCC05 Control signal for the memory address and bank select counter

CCCMWEMB-- Memory map write enable

RAS Memory map row address strobe from PROM look-up table

CCRAS Memory map column address strobe, activated by system clocks and MR--

RNGCTE Memory map address counter enable

ADDRSEL-- Memory map row and column select signal

CCMEMADDR Eight-bit multiplexed memory map row and column address

CAS Memory map bank select code enable

CCSCAS Memory map bank select code

2--218

2.3.2.5.2.1.2.1.2.4 Error Detection. See figure 2--67. An error detection network on clutter map A4A110 monitors its RAM to locate faulty memory locations, thereby improving the reliability of the module. The error detect network consists of a digital Error Detection and Correction (EDAC) unit and an error register. The EDAC examines each data word that is stored in the clutter map RAM to detect single-bit and multiple-bit errors and correct single-bit errors. Results of the error detection are stored by the error register until the monitoring and control processor enables the register to output the results to the response bus. The error detection function has four operating modes: check bit generation, pass through, error detection, and single-bit error correction. All control and interface signals for the error detection function are generated by the memory map timing and control microcode sequencer.

ERROR

DETECTOR

DATA

INPUT

LATCH

DATA

OUTPUT

LATCH

BIT--IN--

ERROR

DECODER

CORRECTION

LOGIC

CHECK/

SYNDROME BIT

GENERATOR

CONTROL

LOGIC

D16--21

6568--SP--192A

CB0--5

SB0--5

SB0--5

CORRECTION

CODED00--15

D00--15

CCEDCTOE--

CCEDCOLEN

SINGERR--

MULTERR--

MEMORY

CLTPT--

CCCHBTGEN--

LOCAL CONTROLS

ERROR

REGISTER

CCSCAS0--4

EDAC

CCORENBL--

CCTREDEN--

CHECK BIT

INPUT

LATCH

MEMORY

XCVR

FIGURE 2--67. ERROR DETECTION AND CORRECTION UNIT

2.3.2.5.2.1.2.1.2.4.1 Check Bit Generation Mode. See figure 2--67. In the check bit generation mode, six check bits CB0 through CB5 are generated by the EDAC and sent to memory. Check bit generation takes place during a write to memory (when information from clutter map control A4A112 map-update A and map-update B is transferred to memory by the clutter map A4A110

2--219 memory transceiver). The two 8-bit data outputs from map-update A and B are combined and stored in memory as 16 bits. The 16 bits of map-update A and B plus the 6 CB0 through CB5 check bits form a 22-bit word as shown in figure 2--68. A low CCTREDCEN-- signal from the memory map microcode sequencer enables the memory transceiver to send data D00 through D15 to the EDAC. A high CCEDCOLEN signal from the memory map microcode sequencer latches D00 through D15 into the EDAC. A low CCCHBTGEN-- signal from the memory map microcode sequencer causes the EDAC to perform a series of parity checks on the 16 data bits (D00 through D15). The result of the parity checks is 6-bit check bit code CB0 through CB5. The EDAC stores one set of check bits, and places a duplicate set on the D16 through D21 data lines. Data in the EDAC input latch passes through the correction circuit to the output latch, where a low CCEDCDTOE--signal places the unaltered data on the D00 through D15 data lines to the memory transceiver.

The 22-bit data word is then written into memory.

6568--SP--193A

D18D8D3 D4 D5 D6 D7 D9 D11 D12 D13 D14 D15 D16 D17 D19 D20 D21D1 D2D0

DATA

CHECK/SYNDROME

BITS

D10

FIGURE 2--68. MEMORY MAP DATA WORD

2.3.2.5.2.1.2.1.2.4.2 Error Detection Mode. See figure 2--68. On a read from memory, the EDAC latches both the 16-bit data D00 through D15 and check bits D16 through D21. The EDAC generates a second set of check bits from D00 through D15. The check/syndrome bit generator compares (EXCLUSIVE--OR) the second set of check bits with the old stored set. The comparison results in 6-bit syndrome code SB0 through SB5, which is sent to the error detector. The error detector decodes the syndrome bit code. Any syndrome bit code other than all zeros indicates an error. The location of logic highs in the code indicates whether there is a single-bit or multiple-bit error. If there is no error in D00 through D15, error detect signals SINGERR-- and MULTERR--are kept high by the error detector. If the syndrome bit code indicates that there is a multiple-bit error, MULTERR-- is forced low. If the syndrome code indicates that there is a single-bit error, SINGERR-- is forced low.

2.3.2.5.2.1.2.1.2.4.3 Pass Through Mode. See figure 11--24, sheet 2. When no error is detected in D00 through D15, the unmodified contents of the data input are placed in the data output latch and sent from the EDAC to the transceiver on the D00 through D15 data lines. The data output is enabled by memory map microcode sequencer signal CCEDCDTOE-- (active low). EDAC configuration signal CLTPT-- is tied to a logic low to enable data to pass from the EDAC input latch to the output latch. The NCCLTPT signal is the inverted CLTPT-- signal and is available at the clutter map A4A110 output for debugging purposes.

2.3.2.5.2.1.2.1.2.4.4 Correction Mode. See figure 11--24, sheet 2. When a single-bit error is detected, the check bit and syndrome bit codes are sent to a bit-in-error circuit for decoding.

The faulty bit is identified from the codes, and then corrected (inverted) by the correction logic.

Corrected data word D00 through D15 is placed in the data output latch, and output from the EDAC on the D00 through D15 data lines.

2.3.2.5.2.1.2.1.2.4.5 Error Register. See figure 11--24, sheet 2. A 12-bit error detection word is placed in the error register by a high CCORENBL signal (from microcode sequencer signal ORENBL), and held until the monitoring and control processor enables the register to output to

2--220 the response bus. The error detection word (C) contains a 1-bit indicator for single-bit error or multiple-bit error detection, a 6-bit syndrome bit code that identifies the location of the faulty memory Integrated Circuit (IC) within a memory bank, and 5-bit memory address code CCSCAS-- that identifies which memory bank contains the bad component.

2.3.2.5.2.1.2.1.2.5 Map Update Calculations. See figure 11--15, sheet 2. Each map update circuit on clutter map control A4A112 adds seven-eighths of the current map value CMCMDATOA0 through CMCMDAT0A7 or CMCMDATOB0 through CMCMDAT0B7 to one-eighth of the current scan value ND0 through ND9 or CCRPZVF0 through CCRPZVF9. The log adder, function PROM, and map adder perform the logarithmic update calculations. Current map value CMCMDATOA0 through CMCMDATOA7 or CMCMDATOB0 through CMCMDATOB7 is inverted (OLDATA--), and OLDATA--is added to the eight MSBs of current scan value ND0 through ND9 or CCRPZVF0 through CCRPZVF9 in the 8-bit log adder. The 8-bit subtraction result, the two LSBs of the current scan value, and the carry bit of log adder LOGADDCARRY form the 11-bit function PROM address LUPADDRA.

The function PROM stores a conversion table for the logarithmic calculation and yields an intermediate result (U). The intermediate result is added to the eight MSBs of current scan value ND0 through ND9 or CCRPZVF0 through CCRPZVF9, and results in an 8-bit value, the MSB of NORDAT. The two LSBs of the PROM output bypass the adder and become the two LSBs of NORDAT, making NORDAT a 10-bit word.

2.3.2.5.2.1.2.1.2.5.1 Map Value Selection. See figure 11--24, sheet 2. Three 10-bit map values are available as inputs to the data multiplexer: the update calculation NORDAT, current scan value ND0 through ND9 or CCRPZVF0 through CCRPZVF9, and current stored map value CMCMDATOA0 through CMCMDATOA7 or CMCMDATOB0 through CMCMDATOB7 (extended to 10 bits by a logic high MSB and logic low LSB). The DMUXSEL signal selects the data multiplexer output. DMUXSEL, enabled by batch start control BCCTLCC07, normally selects NORDAT. If the data select logic receives interference flag MTINTF-- or unconditional coast flag SBCOAST--, ND0 through ND7 or CCRPZVFO through CCRPZVF7 is selected. The filter and magnitude processor asserts MTINTF--when a RC with interference is detected, and SBCOAST-- when a system fault is detected. If either flag is active (low), the stored map value is not updated for two-to-the-nth scans, where n is a VSP (SC) less than or equal to four. A 1-bit system configuration ready signal CNFGRDY, at system reset MR--, forces selection of CMCMDATOA or CMCMDATOB.

2.3.2.5.2.1.2.1.2.5.2 Boost Factor. See figure 11--24, sheet 2. At map initialization or conditioning, the boost adder adds a 4-bit VSP boost factor (BF) to the four MSBs of 10-bit new map value NF. Map initialization occurs at the first north mark upon power-up, and map conditioning occurs when an antenna polarization switch is detected. Synchronizer signal SBLP/CP--, the polarization switch indicator, and SRARP-- (the power-up indicator) generate the MAPCOND and MAPINIT signals, which select the multiplexer output BF. The multiplexer inputs three VSP BF: IN, CL, and LC.

Initialization or a switch from circular to linear polarization results in the addition of 18 dB (IN or CL). A switch from linear to circular polarization results in the addition of 6 dB (LC). If the boost addition results in a sum large enough to produce a carry out from the boost adder, carry out signal TOPLIMIT forces selection of the 8-bit wide pulled up input. The 8-bit output multiplexer words CCCMDAT1A0 through CCCMDAT1A7 and CCCMDAT1B0 through CCCMDAT1B7 become the new input to the memory maps. The NF0 and NF1 bits from the data multiplexer output are used as CCCMDAT1A0 through CCCMDAT1A9 and CCCMDAT1B0 through CCCMDAT1B9 LSB for the 10-bit input to the multiplexed CCCMAPDAT0 through CCCMAPDAT9 lines.

2.3.2.5.2.1.2.2 Clutter and Residue Map Scaling. See figure 11--24, sheet 4. Multiplexed clutter and residue data lines CCCMAPDAT0 through CCCMAPDAT9 are applied to the scale adder on primitive detector no. 2. During ZVF time periods (clutter map intervals), the clutter map receives

TI6310.26

303 B30--39

MTLOGMAG00--09

CLUTTER MAP CONTROL A4A112

MAP UPDATE A NDO--9

OLDATA--

ZVF

PEAK SELECT

LOGIC

C42

CCMPINIT--

201--5

FROM

M/C

B82--97

CICMTS00--15 16

STIMULUS BUS

3 4 4 4

VSP

RGTR

MUXR

SC0--2

IN0--3

CL0--3

LC0--3

R

DATA

SELECT

LOGIC

B20--27

BCCTLCC00--07

FROM

SYNCR

BCCTLCC08

B28

B78

CICSS09--

C78

B79--81

CICMTPS0--2

A37

PD1PRT1WR--

A38

CICSR09--

CICMTPS0--2

C79--81

PD2PRT7WR--

BCCTL24--31

BCCTL67

FROM

M/C

501 A39

FROM

NC A97

FCPORT0WR--

NCMANRST--

SA2.6TSTG1

SYNCR

SA1.3TSTG1

10.35MHZD

SBLP/CP--

SBARP--

MR--

A04

A06

A09

A08

A16

A13

A19

A18

10.35MHZD+/--

SMLP/CP--

MR1(+/--)FROM

F/M

PROC

8AZ0--7

B11--18

AZ0--7

A21--28

AZA0--7 8

ADDR

LOGIC

A17

SBCOAST--

B40

MTINTF--

NC A31

SYNCR

FROM

3NCCOAST--

CCSCAS0--THRU

CCSCAS4--

CCMEMADDR0--7

CCMEMWENB--

CCRAS--

L

M

N

P

CCMPINIT--

CCEDCSEL

A

B

CCTI/OSEL--

C

CCTREDCEN--

D

CCCHBTGEN--

E

CCEDCOLEN

F

CCEDCDTOE--

G

CCIRENBL

H

J

K

CCPORT0WR--

CCORENBL

TIMING

AND

CONTROL

CCIROENBL--

MAPCOND

MAPINIT

CNFGRDY

LOCAL CONTROL

(TO LOCAL USERS)

CMPORT0WR--

S

T

BF0--3

DMUXSEL0,1

LOGADDCARRY

ND0,1

LOG ADDER

LUPADDRA02--10

FUNCTION PROM

U00--09

U02--09

U00,01 2

MAP ADDER

+5V

NORDAT0--9

DATA MUXR

BOOST ADDER

10 NF0--9

NF6--9

4NF2--54

OUTPUT MUXR

+5V

TOP LIMIT

8 2

8 8

MAP

UPDATE

B

DMUXSEL0,1

S (SAME AS

MAP

UPDATE

A)

T 4

BF0--3

BUFFER

RGTR

RESPONSE BUS

R

C82--97

TO

M/C

203--4C50--59

205--5 8A

B C M L P N D E F

MEMORY

8 5

NC

U

CCMTS00--15

MR1--(+/--)

FROM M/C

FROM F/C

PROC

B82--97

A19

A18

10.35MHZD+/--

SA2.6TSTG1

A09 A08

FROM

SYNCR

A04

CLUTTER MAP

A4A110

CICMTS00--15

XXPWRRST--

SA2.6TSTG1

10.35MHZD

FROM

M/C

CICMTPS0--2 CICMTPS0--2 3

CICMTPR0--2 CICMTPR0--2 3

3CICSS10--

3CICSR10--

B79--81 C79--81

B78

C78

CICSS10--

CICSR10--

LOCAL

CONTROL

TIMING

AND

CONTROL

STIMULUS BUS

16 MEMORY

XCVR

Q00--21

D00--21

CB0--5

SB0--5

D0--15

R00--15

ERROR

DET

SB0----5

8 8

OUTPUT

RGTR

SINGERR--

MULTERR--

CCSCAS0-- THRU 4--

ALL RGTR

ENABLES

ERROR

RGTR U

RGTR ENABLE

LOGIC

H J K

RESPONSE BUS

C82--97

CICMTR00--15 TO

M/C

204--1,3

CCPORT0WR--

6568--CD--072G

G

C M

C D

AT

O

A 0-

-7

C M

C D

AT

O

B 0-

-7

C C

C M

A P

D

AT

0- -9

C C

C M

D

AT

IA

0-

-9

C C

C M

D

AT

IB

0-

-9

C C

C M

D

AT

IB

0-

-7

C C

C M

D

AT

IA

0-

-7

C C

E D

C S

E L

C C

TI

/O

S E

L-

C C

TR

E

D C

E N

N F0

--1

C C

C H

B

TG

E N

C C

E D

C O

LE

N

C C

E D

C D

TO

E

N C

C

LT

P T

C

C

B

67 B

75 A

A

A

B

58 A

57 A

A 58 A

A

A

A

C

27 C

A

A

A

A

C

C

C

C 41B

67 B

75C

C

C

C

77 B

58 B

B

C

C

C 65C

27 C

C C

C M

D

AT

IB

0-

-7

C C

C M

D

AT

IA

0-

-7

C C

R P

ZV

F0

--9

C

IC

M

TR

--1

FIGURE 11--24. TARGET AND TWO--LEVEL WEATHER DETECTOR SIGNAL FLOW DIAGRAM (SHEET 2)

11--133/11--134