Processor Reconfiguration for Wideband Sensor Systems (PROWESS)

The Defense Advanced Research Projects Agency seeks to develop run-time reconfigurable processors that provide autonomous radiofrequency systems with decision-directed situational awareness of complex electromagnetic environments through its Processor Reconfiguration for Wideband Sensor Systems program. Offerors must submit proposals by December 19, 2022 to be evaluated based on their ability to achieve over 200 GOPS/mm2 compute density, 50 nanosecond program switching time, and continuously monitoring 40 GHz total input bandwidth.

There is no set-aside designation for this opportunity. The NAICS code is 541715 and PSC code is C314. No incumbent or current contractors are identified. The solicitation does not provide award values or quantity details but seeks multiple awards over a period of performance anticipated to begin June 1, 2023. Numerical program goals include achieving 100 GFLOPS/mm2 compute density at a 16nm process node and enabling 50 nanosecond program switching times.