ARL 25-18.pdf

Invention Disclosure

ARL 25-18

TITLE OF INVENTION:

Pipeline Level Crossing ADC with Error Integral 2nd Stage

Error signal = Input – LC ADC Output Bell Curve causes in-band harmonics

Kurchuck [1]

EXECUTIVE SUMMARY OVERVIEW:

(the purpose of this overview is to provide a brief summarized overview of the invention as described in this invention disclosure document and a direct explanation on what is new about the invention and information about potential military and commercial uses)

What is this Invention?

(e.g., a short 3-sentence “summarized” description as a more “detailed” description will be required further into this invention disclosure)

Invention Title: Pipeline Level Crossing ADC with Error Integral 2nd Stage

The invention solves the low frequency harmonic distortion described in Kurchuck’s dissertation [1] for level crossing analog-to-digital converters. We have simulated a two stage pipeline level crossing ADC using the integral of the error signal to significantly improve the performance of a level crossing analog-to-digital converter. Pipeline level crossing patent pending inventions ARL 21-13, and ARL 24-23 do not use the integrated error signal method for the present invention.

1. What is the basic premise of the design?

Figure 1. Kurchuk’s dissertation shows in-band harmonic distortion for the error signal (Input – ADC Output) for the near zero slope region (“Bell” region) in a sinewave. The bell part of the error signal causes in-band harmonic distortion. High slope regions (sawtooth regions) have harmonic distortion outside the passband. In [1], Kurchuk presents an analysis of harmonic distortion present in level crossing analog-to-digital converters. A new signal capture method is required to overcome the small number of sample points in the bell region to overcome in-band harmonic distortion.

LC2 Out df/dt Low Pass Filter

LC1 Out

LC2 Out

Resistor Ladder Voltage Levels

LC1 Out

Stage 2 Stage 1

Input Signal 16 Voltage Level, Level Crossing ADC

Error Signal Error Integral

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-8 . 005 . 01 . 025

Time(sec) . 03 . 035 . 04 . 045

Analog Integrator ʃ ʃ(in-LC1)dt

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Digital Integrator ʃ ADC Output Code

Digital Digital

Σ Digital Sum

Figure 2 shows a simulation of a 16 voltage level, level crossing ADC comparing the integral of the error signal instead to the error signal from Kurchuk [1]. The present invention uses the integral of the error signal (Input – ADC Output). For the integral of the error signal, we see a much faster changing signal. This moves the harmonic distortion for the low slope regions to outside of the passband. The present invention significantly improves the signal capture performance.

Figure 3 presents a block diagram of the invention. ARL21-13 presents a pipeline level crossing ADC using discrete voltage levels as illustrated in Figure 4. In Figure 5, ARL24-23

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5Δ 4Δ 3Δ 2Δ 1Δ 0Δ

5Δ 5Δ

5Δ - 3Δ - Fine Level Number

4Δ

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2Δ -

3Δ 3Δ

3Δ - 1Δ -

+ Fine Level Crossings 2Δ 2Δ

2Δ -

1Δ 1Δ

Course Level Number 1Δ

0Δ 0Δ

0Δ - Course Output Code = 0, 5, 10, 15, 20, 25 Course Level Crossings

Fine Output Code = 1, 2, 3, 4 Σ

Fine Resolves Levels Between Course.

Notice there is no overlap between

Course and Fine Levels

Output Code (integer)

Input Signal

CUI//Invention

1 fine voltage step = 0.125 volt

Fine Stage = Stage 2

1 coarse voltage step = 1.0 volt Coarse Stage = Stage 1 AR24-23 CUI//Invention

Input Signal

Comp

Coarse Asynchronous Counter DAC

- Up Out In

1 OR Dn

DAC

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- Reset

Upper n bits

Digital Output Code

Lower m bits

Comp

Asynchronous Fine DAC

Counter

- Gain +

Up Out In

1 Dn

DAC

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Reset also presents a pipeline level crossing ADC based on UP/Down counters with a digital-to-analog-converter feedback. The present invention adds an integration stage after the error amplifier. This results in much better signal capture as shown in Figure 2. The present invention can be used with both inventions ARL21-13 and ARL24-23.

Figure 4. Pipeline level crossing ADC from ARL 21-13 uses flash ADC type comparator banks.

Figure 5. Pipeline Level Crossing ADC using UP/Down Counters from ARL24-23.

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Input Signal 16 Voltage Level, Level Crossing ADC

Error Signal Error Integral

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0 . 005 . 01 .015 .02 . 025 Time(sec)

. 03 . 035 . 04 . 045 .05

16 Voltage Level, Level Crossing ADC

Two Stage ADC Output Code

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-300 0 . 005 . 01 .015 . 02 . 025

Time( sec) .03 . 035 .04 . 045 .05

Time in seconds

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-8

ADC Stage 1 Output Input Signal 16 Voltage Level, Level Crossing ADC

16 Voltage Level, Level Crossing ADC

ADC Output Code Power Spectral Density

Figure 6. 16 Voltage Level, Pipeline ADC Simulation Results for Figure 3.

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32 Voltage Level, Level Crossing ADC

20 Input Signal ADC Stage 1 Output

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32 Voltage Level, Level Crossing ADC

Input Signal Error Signal Error Integral

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-20 0 . 002 .004 . 006 .008 .01 . 012 . 014 .016 . 018

Time(sec) .02 .022 . 024 .026 . 028 .03

100 ADC Output Code

-20 Startup Error

-40

-60

-80

- 100 0 . 0025 . 005 . 0075 .01 . 0125 . 015 . 0175 .02 . 0225 . 025 . 0275 . 03

Time in seconds

Figure 7. 32 Voltage Level, Pipeline ADC Simulation Results for Figure 3.

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Wider Dynamic Range

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Error Signal Integral of Error Signal

Error Signal Large slope (derivative)

Integral of Error Signal

For Figure 6, a two stage 16 level crossing ADC with integrated error provides a 70 dB spurious free dynamic range. A two stage 32 level ADC with integrated error in Figure 7 provides 90 dB of spurious free dynamic range.

Figure 8 presents an error signal comparison for the level crossing ADC from Kurchuk [1] to the present invention. The present invention offers a much faster rate of change than the conventional approach for the “bell” region from [1]. The faster rate of change moves the harmonic distortion for the low slope regions outside the passband. The present invention offers a significant performance increase. The second benefit is the integral of the error signal provides another degree of freedom for the PAR level crossing ADC signal reconstruction algorithm presented in [5] and Figure 9.

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64 Level ADC + PAR LCD Interpolation = 72 dB SINAD

38 dB 40 dB

LCD PAR improvement over DT 6.0 bits

6.3 bits

5.7 bits Ideal Progressive Asinc Reconstruction

AtDiConal ADC = 38 dB SNR Level Crossing Delta (LCD)

Discrete Time SQNR(n) =6.02n + 1.76 dB

(3) (4) (5) (6) (7) Number of Levels (bits) (8)

Figure 9. PAR Interpolation performance comparison. The PAR interpolation in Figure 9, does not use the integral of the error function for signal reconstruction. We will investigate adding it in the future. PAR interpolation provides about 40 dB signal-to-noise ratio improvement over a conventional, Shannon sampling analog-to-digital converter.

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LC2 Out Low Pass Filter PLL FM Demodulator

LC2 Out

Resistor Ladder Voltage Levels

LC1 Out

Stage 2 Stage 1 Phase Integrator

Frequency Modulator

FM(in-LC1)

Input

All use the same Resistor Ladder

LC1 Out ADC Output Code

Digital

Σ Digital Sum

Figure 10 presents a second possible implementation of the present invention using a frequency modulator as a phase integrator instead of an analog integrator. A phase integrator based on a frequency modulator has better performance than an analog integrator. The trade-off is the demodulation process is more complex.

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https://doi.org/10.1117/12.3014164

The present invention shows a 70 dB spurious free dynamic range for 16 voltage levels.

A 32 level version provides 90 dB of spurious free dynamic range.

What is new about this Invention?

The invention solves the low frequency harmonic distortion described in Kurchuk’s dissertation [1] for level crossing analog-to-digital converters. The bell part of the error signal causes in-band harmonic distortion. High slope regions have harmonic distortion outside the passband.

We have simulated a two-stage pipeline level crossing ADC using the integral of the error signal to significantly improve the performance of a level crossing analog-to-digital converter. Pipeline level crossing patent pending inventions ARL 21-13, and ARL 24-23 do not use the integrated error signal method for the present invention.

2. Has this Invention been verified?

(e.g., does it exist, is it factual, is there a test module)

Yes, the invention disclosure shows simulations and results for the present invention.

3. Identify Potential Military Uses of the Invention:

Any application requiring analog-to-digital conversion covering, audio signals, RF signals, radar, sonar, etc.

4. Identify Potential Commercial Uses of the Invention:

Any application requiring analog-to-digital conversion covering, audio signals, RF signals, radar, sonar, etc.

CUI//Invention

PUBLICATION OF THE INVENTION:

If a description of the invention has been published (publicly disclosed, verbally or in writing), list the type of publication and the dates. Please also provide a detailed explanation of the circumstances surrounding this external disclosure (e.g., what are the provisions of a funding agreement, etc.). Also, identify any further planned reports or publications. If none, so state.

not applicable.

LIST ANY KNOWN RELATED PATENTS, PUBLICATIONS or PATENT

APPLICATIONS:

Also identify any previous reports, drawings, publications, or correspondence describing or showing the invention. List any known closely related patents, patent applications, reports, publications, devices, or methods. If none, so state.

ARL24-23 and ARL21-13.

IS AN EMBODIMENT OF THE INVENTION AVAILABLE FOR INSPECTION?

Yes.

NATURE AND EXTENT OF PAST USE, PRESENT USE, AND FUTURE USE

AS WELL AS APPLICATIONS AND ADVANTAGES OF THIS INVENTION:

Past: Performance limited by Shannon sampling. Higher energy requirements for clocked systems transferring data through registers.

Present: We have developed three new analog-to-digital converter algorithms that can provide significant performance improves.

Future: Much higher bandwidth, and much higher performance analog-to-digital converters. Current 4 GHz ADCs are limited to less than 60 dB SNR due to the limitations from Shannon sampling. The present converters use level crossing sampling and are not limited by Shannon sampling.

DETAILED DESCRIPTION OF THE INVENTION:

Provide the following information concerning the disclosed invention and in the indicated sequence (or reference other submitted papers that contain the requested information – please do not cut and paste):

A. Specifically describe the invention and its operation. You may use and attach copies of sketches, prints, photographs, paper, and illustrations, all of which should be signed, witnessed and dated. Alternatively, this form should be signed, witnessed and dated if the invention description is incorporated into this form. Use numbers and descriptive names in descriptions and drawings. For inventions that are methods list the steps involved in the method. For inventions that are apparatus describe all the elements.

See 1.

B. State the advantages of the invention over presently known devices, systems or processes. Also discuss/provide a background of the prior art.

Kurchuk’s dissertation shows in-band harmonic distortion for the error signal (Input – ADC Output) for the near zero slope region (“bell” region in Figure 1) for a sinewave. The bell part of the error signal causes in-band harmonic distortion. High slope regions have harmonic distortion outside the passband. A new signal capture method is presented to overcome in-band harmonic distortion.

C. Discuss the problems which the invention is designed to solve, referring to any prior invention of a similar nature with which you may be familiar (e.g limitations or disadvantages).

See B, solves the “bell” region low frequency harmonic distortion.

D. List all known and other possible uses for the invention.

Any application requiring analog-to-digital conversion covering, audio signals, RF signals, radar, sonar, etc.

E. List the features of the invention that are believed to be novel – how does this invention differ from present technology.

Integrated error signal for the 2nd stage in the pipeline level crossing analog-to-digital architecture. Pipeline level crossing patent pending inventions ARL 21-13, and ARL 24-23 do not use the integrated error signal method for the present invention. The present invention offers further improvements for level crossing analog-to-digital converters. As pointed out in Figure 9, PAR interpolation is currently not using the integral of the error signal for signal reconstruction. We believe another 10-20 dB improvement in the signal-to-noise ratio is possible.

F. Please provide an abstract of your invention. This should be limited to no more than 250 words and will be used to facilitate discussion with the Invention Evaluation Committee.

Invention Title: Pipeline Level Crossing ADC with Error Integral 2nd Stage

The present invention solves the low frequency harmonic distortion in level crossing analog-to-digital converters caused by the low slope regions (bell regions) described in Kurchuk’s dissertation. The methods presented here can also be applied to improve ARL inventions ARL 21-13, and ARL 24-23.