SATPC0041470 Tab 04 4 SOW.pdf

STATEMENT OF WORK

Astrophotonics fabrication of silicon PICs for high-contrast imaging coronagraphy

1. Objective/Requirements The AstroPIC project at NASA Ames Research Center is seeking to manufacture silicon-based photonics integrated circuit (PICs) for laboratory testing. These PICs feature input grating coupler designs that need to be manufactured to fabrication tolerances to enable high efficiency coupling. Applied Nanotools (ANT) will use an electron-beam write lithography process with both full and partial etch capabilities to fabricate silicon PIC devices that meet fabrication tolerances specified below. These silicon PIC devices will be used for high-contrast imaging demonstrations for coronagraphy.

ANT is a registered entity on SAM.gov with ID#: J3Q3ARBLN3H3.

NASA Ames Research Center technical POCs:

Dan Sirbu (AstroPIC Principal Investigator) – dan.sirbu@nasa.gov Kevin Sims (AstroPIC Project Manager) – kevin.sims@nasa.gov

Applied Nanotools POCs:

Cameron Horvath - cameron@appliednt.com

2. Characteristics, Scope, and Specs

Applied Nanotools (ANT) shall deliver a total of 56 photonic integrated circuit devices (referred to as “dies” on the quote) based on the following NASA provided silicon photonic layout design files:

ant_apr26_121_ACHIP.gds – 4 copies diced into 12 dies ant_apr26_121_AstroPIC_main.gds – 12 copies diced into 12 dies ant_apr26_121_AstroPIC_secondary.gds – 4 copies died into 4 dies ant_apr26_121_BBDC.gds – 4 copies diced into 4 dies ant_apr26_121_grating.gds – 4 copies diced into 4 dies ant_apr26_121_Grating_pp.gds – 4 copies diced into 4 dies ant_apr26_121_MEMS.gds – 4 copies diced into 4 dies ant_apr26_121_PCLA.gds – 4 copies diced into 4 dies ant_apr26_121_Polarization.gds – 4 copies diced into 4 dies ant_apr26_121_SPEC.gds – 4 copies diced into 4 dies

Each of the PIC devices shall have the following specifications and fabrication tolerances:

All devices will be Silicon-on-Insulator (SOI) material Partial etch (layer 2) with 70nm (±10nm) depth, with pattering of gratings and partial-etching down to custom etch depth Full etch (layer 1) at 220 nm depth with patterning of waveguides and etching down to the buried oxide (BOX) layer.

Oxide cladding: 2.2 +/- 0.2 micron thickness, deposited using plasma-enhanced chemical vapor deposition (PECVD) process.

Tri-layer metallization (layer 11, 12, 13) for thermal phase shifters and deep trench process for thermal isolation, on applicable devices. TiW and Au layers on 5 wafers total.

Oxide window openings (or MEMS release on MEMS devices – see below) For devices containing Micro-Electro-Mechanical Systems (MEMS) structures:

o Direct metallization (layer 5) o Via openings (layer 40) o MEMS release (layer 6)

Deep trenches for thermal isolation trenches: > 250 microns (applicable to non-

MEMS)

Dicing of 48 layout copies into 56 dies in total (as described above) Shipping to NASA Ames.

3. Place of Performance Delivery of fabricated photonics integrated circuits to:

NASA Ames Research Center Building N255 Central Receiving Moffett Field, CA 94035 United States Attention: Dan Sirbu

4. Period of Performance Delivery approximately 16 weeks after receipt of order.