RFI_SOW.pdf

Digital Signal Processing Module (DSPM)

DRAFT Specifications and Statement of Work

Minimum and Maximum Quantities Minimum Order Quantity: 32 units Max Order Quantity Including Options: 390 units

Technical Support – On Site at NRL Minimum Order Quantity: 40 hours Max Order Quantity Including Options: 2,080 hours

Performance Specification for Digital Signal Processing Module (DSPM) 1 Introduction The Naval Research Laboratory (NRL) Tactical Electronic Warfare Division (TEWD) has a need for an electronic digital signal processing module. This module will be used to design and evaluate prototype shipboard and airborne electronic warfare (EW) applications and will be installed and operated within an enclosure that will be mounted to both airborne and shipboard platforms.

2 Digital Signal Processing Module (DSPM)

2.0 Performance Requirements

The offeror shall provide Digital Signal Processing Modules that meet or exceed the performance requirements and other characteristics contained in this specification. Per Section 2.2 below, the DSPM shall comply with the VITA 41.0 and VITA 41.6 “VXS” format. It is acceptable for the offeror to populate each VXS assembly with multiple DSP channels. If the offeror is proposing this approach, the number of channels per VXS assembly must be clearly stated in the Compliance Matrix for Section 2.0. Subsequent compliance matrix entries must specify the number of channels to which the specification applies.

Unless otherwise specified, the Government will assume one channel per VXS assembly for all offeror compliance statements.

2.1 Specifications (DRAFT)

• ADC

o ≥10 bits sampling resolution o Sampling rate 1.0Gsps to 2.5Gsps o 3dB BW ≥ 2.5 GHz o ≥8.5 bits ENOB (125MHz to 1125MHz) o 58 dBc SFDR (125MHz to 1125MHz) o 52 dB SNR (125MHz to 1125MHz) o single ended 50Ω input o ≤+2dBm full scale input o ≥12dBm absolute maximum input.

o Sampling clock input at ½ Fs.

• ADC Clock Input o ≥10 bits sampling resolution o Sampling rate 1.0Gsps to 2.5Gsps o 3dB BW ≥ 2.5 GHz o Single ended 50Ω input o Power level [to be determined; feedback/input from industry is desired] o Clock feed directly to ADC, not multiplied or divided.

o Separate clock for ADC and DAC.

• DAC

o [to be determined; feedback/input from industry is desired]

• Synchronization o [to be determined; feedback/input from industry is desired]

• Digital Communication o Front panel 1000Base-T or SFP o VXS compliant

41.0 – VXS Base standard

41.6 – VXS Gigabit Ethernet control layer

• Must have access to ports A and B at all times.

• May connect through onboard router.

41.1 / 41.2 / 41.3 / 41.4 / 41.5 / 41.8 – VXS protocol layer standards

• All protocols have a common physical layer

• Separate protocol layers for ports A and B o JTAG including all FPGAs o 32 LVDS Pairs to VME64x P2 User Defined Connections @ ≥ 100 MHz.

Connected directly to a DSP Critical FPGA.

Configurable as input or output.

Configurable as differential or single ended.

Run time reconfigurable in sets of 4 or less.

o 1000Mbps links between FPGAs ≤1us maximum latency o ≥4 SE bits shared by all DSP Critical FPGAs.

≥100 MHz from any FPGA to all other FPGAs.

Notes :

• VXS protocol layer will be unused in the near term, or perhaps used as the control layer if 41.6 is not supported by other devices in the system. However, since most, if not all of the proposed VXS protocol layer standards use the same physical layer (four Multi-Gigabit links per port) the board should be able to support a number of choices for the protocol layer. Meeting this requirement will virtually necessitate that the links be routed to an FPGA, as any sort of protocol-specific router will constrain the ports to the specific protocol.

FPGA Requirements:

• Dedicated Multipliers o ≥ 4000 dedicated 2-input multiplier blocks (≥18 bits each input).

o Demonstrated capacity of running at ≥312.5 MHz with 75% of multipliers in use.

• Dedicated Memory o ≥ 70 Mb in dedicated memory blocks o ≥ 1000 blocks of memory, each 108 bits wide and 512 words deep, with true dual port access for each block.

o Demonstrated capacity of running at ≥312.5 MHz with 75% of memory in use.

• General Purpose Logic o ≥ 800,000 logic cells.

Notes :

• FPGAs under consideration SX315T or SX475T.

• The demonstrated capacity is intended to ensure the particular speed grade chosen can relatively easily support processing at one-eighth of the maximum required sampling rate.

• The memory block size is intended to demonstrate storage of four sets of 25 bit words. Each word represents 2 12 bit samples and 3 spare bits. Each word can then store eight 12 bit samples, with the memory running at one-eighth of the sampling rate.

• There is no specific requirement for logic cells. However, all logic cells cannot be used just to support the multipliers and memory.

Board and Backplane Requirements:

• “VXS” per VITA 41.0 and VITA 41.6.

• Slot Pitch: .8 inch

• Backplane Control: Ethernet “SGMII”

NOTE: Refer to Section 2.4 of VITA 41.6 Standard

• Backplane Power: Per VXS standard

• Front Panel Connections: Analog In, Out (all other available over backplane)

Environmental Requirements:

• Storage Temperature: -55C to +125C

• Operational Temperature: -40C to +85C (at card edge, conduction cooled)

• Shock: ½ Sine, 11 ms, 40g pulse

• Vibration (Random): .1 g^2/Hz, 15 to 2000Hz

• Vibration(Sine): 10g peak, 15 to 2000Hz

• Humidity: 95% condensing

DSPM Desired Delivery Schedule – Base Order Number of Units* Months ARO Cumulative 16 4 4 16 5 20 16 6 36 16 7 52 16 8 68 16 9 84 16 10 100 12 11 112

*Assumes one channel per VXS assembly(unit). Contractor must specify the number of channels per VXS assembly if it is other than one.

Technical Support Offeror shall submit an hourly rate for technical support personnel to support the Government in the integration of the DSPM and the development of firmware. Offeror shall submit the names and resumes of technical support staff. Technical support staff must have, at the time of contract award, active US DoD SECRET clearances. Following award, substitutions of alternate technical support staff will require a prior on-site interview (at contractor’s expense) and written approval by the Government.

CLINs Demonstration Units, 2 each, including VXS chassis (supplied to Government for 10 day evaluation), 30 days ARO

Demonstration Unit Test Data and Compliance Matrix, 30 days ARO

Production Unit Test Plan and Test Data Sheet, 30 days ARO Block diagram of test system, test procedure and sample test data sheet.

Software Development Environment, Licenses (2 each) Sufficient to develop firmware and meet all specifications listed in offeror proposal and achieve all features listed in COTS data sheet. Licenses valid for two years from contract award. 15 days ARO

Operating, Technical Manuals – hard and soft copy on CD, 15 days ARO

DSPM Unit Test Data, Submit along with each deliverable production units