II.D Attachment 2 Equal Brand Minimum Requirements.xlsx

XLSX spreadsheet 23 KB Posted Aug 20, 2026

Attached to: Keysight Brand Name or Equal Logic Analyzer
Solicitation number: N6660426Q0405
Issued by: Department of the Navy Naval Sea Systems Command

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Written by GovTribe AI · Aug 20, 2026

This is an Equal Brand Minimum Requirements specification document for the procurement of a Logic Analyzer under solicitation N6660426Q0405 issued by the Naval Undersea Warfare Center Division, Newport (NUWCDIVNPT), a component of the Department of the Navy Naval Sea Systems Command. The procurement is structured as a 100% small business set aside on a brand name or equal basis, with Keysight identified as the reference brand. Offerors must be either Original Equipment Manufacturers (OEM) or OEM-authorized resellers, with resellers required to provide proof of authorized reseller status that the Government will validate prior to award.

The specification establishes comprehensive minimum technical requirements for the logic analyzer across multiple performance dimensions. Physical requirements mandate portability with a weight under 60 pounds, a system volume not exceeding 5,000 cubic inches, and provision of a four-wheeled cart. Power consumption must not exceed 10 amps at 120 VAC. The unit must support a minimum of 136 total channels with at least 128 data channels, accommodate both internal and external clocking with a minimum of 4 external clocks and 4 clock qualifiers, and provide timing sample rates of 2.5 GHz at full channels, 5.0 GHz at half channels, and 10.0 GHz at quarter channels. Additional requirements include 4 Mbytes of memory (expandable to 128 Mbytes) at full channel capacity, a maximum state clock rate of 700 MHz, timing zoom capability of 12.5 GHz or higher, eye scan functionality for signal integrity assessment, oscilloscope interface capability with time-correlated measurements and trigger functionality, DDR memory support upgrades, and comprehensive trigger capabilities with at least 16 trigger positions and 8 pattern evaluation operators. All products quoted must be Trade Agreements Act (TAA) compliant, and the unit must accommodate both single-ended and differential probes with appropriate terminations and grounding connections.

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File	Type	Posted
II.D Attachment 1 - Keysight Required Specifications.xlsx	XLSX spreadsheet	Aug 20, 2026
N6660426Q0405.pdf	PDF	Aug 20, 2026

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Sheet1

Logic Analyzer Procurement Requirement Specification
Number	Requirement Specification	Description
1.0	TAA Compliant	If Keysight or another brand is quoted, it must be TAA compliant.
2.0	Physical Requirements
2.1	Portability	The unit must be portable with a weight under 60 pounds.
2.2	Volume	The volume of the system without the cart should be no larger than 5,000 cubic inches.
2.3	Cart	A cart with 4 wheels must be provided to allow the unit to be rolled wherever required.
3.0	Power Consumption	The unit should draw no more than 10 amps on a 120 VAC receptacle.
4.0	Number of Channels & Clocking
4.1	Clocking Type	The unit should allow for either internal or external clocking on the pods.
4.2	Number of clocks	The unit should support a minimum of 4 external clocks as channels
4.3	Clock qualifiers	The unit should support a minimum of 4 clock qualifiers as channels
4.4	Reset Qualifier	The unit should support 1 Reset qualifier in single clock mode as a channel
4.5	Total Number of Channels	The unit should support a minimum of 136 channels of data, clocks, clock qualifier, or reset qualifier. These channels should be available for State or Timing mode of the unit.
4.6	Minimum Data Channels	The unit should support 128 data channels or more.
5.0	Maximum Timing Sample Rate	2.5 GHz with full channels used (136 channels or more)

5.0 GHz with half channels used (68 channels or more)

10.0 GHz with quarter channels used (34 channels or more)

6.0	Timing Zoom	Must provide a timing zoom of 12.5 GHz or higher at 256 Kbyte(1024 bytes) size or larger
7.0	Maximum State Clock Rate	700 MHz
8.0	Memory Depth Provided	4 Mbytes with full channels used (136 or more)

8 Mbytes with half channels used (68 or more) 16 Mbytes with half channels used (34 or more)

9.0 Optional Memory Capability The unit should be able to accommodate a future memory upgrade of the following:

128 Mbytes with full channels used (136 or more) 256 Mbytes with half channels used (68 or more) 512 Mbytes with half channels used (34 or more)

10.0	Transitional State Storage	The unit should be capable of providing transitional storage such that a state is only stored if a signal change is detected in one of the data channels
11.0	Probe Capabilities	Unit must be able to accommodate single-ended or differential probe capability for all channels. The probes should have the proper terminations to meet all high speed signal rates defined in this specification.
12.0	Provided Probes
12.1	Single-Ended	Unit must come with probes or leads for 136 or more single-ended channels plus a spare for 34 or more single-ended channels.
12.2	Differential	Unit must come with probes or leads for 17 or more differential channels.
12.3	Grounding	The differential or single-ended probes must come with ground connections leads.
13.0	Eye Scan Feature or equivalent	The unit must be capable or providing an 'Eye Scan' feature, or equivalent function, to check for signal integrity without the need of an oscilloscope. This enables eye diagrams across all buses and signals simultaneously, allowing detection of problematic signals.
14.0	Oscilloscope Interface
14.1	Oscilloscope Interface	The manufacturer of this unit must be able to provide an oscilloscope interface even if it is only to the vendor's oscilloscope.
14.2	Time-Correlated measurements	The logic analyzer and oscilloscope waveforms are integrated into a single logic analyzer display.
14.3	Trigger capability	The unit can trigger an oscilloscope or the oscilloscope can trigger the unit itself.
14.4	Physical interface	This interface can use BNC connectors or an Ethernet RJ45 connector for this function.
14.5	Measurement de-skewing	Be capable of measurement de-skewing so that time reference of the logic analyzer unit and the oscilloscope times are aligned.
15.0	DDR Memory Support Upgrade	The unit should be able via upgrades, to support analysis of various memory types like DDR, DDR2, DDR3, LPDDR, LPDDR2, LPDDR3, and Open Nand Flash Interface(ONFi) up to 1400 Mb/s.
16.0	Trigger Capabilities
16.1	Trigger Position	The unit should be capable of allowing the user to specify at least 16 trigger positions for State mode at various points in the data capture.
16.2	Patterns Evaluation	A minimum of 8 patterns evaluated as "=", "!=", ">", ">=", "<", and ",=".
16.3	Trigger sequence step branching	Arbitrary 4-way if/then/else
16.4	Range	At least 4 double-bounded ranges evaluated as in range, not in range
16.5	Edge Detection	At least 3 edge detectors
16.6	Timer	At least 1 timer
16.7	Timer Range	At least up to 24 hours
16.8	Trigger Resource Conditions	Arbitrary Boolean Combinations like "and", "or", "invert", and etc.
17.0	Data Display	Unit must be able to display data as binary, hex, octal, decimal, signed decimal (two's complement), ASCII, and user symbol table.
18.0	Data Export	The unit should be able to export results in some form of a file (example .csv or .xml).
19.0	Data Timestamping	The unit should be capable of providing at minimum the following time stamping conditions previous, absolute, and from trigger. The resolution of the time must be 5nsec or lower.
20.0	Warranty	The unit should come with a minimum of 1 year warranty.
21.0	Startup Assistance	The unit should come with technical startup assistance for at least 3 weeks.
22.0	Required Peripherals	The unit should come with a keyboard, mouse, and a power cord.
23.0	Serial to Parallel Analysis	The unit should provide the capability to extract parallel data information from serial interfaces defined by the user.
24.0	PC Operating System	The unit should use a Windows 10, preferably Windows 11 Operating system
25.0	PC Disk	The unit should come with a removable Solid State Disk with a minimum capacity of 256 Gbytes.
26.0	PC System Memory	8 Gbytes minimum
27.0	Touch-Screen Display	The unit should have a built in touch screen display of at least 14 in. with a minimum resolution of 1024x768. The built in touch screen display should be capable of operating with an external connected video monitor also.
28.0	PC Peripheral Interfaces
28.1	Ethernet LAN	The unit should have at minimum a Gigabit RJ45 LAN connector for purposes of importing or exporting data, printing results, and for various communications.
28.2	USB Ports	The unit should have a minimum of two USB ports. Two of the USB ports must support USB 3.0 or higher.
28.3	Display Ports	The unit should have a means of interfacing with an external monitor via at least one of these interfaces - HDMI or Display Port - with a minimum resolution of 1024x768.
29.0	Signal Thresholds	The unit should be capable of selecting signal threshold levels of ECL, LVPECL, LVTTL, PECL, TTL, or user defined thresholds +/- 5 volts in at least 100 mV increments for all its probes.
30.0	Trigger In Interface	The unit on its main chassis should provide at least one Trigger In signal interface capable of detecting the rising and falling edge of the Trigger In signal. The unit will be able to use this Trigger In signal to trigger the State or Timing modes. It should also be able to accept a Trigger In signal with an a maximum amplitude of +/- 5 VDC.
31.0	Trigger Out Interface	The unit on the main chassis should provide at least one Trigger Out interface signal preferably active high with a voltage not to exceed 5.2 VDC.
32.0	External Clock In Interface	The unit should be able to receive an External Clock In signal on the main chassis up to 10 MHz supporting up to a 5 Vp-p swing.

File details come from the government source that posted it. Updated Aug 20, 2026.