HR001124S0022.pdf

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Scalable Analog Neural-networks (ScAN) Federal contract opportunity
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HR001124S0022
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Defense Advanced Research Projects Agency

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This document is a Broad Agency Announcement (BAA) issued by the Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office for the Scalable Analog Neural-networks (ScAN) program.

The BAA solicits innovative proposals for the research and development of scalable, robust, and power-efficient analog neural network (NN) architectures and circuits that can directly interface with the analog outputs of conventional sensors. The program is structured in two phases, with Phase 1 focused on demonstrating robustness and 200x power efficiency gains with intermediate-scale analog NNs, and Phase 2 focused on scaling analog NNs to large systems with 2000x power efficiency gains. Key program requirements include supporting domestic manufacturing, delivering hardware prototypes and design models in open, non-proprietary formats, and adhering to specific deliverables and reporting throughout the 54-month program. Proposers must address technical challenges related to overcoming scaling limitations, performance fluctuations, device-dependent variations, and long-term performance changes. Proposals are due August 22, 2024, with multiple awards anticipated.

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Broad Agency Announcement Scalable Analog Neural-networks (ScAN)

MICROSYSTEMS TECHNOLOGY OFFICE

HR001124S0022

May 22, 2024

This publication constitutes a Broad Agency Announcement (BAA) as contemplated in Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016 and 2 CFR § 200.203. Any resultant award negotiations will follow all pertinent law and regulation, and any negotiations and/or awards for procurement contracts will use procedures under FAR 15.4, Contract Pricing, as specified in the BAA.

OVERVIEW INFORMATION:

Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office

Funding Opportunity Title – Scalable Analog Neural-networks (ScAN)

Announcement Type – Initial Announcement

Funding Opportunity Number – HR001124S0022

Assistance Listing Number – Not applicable

Dates/Time – All Times are Eastern Time Zone (ET) o Posting Date: May 22, 2024 o Proposers Day: May 15, 2024 o Proposal Abstract Due Date: July 8, 2024, at 4:00 PM o Question Submittal Closed: August 8, 2024, at 4:00 PM o Proposal Due Date: August 22, 2024 at 4:00 PM

Anticipated individual awards – Multiple awards are anticipated.

Types of instruments that may be awarded – Procurement contract or other transaction.

NAICS Code – 541715

Agency contact o Points of Contact

The BAA Coordinator for this effort may be reached at:

HR001124S0022@darpa.mil

DARPA/ MTO

ATTN: HR001124S0022

675 North Randolph Street Arlington, VA 22203-2114 mailto:HR001124S0022@darpa.mil

Section I: Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) is soliciting innovative proposals in the following technical areas: the research and development of scalable, robust, and power-efficient analog neural network (NN) architectures and circuits that could directly interface with the analog outputs of conventional sensors. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice including in-memory-compute (or compute-in-memory) device technology, non-volatile memory development, analog-digital conversion technology, digital accelerator technology, and general-purpose computing technology.

1.1 Program Overview

1.1.1 Background

Today’s NNs are typically implemented on digital systems, whose power consumption makes the processing of high data-rate sensors prohibitive on size-weight-and-power (SWaP)-constrained sensor platforms. Recently, analog in-memory computing (IMC) has been partially introduced into otherwise digital NN systems to increase their power efficiency.

While analog IMC circuitry has been introduced to replace the multiply-and-accumulate operations that are prolific in these devices, these techniques also increase the number of power-hungry analog-to-digital (and digital-to-analog) converters that are required for the digital storage of intermediate results. Furthermore, these architectures are only reliable at small scales due to underlying analog circuit sensitivities to process, voltage, and temperature (PVT) variations; and their power efficiency is consequently limited by analog-to-digital converters (ADCs) required for the digital storage of intermediate results.

1.1.2 Program Description

The Scalable Analog Neural-networks (ScAN) program will develop new analog NNs that could interface directly with the analog outputs of conventional sensors and demonstrate a three-orders-of-magnitude power reduction over existing solutions. ScAN systems will demonstrate inferencing capabilities of analog NNs while eliminating the need for analog-to-digital converters at the raw sensor level.

State-of-the-art (SoA) approaches, such as in-memory computing, use nonvolatile memory (NVM) in passive analog crossbar architectures. NVMs are inherently sensitive to PVT variations, parasitics, and stochastic conductance fluctuations. Additionally, these approaches are also subject to ageing and drift, requiring periodic calibration or retraining to maintain performance. The ScAN program seeks to realize the promise of analog technology to greatly increase the power efficiency of NNs over today’s digital technology while achieving SoA inferencing accuracy, robustness to PVT variations, and scalability.

ScAN will develop the new analog NN processing architectures and algorithms by demonstrating:

Reliable analog NN circuits providing near SoA inferencing accuracy for intermediate-scale networks with 200x power reduction over digital systems, and

Scalable NN architectures for large-scale networks achieving power efficiency gains exceeding 2000x over digital systems.

To achieve program objectives, the ScAN program will address the two key Technical Challenges (TCs):

TC1: Efficiently overcoming scaling limitations and short-term performance fluctuations Current analog NN techniques fail to achieve their predicted efficiency gains at large scales (> 1M inputs, > 50M parameters). Power-efficient scaling is limited by the parasitic resistance of passive crossbars, which degrades the signal dynamic range (requiring more power) as more deep-neural-network (DNN) nodes are connected. Variations in the programable resistive elements—caused by voltage, temperature, and stochastic conductance fluctuations—result in DNN weight errors. The combined effects of parasitic resistance, conductance variations, and SoA ADC-based architectures limit performance (compared to all-digital) to roughly 20x power efficiency gain at small scales.

TC2: Efficiently overcoming device dependent variations and long-term performance changes Process variations result in device-dependent properties that can be partially mitigated at small scales by initially customizing DNN weights for each device separately after fabrication. DNN weights also require compute prohibitive retraining as performance degrades due to device variations caused by ageing and long-term drift. Large scale DNN training (in support of, for example, object detection and tracking) typically requires > 4M core-hours of digital compute, which is not feasible to perform on every device even once, let alone daily. The limit of feasibility for practical applications is several orders of magnitude lower (e.g., 1k-core hours).

To overcome the technical challenges and to realize scalable, robust, and power-efficient analog NNs, innovations in both architecture and hardware are necessary. Proposals should demonstrate an understanding of the ScAN Technical Challenges described above and explain how and why the proposed approach will address each Technical Challenge in the respective program phases. A successful proposal will provide compelling evidence that the proposed architecture, hardware, and algorithms successfully address both Technical Challenges described above.

Diverse expertise from across academia, small business, and the defense industrial base research community may be applicable to achieving all program goals. While not required, DARPA is open to teaming when appropriate and strategic to achieving program outcomes. To achieve the program objectives, the ScAN program will likely require integrated teams with comprehensive expertise covering NN architecture and algorithm development, large-scale analog circuit design and integration, hardware-informed application performance modeling, and image sensor processing.

Solutions that use domestic manufacturing capabilities to achieve program goals are preferred, as DARPA seeks to strengthen DoD access to differentiating technologies.

1.1.3 Program Structure

The ScAN program is a 54-month, 2-phase program with a 27-month Phase 1 (divided into a 15-month Phase 1a (base), 12-month Phase 1b (option)), and 27-month Phase 2 (option). Options may be exercised, at the Government’s sole discretion, based on technical progress measured against the metrics and milestones (Table 2 Program Metrics and Milestones) defined in the BAA and based on funding availability. The performers will address TC1 to demonstrate robustness and 200x power efficiency gains with intermediate-scale analog NNs in Phase 1, and the performers will address TC2 to demonstrate scalability of analog NN architectures and to enable 2000x power efficiency gains for large-scale networks in Phase 2.

The ScAN program BAA is soliciting research proposals for efforts in a single technical area:

Design, Simulation, and Hardware Development of analog NNs. Each performer is required to address all Technical Challenges. The main objectives of each program phase are:

Phase 1a (Base): The program will develop techniques to address TC1 and TC2 for realization of robust, accurate, and power efficient analog NN circuits at intermediate scales (equivalent to at least 1M parameters in digital implementation).

o The performers will research NN architectures and algorithmic techniques to demonstrate power efficiency gain and reduce sensitivity to variations through simulations of targeted intermediate-scale analog NNs.

o The performers will incorporate architecture and algorithmic research results to develop a tape-out ready design of the analog NN demonstration system—at the scale of the equivalent digital model of 1M parameters—to be fabricated and tested in Phase 1b.

Phase 1b (Option): The program will validate the techniques developed in Phase 1a o The performers will demonstrate processing techniques, including training of the intermediate-sized networks, to address both Phase 1 Technical Challenges (i.e., TC1 and TC2).

o The performers will fabricate and test the analog NN circuits designed in Phase 1a to demonstrate robustness (target: 5% or less degradation in sensitivity to the variations), the targeted power-efficiency gain (> 200x), and a total system power1 of less than 1 W, while maintaining 90% or better of the SoA inferencing accuracy with the Government-provided test dataset.

Phase 2 (Option): The program will develop and demonstrate techniques to scale analog NNs to large systems (i.e., the program-specified large-scale systems with the network size equivalent to 50M parameters in digital implementations) while maintaining power efficiency, accuracy, and robustness.

o The performers will design and simulate program-specified large-scale NN systems and demonstrate that their PVT-mitigation techniques are scalable to large scales without the benefit of device-dependent training.

1 Total system power includes all power consumption from the neural network and peripheral circuits, and pre- and post-processing circuits (analog and digital).

o The performers will develop a demonstration system with analog (sensor-proximate) preprocessing circuits capable of handling 1M inputs.

o The performers will develop a tape-out ready design of the program-specified large-scale NN system by Month 12—after the start of Phase 2.

o At the end of Phase 2, the performers will fabricate and test the program-specified large-scale system to demonstrate 95% or better of the SoA inferencing accuracy with 2000x less power.

1.1.3.1 Program-Specific Requirements

Specific requirements of the ScAN program efforts are:

1. Computing resources The program performers are required to utilize existing infrastructure or cloud-based services for all computing needs. No new computing hardware acquisitions are allowed in the proposal given the very short timeline. Program performers are also encouraged to utilize the computational resources provided by the Department of Defense (DoD) High Performance Computing Modernization Program (HPCMP)2; eligibility requirements for the HPCMP can be found at:

https://centers.hpc.mil/users/index.html#accounts.

2. Large-scale analog circuit design, design tool infrastructure, and Silicon IP3 integration If applicable to the proposed technology, the proposal should specify the targeted technology node of a specific foundry. The program performers are required to have prior experience in large-scale analog circuit design and Silicon IP integration on the proposed technology node at the specific foundry. The program performers must have design tool infrastructure commensurate to the targeted technology node at the specific foundry and have a path to acquire required Silicon IP licenses within the program schedule. Given the aggressive program schedule, the program performers are restricted from making any change in the proposed technology node or foundry between Phase 1 and 2 to avoid any design compatibility and schedule issues.

3. Demo hardware input interface The objectives of the ScAN program do not include development or integration of analog sensors.

For benchmarking purposes, the analog sensor interface must be emulated in the demonstration hardware. Digitized data4 will be provided as inputs, and the demonstration hardware will be required to generate the corresponding analog currents to be used as inputs to the proposed NN and/or analog preprocessing circuits. Although performers are required to provide the interface, the energy consumption of the interface will not be included in the metrics calculation.

2 https://www.hpc.mil/ 3 Silicon IP refers to pre-designed, pre-verified building blocks of circuits that are licensed for use in chip design 4 The raw sensor signal is from the analog output of an image sensor, which corresponds to the raw image in a typical camera imaging pipeline, found in, e.g., H. C. Karaimer, et al., ECCV`16, https://karaimer.github.io/camera-pipeline/; M. Brown, ICCV 2023, https://www.eecs.yorku.ca/~mbrown/ICCV2023_Brown.html; and M. Buckler, et

al. arXiv:1705.04352 [cs.CV] https://centers.hpc.mil/users/index.html#accounts

The government provided benchmark targets are the following:

Phase 1: The benchmark target is an analog image sensor with outputs of CIFAR-10/1005 (or equivalent image datasets at 32 x 32 color pixels) in raw pixel format without digital preprocessing.

Phase 2: The benchmark target is an analog image sensor with outputs of BDD100K6 (or equivalent video datasets at high definition (HD)7) in raw pixel format, without digital preprocessing.

For evaluation purposes, the raw signal data transformed from the program-specified datasets may further include noise and other variations (that will be specified by the government team) to simulate real hardware outputs. The nominal specification for the hypothetical image sensors are:

Phase 1: Color CMOS8 Image Sensor o Resolution: 32 x 32 pixel array in Bayer RGB filter pattern9 or equivalent

Phase 2: Color CMOS 720p Image Sensor o Resolution: 1280 x 720 pixel array in Bayer RGB filter pattern or equivalent o Frame rate: 30 frames per second (fps) o Shutter mode: global shutter (preferred) or rolling shutter

4. Specific deliverables for design and simulation efforts

Phase 1a: PVT-tolerant architecture design and NN model in an open standard format and performance simulation results

Phase 1b: Demonstration of program-specified large-scale NN model and projected performance simulation results

Phase 2: Demonstration of hardware-informed large-scale NN model and demonstration of re-training techniques

5. Specific deliverables for hardware demonstration efforts

Phase 1a: Tape-out ready network design of program-specified intermediate-scale NN circuits

Phase 1b: demonstration of intermediate-scale NN hardware solving Phase 1 benchmark problems

Phase 2: Tape-out ready design in Month 12; demonstration of large-scale NN hardware solving Phase 2 benchmark problems at the end of the Phase

5 The Canadian Institute for Advanced Research (CIFAR) 10- and 100- class dataset, https://www.cs.toronto.edu/~kriz/cifar.html 6 Berkeley DeepDrive (BDD) 100k driving dataset, https://github.com/bdd100k/bdd100k 7 HD video standard with a resolution of 1280x720 pixels (720p) and 30 frames per second (fps) 8 Complementary Metal-Oxide Semiconductor 9 https://en.wikipedia.org/wiki/Bayer_filter

See also Section 1.2.3 Program Deliverables for further deliverable requirements and schedule.

Proposers are further required to provide the fabrication requirements and timeline of analog hardware subsystems.

1.1.4 Government Furnished Equipment/Property/Information

The ScAN program does not anticipate any Government furnished equipment or property. Rather, the Government independent validation and verification (IV&V) team in collaboration with performers will provide benchmark datasets as Government Furnished Information (GFI) for NN training and testing. The GFI will include digitized analog sensor data10 appropriate to targeted program milestones.

1.2 Program Schedule, Metrics, and Deliverables

1.2.1 Program Schedule

The ScAN program will be a 54-month, 2-phase program with the period of performance estimated to start in December 2024. A post-award program kickoff meeting will be held to present the technical approaches, to discuss technical and programmatic items of concern, and to interact with the Government team and other program performers. The end of each phase represents a major technical milestone in the program; end-of-phase review meetings will be scheduled to take place approximately four to six weeks before the end of Phases 1a and 1b.

The notional schedule is shown in Figure 1. The key milestones are power and sensitivity estimates for the preliminary (PDR) and critical (CDR) design reviews, along with hardware demonstrations (Demo).

Figure 1 Program Schedule and Milestones

1.2.2 Program Metrics and Milestones

The performance metrics and requirements associated with the target program benchmarks are shown in Table 1 and Table 2. The NN model sizes are defined in terms of numbers of parameters

10 Analog sensor data transformed from the program specified datasets could be obtained through reversed imaging pipeline methods such as H. C. Karaimer, et al. ECCV`16, https://karaimer.github.io/camera-pipeline/; or M.

Buckler, et al. arXiv:1705.04352 [cs.CV] https://karaimer.github.io/camera-pipeline/ in an equivalent digital implementation of the same functions. The proposed technical approach is expected to be capable of at least 100x energy efficiency gains in the hardware alone over digital SoA by the end of Phase 1; efficiency gains coming mainly from proposed software innovations should be well supported by detailed analysis and supplemented with prior work and large-scale simulations.

Table 1 Program Requirements

Requirements Phase 1 Phase 2 Minimum Model size (equivalent digital model size)11: Number of parameters 1M 50M

Hardware demonstration: Input Output 3x103 10 and 100 106 103

Latency (ms) < 16

Table 2 Program Metrics and Milestones

Metrics and Milestones Phase 1 Phase 2 Accuracy (% of state of the art) 90 95 Sensitivity (% accuracy degradation) < 5 Demonstrated system power (W) 1 Demonstrated power efficiency gain > 200x > 2,000x Device-dependent training (core-hours) N/A 1000

Performers are encouraged to propose additional (more challenging) metrics, milestones, benchmark datasets, or schedules.

1.2.3 Program Deliverables

The ScAN program deliverables comprise the following:

1. Program Review and Technical Exchange Meeting materials Program review and technical exchange meetings will be held approximately semi-annually in the form of conferences (see Table 3 Program Event Schedule). These meetings will be typically 2- 3 days each with locations split between eastern, central, and western regions of the United States, e.g., Washington, DC; Dallas, TX; and San Francisco, CA, areas. Performers are required to provide their technical briefs in the form of presentations in technical sessions and are further required to present program progress and financial summaries in individual program review sessions with the ScAN Program Manager and the Government team.

Additionally, there will be separate end-of-phase program review meetings with each individual performer approximately four (4) to six (6) weeks before the end of each program phase. Prior to individual end-of-phase meetings, performers are required to provide to the Government a written report covering

11 Model sizes are in terms of corresponding digital implementation with a similar architecture

a. Technical results

b. Charts of technical results against the program metrics specified in this BAA with explanations

c. Updated technical approaches for the next phases if options are to be exercised

Table 3 Program Event Schedule

Date Program Event

Program Phase 1a

Month 1 Phase 1 Kick-off Meeting

Month 7 Program Review and Technical Exchange Meeting

Month 14 End of Phase 1a Program Review Meeting

Month 15 Phase 1a Final Report due

Program Phase 1b

Month 20 Program Review and Technical Exchange Meeting

Month 26 End of Phase 1b Program Review Meeting

Month 27 Phase 1b Final Report due

Program Phase 2

Month 28 Phase 2 Kick-off Meeting

Month 34 Program Review and Technical Exchange Meeting

Month 40 Program Review and Technical Exchange Meeting

Month 46 Program Review and Technical Exchange Meeting

Month 52 End of Phase 2 Program Review Meeting

Month 54 Phase 2 Final Report due

2. Prototype Delivery Delivery of prototype design, simulations, and hardware shall be made to the Government six (6) weeks prior to the end of the period of performance of every program phase, i.e., Phase 1a, Phase1b, and Phase 2. This will allow the Government team time to independently verify performance of the prototypes. Specific deliverables of individual efforts are listed in Section 1.1.3.1. In addition, the deliverables must also comply with the following:

a. NN designs, NN models, and simulation results must be in an open, non-proprietary format, such as ONNX12

b. Tape-out ready design, hardware prototypes, and corresponding models must be in an open, non-proprietary format for independent verification and validation

c. Remote access to simulations and hardware prototypes must be allowed for the purposes of independent test and evaluation

Performers are required to provide whatever legal access is needed to run, test, or analyze the deliverables, e.g., appropriate software licensing terms with the third party if third party software are needed for the execution, to the Government team. Performers are required to work with the Government team and deliver at least one copy of hardware with associated test plans and test results that demonstrate that the program metrics were achieved. The performers are also required to provide supplementary information specific to individual deliverables to enable independent evaluation and validation by the Government team, e.g., the runtime environment specification.

These may include experimental protocols, publications, data management plan, intermediate and final versions of software libraries, code, and APIs, including documentation and user manuals and/or a comprehensive assemblage of design documents, models, modeling data and results, and model validation data.

3. Quarterly Technical Reports and Status Updates Performers are required to provide technical status updates with overview slides through quarterly teleconferences with the Government team. Comprehensive technical reports with a separate overview slide shall be submitted on a quarterly basis at least two (2) working days prior to the end of each quarter. Additional technical presentations are due at least two (2) working days prior to each subsequently scheduled program event, such as program manager site visits, program review meetings, and technical exchange meetings.

4. Monthly Financial Reports The financial report shall describe resources expended, resources available, any deviation from planned expenditures, and any potential issues requiring the attention of the Government team.

This report shall be provided within ten (10) days from the end of each month.

5. Final Reports After the end of each phase, the report shall summarize the effort in a comprehensive text document. The document shall cover the following in detail:

a. Technical results

b. Charts of technical results against the program metrics specified in this program with explanations

c. Updated technical approaches for the next phases if options are expected and exercised

d. List of publications, copyrights, and patent applications

12 Open Neural Network Exchange (ONNX), https://onnx.ai/

e. Additional materials as defined in the respective contract/award

1.3 Intellectual Property

It is expected that the data, software, model, and design developed under the ScAN program will have the following minimum data rights:

Government Purpose Rights.

Any use of proposer-defined, prior intellectual property (patents, proprietary information, etc.)

should be clearly marked as such within the proposal. Include all proprietary claims to the results, prototypes, intellectual property, or systems supporting the effort and/or necessary for the use of the research, results and/or prototype. If there are any intellectual property claims to future results, prototypes, or deliverables, proposer must explain how these claims may limit Government use of the technology developed under the ScAN program or the development of derivative technologies.

If there are no proprietary claims, this should be stated. For forms to be completed regarding intellectual property, see Attachment D.

Section II: Evaluation Criteria

Proposals will be evaluated using the following criteria listed in descending order of importance: Overall Scientific and Technical Merit; Potential Contribution and Relevance to the DARPA Mission; and Cost Realism.

o Overall Scientific and Technical Merit: The proposed technical approach is innovative, feasible, achievable, and complete. The proposed technical team has the expertise and experience to accomplish the proposed tasks. Task descriptions and associated technical elements provided are complete and in a logical sequence with all proposed deliverables clearly defined such that a final outcome that achieves the goal can be expected as a result of award. The proposal identifies major technical risks and planned mitigation efforts are clearly defined and feasible.

o Potential Contribution and Relevance to the DARPA Mission:

The potential contributions of the proposed effort bolster the national security technology base and support DARPA’s mission to make pivotal early technology investments that create or prevent technological surprise. The proposed intellectual property restrictions (if any) will not significantly impact the Government’s ability to transition the technology.

o Cost Realism: The proposed costs are realistic for the technical and management approach and accurately reflect the technical goals and objectives of the solicitation. The proposed costs are consistent with the proposer's Statement of Work and reflect a sufficient understanding of the costs, skill mix, and level of effort needed to successfully accomplish the proposed technical approach. The costs for the prime proposer and proposed sub awardees are substantiated by the details provided in the proposal (e.g., the type and number of labor hours proposed per task, the types and quantities of materials, equipment and fabrication costs, travel and any other applicable costs and the basis for the estimates).

The effort leverages all available relevant prior research in order to obtain the maximum benefit from the available funding. For efforts with a likelihood of commercial application, appropriate direct cost sharing has been proposed.

Unless otherwise specified in this announcement, for additional information on how DARPA reviews and evaluates proposals through the Scientific Review Process, please visit: Proposer Instructions and General Terms and Conditions https://www.darpa.mil/work-with-us/proposer-instructions

Section III: Submission Information

This announcement allows for multiple award instrument types to be awarded to include Procurement Contracts, and Other Transactions. Some award instrument types have specific cost-sharing requirements. The following websites are incorporated by reference and contain additional information regarding overall proposer instructions, general terms and conditions, and each specific award instrument type.

o Proposer Instructions and General Terms and Conditions: Proposer Instructions and General Terms and Conditions o Procurement Contracts: Proposer Instructions: Procurement Contracts o Other Transaction agreements: Proposer Instructions: Other Transactions

This announcement contains an abstract phase. Abstracts are strongly encouraged but not required. Abstracts are due no later than the due date and time stated in the Overview section.

Additional instructions for abstract submission are contained within Attachments A and B.

Full proposals are due no later than the due date and time stated in the Overview section.

Attachments C, D, E, and F contain specific instructions and templates and constitute a full proposal submission. Please visit Proposer Instructions and General Terms and Conditions for specific information regarding submission methods through the Broad Agency Announcement Tool (BAAT).

BAA Attachments:

o Attachment A: Abstract Summary Slide Template o Attachment B: Abstract Instructions and Template o Attachment C: Proposal Summary Slide Template o Attachment D: Proposal Instructions and Volume I Template (Technical and

Management) o Attachment E: Proposal Instructions and Volume II Template (Cost) o Attachment F: MS ExcelTM DARPA Standard Cost Proposal Spreadsheet o Attachment G: MTO Controlled Unclassified Information Guide signed 11.3.2023 https://www.darpa.mil/work-with-us/proposer-instructions https://www.darpa.mil/work-with-us/proposer-instructions https://www.darpa.mil/work-with-us/procurement-contracts https://www.darpa.mil/work-with-us/other-transaction-agreements

Section IV: Special Considerations

This announcement, stated attachments, and websites incorporated by reference constitute the entire solicitation. In the event of a discrepancy between the announcement, attachments, or websites, the announcement shall take precedence.

All responsible sources capable of satisfying the Government's needs, including both U.S. and non-U.S. sources, may submit a proposal that shall be considered by DARPA. Historically Black Colleges and Universities, Small Businesses, Small Disadvantaged Businesses and Minority Institutions are encouraged to submit proposals and join others in submitting proposals; however, no portion of this announcement will be set aside for these organizations’ participation due to the impracticality of reserving discrete or severable areas of this research for exclusive competition among these entities. Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

As of the time of publication of this solicitation, all proposal submissions are anticipated to be unclassified.

This program is subject to Attachment G: MTO Controlled Unclassified Information (CUI) Guide signed December 14, 2023. All individuals accessing CUI agree to protect CUI in accordance with DoD Instruction 5200.48 CONTROLLED UNCLASSIFIED INFORMATION (CUI) and NIST Special Publication 800-171 Protecting Controlled Unclassified Information in Nonfederal Systems and Organizations.

Federally Funded Research and Development Centers (FFRDCs), University Affiliated Research Centers, and Government entities interested in participating in the ScAN program or proposing to this BAA should first contact the Agency Point of Contact (POC) listed in the Overview section prior to the Abstract due date to discuss eligibility. Complete information regarding eligibility can be found at Proposer Instructions and General Terms and Conditions.

As of the date of publication of this solicitation, the Government expects that program goals as described herein may be met by proposers intending to perform fundamental research and does not anticipate applying publication restrictions of any kind to individual awards for fundamental research that may result from this solicitation. Notwithstanding this statement of expectation, the Government is not prohibited from considering and selecting research proposals that, while perhaps not qualifying as fundamental research under the foregoing definition, still meet the solicitation criteria for submissions. If proposals are selected for award that offer other than a fundamental research solution, the Government will either work with the proposer to modify the proposed statement of work to bring the research back into line with fundamental research or else the proposer will agree to restrictions in order to receive an award.

For additional information on fundamental research, please visit Proposer Instructions and General Terms and Conditions.

https://www.darpa.mil/work-with-us/proposer-instructions

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to determine whether the proposed research shall be considered fundamental and to select the award instrument type. Appropriate language will be included in resultant awards for non-fundamental research to prescribe publication requirements and other restrictions, as appropriate. This language can be found at Proposer Instructions and General Terms and Conditions.

For certain research projects, it may be possible that although the research to be performed by a potential awardee is non-fundamental research, its proposed subawardee’s effort may be fundamental research. It is also possible that the research performed by a potential awardee is fundamental research while its proposed subawardee’s effort may be non-fundamental research. In all cases, it is the potential awardee’s responsibility to explain in its proposal which proposed efforts are fundamental research and why the proposed efforts should be considered fundamental research.

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APEX Accelerators helps businesses:

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o Navigate solicitations and potential funding opportunities.

o Receive notifications of government contract opportunities on a regular basis.

o Network with buying officers, prime contractors, and other businesses.

o Resolve performance issues and prepare for audit, only if the service is needed, after receiving an award.

Project Spectrum is a nonprofit effort funded by the DoD Office of Small Business Programs to help educate the Defense Industrial Base (DIB) on compliance. Project Spectrum is vendor-neutral and available to assist businesses with their cybersecurity and compliance needs. Their mission is to improve cybersecurity readiness, resilience, and compliance for small/medium-sized businesses and the federal manufacturing supply chain. Project Spectrum events and programs will enhance awareness of cybersecurity threats within the manufacturing, research and development, as well as knowledge-based services sectors of the industrial base. Project Spectrum will leverage strategic partnerships within and outside of the DoD to accelerate the overall cybersecurity compliance of the DIB.

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DARPAConnect offers free resources to potential performers to help them navigate DARPA, including “Understanding DARPA Award Vehicles and Solicitations,” “Making the Most of Proposers Days,” and “Tips for DARPA Proposal Success.” Join DARPAConnect at www.DARPAConnect.us to leverage on-demand learning and networking resources.

DARPA has streamlined our Broad Agency Announcements and is interested in your feedback on this new format. Please send any comments to DARPAsolicitations@darpa.mil file://filer1/MTO/MTO_PROGRAM_EXECUTION/MTO_Solicitations/_BAAs_RAs_SNs/Programmatic_BAAs/FY2024/HR001124S0027_COFFEE_TA2/BAA/www.Projectspectrum.io http://www.darpaconnect.us/ mailto:DARPAsolicitations@darpa.mil

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