HR001119S0082.pdf

Broad Agency Announcement Fast Network Interface Cards (FastNICs)

HR001119S0082

August 20, 2019

Defense Advanced Research Projects Agency Information Innovation Office 675 North Randolph Street Arlington, VA 22203-2114

HR001119S0082 FASTNICS 2

Table of Contents

Part I: Overview Information……………………………………………………………………...………3

Part II: Full Text of Announcement………………………………………………………………………..4

I. Funding Opportunity Description

II. Award Information

A. Awards

B. Fundamental Research

C. Disclosure of Information and Compliance with Safeguarding Covered Defense Information Controls

III. Eligibility Information

A. Eligible Applicants

B. Organizational Conflicts of Interest

C. Cost Sharing/Matching

D. Other Eligibility Requirements

IV. Application and Submission Information

A. Address to Request Application Package

B. Content and Form of Application Submission

C. Submission Date and Time

D. Funding Restrictions

E. Other Submission Requirements

V. Application Review Information

A. Evaluation Criteria

B. Review and Selection Process

VI. Award Administration Information

A. Selection Notices

B. Administrative and National Policy Requirements

C. Reporting

VII. Agency Contacts

VIII. Other Information

A. Frequently Asked Questions (FAQs)

B. Proposers Day

C. Submission Checklist

D. Associate Contractor Agreement (ACA)

HR001119S0082 FASTNICS 3

PART I: OVERVIEW INFORMATION

Federal Agency Name: Defense Advanced Research Projects Agency (DARPA), Information Innovation Office (I2O)

Funding Opportunity Title: Fast Network Interface Cards (FastNICs)

Announcement Type: Initial Announcement

Funding Opportunity Number: HR001119S0082

Catalog of Federal Domestic Assistance Numbers (CFDA): Not Applicable

Dates o Posting Date: August 20, 2019 o Proposers Day: July 10, 2019 o Proposal Due Date: October 8, 2019, 12:00 noon (ET)

Anticipated Individual Awards: DARPA anticipates one or more awards for technical area 1, one or more awards for technical area 2, and a single award for technical area 3.

Types of Instruments that May be Awarded: Procurement contracts or Other Transactions (OT)

Agency Contacts o Technical POC: Jonathan M. Smith, Program Manager, DARPA/I2O o BAA Email: FASTNICS@darpa.mil o BAA Mailing Address:

DARPA/I2O

ATTN: HR001119S0082

675 North Randolph Street Arlington, VA 22203-2114 o I2O Solicitation Website: http://www.darpa.mil/work-with-us/opportunities mailto:FASTNICS@darpa.mil http://www.darpa.mil/work-with-us/opportunities

HR001119S0082 FASTNICS 4

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

DARPA is soliciting innovative research proposals for improving network stack performance to realize 100x or more throughput gains, in order to accelerate highly distributed applications, such as training of deep neural networks. Proposed research should investigate innovative approaches that enable revolutionary advances in science, devices, or systems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

This Broad Agency Announcement (BAA) is being issued, and any resultant selection will be made, using procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016.

Any negotiations and/or awards will use procedures under FAR 15.4. Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Federal Business Opportunities (FBO) website (https://www.fbo.gov/).

The following information is for those wishing to respond to this BAA.

A. Introduction/Background Current network subsystems are a bottleneck between multiprocessor servers and the network links that interconnect them. This bottleneck has dramatically worsened over time, stemming in large part from the increasing use of parallelism in processor design to increase central processing unit (CPU) performance. This design strategy is effective for CPUs; however, from the system level, since network link performance has not matched processor gains, increases in integrated computer system performance has been limited. Fundamentally, there is a performance imbalance between network links and other computer system components. This issue remains unaddressed due to strong commercial incentives focus on incremental technology advances across multiple independent market siloes. The separate evolutions of network technology and server technology have made network interface cards (NICs), which bridge the network/server boundary, an afterthought in both technology marketplaces.

At the physical layer, the upper bound for server throughput is imposed by the network interface hardware that connects a machine to a communications network, limiting a processor’s data ingest capability. Other issues, such as limitations in server memory technologies, software that exhibits excessive memory copying, and poor application design also contribute to throttling application throughput.

The differences in data rates at different points in the path from a remote server to a local server illustrate the need for breakthrough approaches in FastNICs. A single optical fiber can (in aggregate) carry about 100 terabits per second of data traffic. Today’s multicore multiprocessors, graphic processing unit (GPU)-equipped servers, and similar computing nodes can (in aggregate) process data at a roughly similar rate. Both are severely limited by the network interface, which typically operate at rates that are 100x – 1000x slower.

https://www.fbo.gov/

HR001119S0082 FASTNICS 5

Figure 1: FastNICs Objectives

Figure 1 represents data rates on a vertical log scale, with an optical fiber on the left and a server on the right. Movement from left to right traces the path data must take through the components from a fiber to a server. As indicated by the multiple colors, the fiber is expected to be wave-length division multiplexed (WDM), as is common in wide-area networks (WANs).

The local area network (LAN) data rates are a function of coding and cabling, and while in principle network striping could be used to achieve multiples of the LAN data rate, e.g., by constructing multiple parallel paths through a “Top of Rack (ToR)” switch associated with each server, this is uncommon in practice.

Network stacks are limited both by network interface cards and system software to 10-100 gigabits per second. This bottleneck is especially important for distributed computation that requires significant communication between the computation nodes. Training of deep neural networks is an exemplar of this class of computation; a significant fraction of machine learning research investigates ways in which the network interface bottleneck can be minimized.

B. Program Description/Scope FastNICs will speed up applications such as the distributed training of machine learning classifiers by 100x through the development, implementation, integration, and validation of novel, clean-slate network subsystems. The program will focus on overcoming the gross mismatches in computing and network subsystem performance. Specifically, computer network interface performance lags the performance of other computer subsystems (RAM, CPU, etc.) by 3 to 4 orders of magnitude.

HR001119S0082 FASTNICS 6

C. Program Structure FastNICs is a four-year program organized into three phases:

Phase 1 (24 months): During this phase, FastNICs will develop an initial, small-scale proof-of-concept that integrates hardware, system software, and application software. The goal of this initial capability is to produce a 5x application speedup over current state-of-the-art hardware and software.

Phase 2 (12 months): This phase will focus on scaling up the Phase 1 proof-of-concept while also achieving a 5x application speedup.

Phase 3 (12 months): The final phase will aim to yield a 4x application speedup over Phase 2.

Specific metrics are shown in Table 1.

Proposals should reflect a four-year base program effort and a nominal start date of May 1, 2020.

D. Technical Areas (TAs) FastNICs is structured into three technical areas:

(1) TA1 Network Subsystem Hardware and Software,

(2) TA2 Applications

(3) TA3 Independent Test and Evaluation.

Layers serve to divide a system into components with logically distinct roles, with interactions between layers via well-defined interfaces. As shown in Figure 2, TA1 and TA2 comprise the layers of the FastNICs network stack. The network subsystem technical area, TA1, is further divided into network interface hardware (TA1.1) and system software support (TA1.2).

Figure 2: FastNICs program Technical Areas TA1 and TA2 as a stack

Proposals to TA1 must address both TA1.1 and TA1.2. A strong TA1 proposal will likely require multiple areas of expertise to support both TA1.1 and TA1.2. TA1 proposers are therefore strongly encouraged to consider an appropriate teaming strategy.

Proposers may submit proposals for any or all technical areas without restriction. However, each technical area must be proposed separately (i.e., each proposal should only address one TA).

Proposers selected for TA3 cannot be selected for any portion of the other two technical areas, HR001119S0082 FASTNICS 7 whether as a prime, subcontractor, or in any other capacity from an organizational to individual level. This is to avoid organizational conflict of interest (OCI) situations between the technical areas and to ensure objective test and evaluation results. If the submission of potentially selectable proposals creates an OCI, the Government will make the final TA selection determination to avoid the conflict.

To support collaboration and the development of technology and systems in the FastNICs program, performers will have an Associate Contractor Agreement (ACA) clause included in their awarded contract or agreement (see Section VIII.E). This clause is intended to ensure appropriate coordination and potential integration of work done by program performers.

TA1.1 Network Subsystem Hardware FastNICs TA1.1 will focus on developing hardware systems to significantly improve aggregate raw server datapath speed. This TA will design, implement, and demonstrate 10Tbps network interface hardware using existing or road-mapped hardware interfaces. TA1.1 computing nodes should reflect the architecture and performance of commercially-available multiprocessor servers. Such servers comprise a set of multicore CPU chips linked by a non-uniform memory access (NUMA) interconnect. Compute nodes may also include many core or GPU computing elements, typically attached via a bus intended for peripherals. TA 1.1 solutions must attach to servers via one or more industry-standard interface points such as I/O buses, multiprocessor interconnection networks, and memory slots. Use of industry-standard interface points is essential for rapid technology transition and industry adoption of FastNICs TA1.1 research results. Further, this requirement ensures that the results of FastNICs TA 1.1 research will persist across multiple generations of network and server technology.

Figure 3: Simplified model of a multiprocessor server

A wide variety of creative approaches exist for TA1.1, with various implications for throughputs, latencies, and consequences for research in TA1.2 and TA2. Proposers should be familiar with and cite prior technical work in this area.

TA1 proposers must provide a scientific and technical argument for their choice of data pathways versus design alternatives, describing the quantitative trade-offs motivating the proposed research plan. The analysis should be sufficiently detailed to demonstrate the proposer’s understanding of the technical challenges that must be overcome.

A proposer’s research plan may include pursuing several approaches in sequence or concurrently, e.g., a conservative design for the short-term to get TA1.2 work under way, and a

HR001119S0082 FASTNICS 8

more radical, longer-term “stretch” design that requires much more research and thus more time to reach a functional state. The proposer’s scientific and technical argument supporting the chosen strategy should follow naturally from the tradespace analysis.

Proposers should explicitly and clearly “connect the dots” from the challenges inherent in their choice of host attachment to how the approaches proposed will address them. For one example in the large space of possible options, in the case of a peripheral bus (see Figure 3), the bus’s intended role in sharing access to server peripherals inhibits scaling throughput by increasing the number of attached data transfer points, as it is a resource shared amongst the peripherals (such as the GPUs illustrated) and the server’s sockets. Bus contention or overload may thus become an issue when multiple cards are attached to the server.

On the other hand, a potential advantage accruing from such a strategy could be reduced time to achieve an initial TA1 capability, in the form of device driver software (written assuming that network interfaces resemble input/output devices). To illustrate the interplay of network hardware with low-level software such as device drivers, consider the common case of a commercial NIC that connects to servers via a peripheral bus, e.g., Peripheral Component Interconnect Express (PCIe). This plan may offer a quick start for TA 1.2 research, as such an attachment is similar to existing systems, except in the number of attachment points. However, meeting the performance goals of the program may require that this number be large enough to challenge assumptions embedded in current systems software (regarding, for instance, serialization, interrupt service, or scheduling) or simply attachment feasibility.

Overcoming the limitations of an inadequate maximum throughput on a shared peripheral attachment bus might necessitate disconnecting lanes of the bus from CPU sockets and replacing the electrical paths with a connection directly to lanes at the socket. For example, the PCIe connects directly to a socketed processor on the motherboard. Data exchange would then be via a non-shared parallel per-socket approach.

Another approach, broadly similar, would be to connect to the server’s memory, comprised of Dual Inline Memory Modules (DIMMs). In a multiprocessor server, memory is processor-local and memory channels connect directly to processor sockets. DIMMs populate slots associated with particular CPU sockets.

This approach would be a major departure from today’s network attachment schemes and may, therefore, demand substantial creativity and a collection of novel software strategies to extract full performance, which is the focus of TA1.2 research.

TA1 proposers should clearly describe any and all assumptions regarding the external network that interconnects the FastNICs TA1.1 servers. For example, under the assumption that wavelength division multiplexing (WDM) is used over single-mode fiber pairs to create a parallelized data path, are optical add/drop multiplexors and/or packet switches presumed to be available on the network side of the proposed FastNICs approach? If so, are these devices necessary for your proposed TA1.1 solution (e.g., in-network packet manipulation as a preprocessing step to prepare packets for traversing in-server paths more efficiently)?

TA1 proposers must include an estimate of the size, weight and power anticipated for sustained operation of their proposed TA1.1 systems. TA1.1 hardware deliverables will include network hardware sufficient to interconnect eight (8) servers. TA1 proposals should include an equipment

HR001119S0082 FASTNICS 9

purchase plan for servers necessary for experimentation and evaluation. As the TA3 Independent Test and Evaluations are expected to be performed at the TA1 performer site, the TA1 equipment purchase plan should anticipate, and be adequate for, concurrent use of equipment for TA1, TA2, and TA3.

TA1.2 Network Subsystem Software FastNICs TA 1.2 will develop the system software required to manage TA1.1 hardware, as well as enable the efficient transit of data to and from processing resources in support of TA 2 applications research. Responsive TA1.2 research proposals will incorporate both novel resource management approaches and novel programming models and interfaces.

Figure 4: TA 1.2 must manage both the TA 1.1 network hardware and the attached server

As illustrated in Figure 4, TA 1.2 must enable the full potential of the proposed TA 1.1 hardware in the context of a server platform, resulting in a working prototype suitable for TA 2 research and experimental validation. TA1.2 must also provide programming interfaces enabling TA 2 to unleash the system’s potential performance. TA 1.2 will collaborate closely with TA 2 while developing the interfaces, APIs, and programming tools (see Figure 5).

Figure 5: FastNICs program Technical Areas TA 1.2 and TA 2

TA 1 proposals should propose novel general programming primitives for connecting multiprocessor systems into a distributed computation in TA 1.2. Here, general means that the proposed primitive can support the range of conditions that multiple TA 2 performers would require.

HR001119S0082 FASTNICS 10

Figure 6: An example interface primitive, the “Computing Surface”

As an illustrative conceptual example, consider the “Computing Surface,” a collection of cores associated with an application, as sketched in Figure 6. It might have sizes and attributes that distributed computations can exploit to reduce software overheads, as well as identify optimal per-application or per-execution stage resource management objectives on the server. Figure 6 declares a 2x2 computing surface, “Tile”, comprising 4 cores; declaration as 2x2 rather than 1x4 might be indicative of the communications pattern amongst its constituent cores. In the Surface_Read invocation, on the left, data ingest needs maximum throughput for the surface, so the component cores are placed on separate CPUs in a notional 4-processor server. For the Surface_Process invocation, on the right, the cores of Tile are placed together on a single CPU to minimize latencies and maximize use of caches.

Libraries for programming languages are used to raise the level of abstraction to that needed by the TA 2 application. TA 1.2 software deliverables must be open source, and compatible with one or more open source operating systems, e.g., a Linux or BSD variant.

In order to realize 100x at the application level, the system software must enable efficient and parallel transfer of data between the TA 1.1 network hardware and the other elements of the system shown in Figure 3.

Strong proposals will address many of the following issues:

Memory: Reducing copies, cache-awareness, NUMA-awareness, maximizing concurrent access, memory protection, sharing, address translation, coherence guarantees, etc.

Computing: scheduling, event-signaling, efficient inter-process communication, cache-aware thread placement, throughput aware scheduling, latency aware scheduling, co-scheduling sets of cores, maximizing concurrency of processing and communication, novel data locking and serialization algorithms, etc.

Device management: GPUs, NICs, interrupts, polling/interrupt hybrids, clocked interrupts, use of programmability, reconfigurable devices, etc.

Networking: Protocol data units, network striping algorithms and units, novel protocols, support for IP, UDP/IP and TCP, etc.

For FastNICs, system software is defined broadly, to be any or all of device firmware, virtualization support, operating systems functions, and libraries to provide efficient application

HR001119S0082 FASTNICS 11

programming interfaces (APIs). It is expected that TA 1.2 efforts will generate software libraries usable by TA 2.

Proposers should distinguish between TA 1.2 approaches that are independent of their TA 1.1 approach and those that are necessitated by it. Examples of the former might include cache-aware or memory hierarchy aware thread and page placement, novel scheduling and event management schemes, and libraries that adapt dynamically to changes in machine resources and user intent. For examples of the latter, consider the case of a TA 1.1 attachment scheme using Dual Inline Memory Module (DIMM) slots as a means to access memory channels associated with each CPU socket.

The data rates and number of these channels offer the raw potential for a fast, highly parallel hardware attachment solution, at the (substantial) cost of losing the coherence support built into NUMA interconnects. System approaches to reestablishing coherence might include the addition of one or more status registers accessible through a more conventional interface such as the peripheral bus. Use of busy-waiting approaches such as polling or more nuanced event-signaling techniques such as clocked interrupts can be used to determine when data has arrived or has been sent. Steps can then be taken, such as invoking specialized code to populate or repopulate entries in flushed data caches towards the goal of consistent views of memory shared amongst elements of a grouping such as the surface sketched in Figure 6. If an approach requires unusual control paths and corresponding software support, proposers should describe both their hardware control path strategies and what other resources are assumed for efficiently performing such tasks, e.g., by use of a plenitude of available cores or use of hyperthreading hardware.

Strategies for maximizing the likelihood of technology transition (e.g., open-source licensing of any modifications necessary to support FastNICs, choice of open-source license, etc.) should be described explicitly and succinctly.

TA1 proposals should provide plans for iteratively developing, testing, and refining their technologies throughout the entire four-year program. TA1 metrics and phase goals are shown below in Table 1.

TA2 Applications TA2, the applications technical area, will explore new applications enabled by the multiple order of magnitude performance increases provided by TA1, and validate the FastNICs objective of increasing application performance. Each TA2 team will design and implement at least one application that demonstrates a 100x speedup when executed on the TA1 hardware/software stack. This technical area will be an important driver for TA1.2 interface/API design.

Strong TA2 proposals will include models of the impacts of throughput increases on the application research proposed for FastNICs. Algorithmic and distributed processing advances should assume the success of FastNICs TA1.

For purposes of modeling the impacts of FastNICs on their proposed application research, TA2 proposers should presume a constant cluster setup of four computing nodes, each with 12TB of 2666 MHz memory, 224 physical cores and a 1-microsecond node-node latency. Estimates for throughput values of 2, 5, 10, 20, 50, 100, 200, 500 and 1000 gigabits per second, as well as the three values for end of Phase metrics for throughputs expected from TA1.1 (2, 5 and 10 terabits per second) should be modeled to estimate the benefit of greatly improved network throughputs

HR001119S0082 FASTNICS 12

on the proposed application or applications. Proposers should provide the scientific basis for these estimates, such as mathematical models based on published research, proposer-developed simulations, traces from measurements, etc. The sole purpose of these estimates is for the TA2 proposers to convincingly demonstrate their depth of understanding of the impact of throughput on their application to DARPA.

Applications proposed for TA2 research should be relevant to DoD and should fit broadly into either machine learning training or image processing or both. An example of relevant training is using tagged images to train a deep learning system to recognize anomalies in a time series of image captures, such as the presence of a strange structure, or a sudden spurt in activity at facilities in an inexplicable location.

Algorithmic advances in distributed machine learning training have been achieved under the assumption that the performance limitations inherent in today’s network stacks will persist indefinitely. The scale of computational challenges facing the DoD requires multiple servers, forcing training of machine learning to become a distributed computation to achieve the required performance. As these computations are often very data-intensive, restructuring distributed training to reduce network use, e.g., by data compression or use of more iterations to avoid passing data, is common. Distributed training is thus an exemplary application of FastNICs.

Applications of the results of such training, such as the analysis of multiple large-scale data streams, provide compelling cases for transition partners.

Many other large-scale applications of interest exist, examples of which include pattern recognition using multiple concurrent streams of data, data generated from arrays of sensors that must be cohered for situational awareness, and real-time fusion with joint analysis of sensor feeds and stored data retrieved from multiple remote repositories.

To reach performance goals, TA2 performers will initially research and model distributed algorithms that require substantial network communication. These models will be used to identify system bottlenecks, which will be used to further focus TA1. The models will also be used to determine the effect of network latency and throughput on application speed.

TA2 will collaborate closely with TA1.2. TA2 proposers should, if an existing version of the application exists, propose an ideal interface for their application or applications. For example, an application might be rewritten with a shared memory model to replace a legacy remote procedure call scheme. These ideal interfaces will enable TA1.2 performers to generate appropriate interfaces, APIs, and programming tools. TA2 will implement their algorithms using TA1.2’s evolving set of programming interfaces, tools, and libraries. Improving application performance to meet FastNICs program goals will require the entire hardware/software stack (TA1.1, TA1.2, and TA2) to operate in an effective, integrated fashion. Workshops for specifying and working through details of these interfaces are included in the program’s schedule.

TA2 proposals should provide plans for iteratively developing, testing, and refining their technologies throughout the entire four-year program. TA2 metrics and phase goals are shown in Table 1.

HR001119S0082 FASTNICS 13

TA Metric Phase 1 (24 months)

Phase 2 (12 months)

Phase 3 (12 months)

Datapath, link to cores >2 Tbps >5 Tbps 10+ Tbps 1.1

Latency, link to cores 100 nsec max, 4 cores in 1 CPU

40 nsec max, 8 cores on 2 CPUs

20 nsec max, 16 cores on 4+ CPUs

Sustained software throughput 12TB in 100 sec 12TB in 30 sec 12TB in 16 sec

1.2 Software Round Trip Time

(3m fiber) nanoseconds nanoseconds nanoseconds

Training time, ImageNet (50 minute baseline) seconds seconds seconds

Training time, labelled 5GB Earth Observing System (EOS) images (90 minute baseline) seconds seconds seconds2

Image processing throughput, 95% accuracy classifier, single FastNICs-equipped server, EOS-sized images images/sec images/sec images/sec

Table 1: FastNICs Metrics

TA3 Independent Test and Evaluation Finally, the Independent Test and Evaluation technical area (TA3) will measure the scientific progress of the program and technical area performance against the metrics in Table 1, and independently provide an objective and convincing evidence base for the impact of FastNICs.

The TA3 performer is responsible for:

Refining TA1.1, TA1.2, and TA2 metrics and devising measurement methodologies, including selection, configuration, and operation of measurement equipment and software tools. These methodologies should enable TA3 to definitively measure performance gains accruing from TA1.1, TA1.2, and TA2 technologies.

Finding and/or generating data required by TA2 (i.e., labeled training data) Facilitating project-level experimentation, data collection, and data analysis Conducting project and program-level evaluations at each Phase and as needed by

DARPA

Of particular interest are evaluation strategies that:

Analyze data movement, data routing, and impacts of statistical phenomena such as locality on the metrics Analyze performance as the number of cores and CPUs in a chassis increases Analyze node and application performance as a function of link throughput and latency Analyze application performance as a function of scale Are lightweight and minimize interference with the system under test Provide concurrent measurement of hardware, software and application performance

HR001119S0082 FASTNICS 14

TA3 proposers should assume that one TA1 and two TA2 proposals will be funded by DARPA, and must include options for an additional performer in each TA1 and TA2. These options should be separate. Cost estimates should reflect the savings from sharing costs, such as proposed measurement apparatus and software tools, while accounting for the additional TA3 effort required to evaluate multiple systems that might be very similar or very unlike in design.

To provide an additional degree of flexibility, multiple options for evaluating an additional TA1 performer may be proposed at different levels of effort.

E. Schedule/Milestones DARPA will conduct quarterly technical reviews, comprising biannual Principal Investigator (PI) meetings and biannual development workshops, during which the program management team will assess progress towards a solution via performer briefings and technical exchanges.

For cost estimation purposes, assume that the locations for PI meetings will alternate between Los Angeles, CA, and Washington, DC, and each meeting will be 2-1/2 days. Program evaluation will be conducted by the Government team throughout program execution. The program schedule and milestones are shown in Figure 6 below.

Government Fiscal Year GFY Quarter Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Kickoff and PI Meetings Development Workshops T&E Activities Transition Demonstrations Integrated System Demos

Phase 1 Phase 2 Phase 3 2020 2021 2022 2023 2024

Figure 6: FastNICs Schedule

F. Deliverables All performers will be required to provide, at a minimum, the following deliverables:

Any technical documents and products derived from work funded by this program Hardware instances produced by TA1.1 with documentation, including electrical requirements, mechanical details, and other details as needed for installation, reliable operation, and diagnosis

Commented source code, any other necessary data, build scripts, and documentation (including at minimum user manuals and a detailed software design document) for all software developed under this program

Annotated slide presentations, delivered within one (1) month after each PI meeting, development workshop, or other program events

Quarterly technical status reports detailing progress made, tasks accomplished, major risks, planned activities, trip summaries, changes to key personnel, and any potential issues or problem areas that require the attention of the Government Team must be provided within fifteen (15) calendar days of the end of each quarter

Monthly financial status reports, provided within fifteen (15) calendar days of the end of each month

A final phase report for each program phase that concisely summarizes the effort conducted, technical achievements, and remaining technical challenges will be due 30 calendar days after the end of each phase

HR001119S0082 FASTNICS 15

A final report at the end of the overall period of performance that summarizes the project

G. Intellectual Property The program will emphasize creating and leveraging open source technology and architecture.

Intellectual property rights asserted by proposers are strongly encouraged to be aligned with open source regimes. BSD-style open-source licenses are preferred. See Section VI.B.1 for more details on intellectual property.

A key goal of the program is to establish an open, standards-based, multi-source, plug-and-play architecture that allows for interoperability and integration. This includes the ability to easily add, remove, substitute, and modify software and hardware components. This will facilitate rapid innovation by providing a base for future users or developers of program technologies and deliverables. Therefore, it is desired that all noncommercial software (including source code), software documentation, hardware designs and documentation, and technical data generated by the program be provided as deliverables to the Government, with a minimum of Government Purpose Rights (GPR), as lesser rights may adversely impact the lifecycle costs of affected items, components, or processes.

II. Award Information

A. Awards

DARPA anticipates a single award for TA1, multiple awards for TA2, and a single award for TA3. The level of funding for individual awards made under this solicitation has not been predetermined and will depend on the quality of the proposals received and the availability of funds. Awards will be made to proposers whose proposals are determined to be the most advantageous to the Government, all factors considered, including the potential contributions of the proposed work, overall funding strategy, and availability of funding. See Section V for further information.

The Government reserves the right to:

select for negotiation all, some, one, or none of the proposals received in response to this solicitation;

make awards without discussions with proposers;

conduct discussions with proposers if it is later determined to be necessary;

segregate portions of resulting awards into pre-priced options;

accept proposals in their entirety or to select only portions of proposals for award;

fund proposals in increments and/or with options for continued work at the end of one or more phases;

request additional documentation once the award instrument has been determined (e.g., representations and certifications); and remove proposers from award consideration should the parties fail to reach agreement on award terms within a reasonable time or the proposer fails to provide requested additional information in a timely manner.

Proposals selected for award negotiation may result in a procurement contract or Other Transaction (OT) depending upon the nature of the work proposed, the required degree of interaction between parties, and other factors. Grants will NOT be awarded under this program.

HR001119S0082 FASTNICS 16

Proposers looking for innovative, commercial-like contractual arrangements are encouraged to consider requesting Other Transactions. To understand the flexibility and options associated with Other Transactions, consult http://www.darpa.mil/work-with-us/contract-management#OtherTransactions.

In accordance with 10 U.S.C. § 2371b(f), the Government may award a follow-on production contract or Other Transaction (OT) for any OT awarded under this BAA if: (1) that participant in the OT, or a recognized successor in interest to the OT, successfully completed the entire prototype project provided for in the OT, as modified; and (2) the OT provides for the award of a follow-on production contract or OT to the participant, or a recognized successor in interest to the OT.

In all cases, the Government contracting officer shall have sole discretion to select award instrument type, regardless of instrument type proposed, and to negotiate all instrument terms and conditions with selectees. DARPA will apply publication or other restrictions, as necessary, if it determines that the research resulting from the proposed effort will present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Any award resulting from such a determination will include a requirement for DARPA permission before publishing any information or results on the program. For more information on publication restrictions, see the section below on Fundamental Research.

B. Fundamental Research

It is DoD policy that the publication of products of fundamental research will remain unrestricted to the maximum extent possible. National Security Decision Directive (NSDD) 189 defines fundamental research as follows:

‘Fundamental research’ means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

As of the date of publication of this BAA, the Government expects that program goals as described herein may be met by proposed efforts for fundamental research and non-fundamental research. Some proposed research may present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Based on the anticipated type of proposer (e.g., university or industry) and the nature of the solicited work, the Government expects that some awards will include restrictions on the resultant research that will require the awardee to seek DARPA permission before publishing any information or results relative to the program.

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to determine whether the proposed research shall be considered fundamental and to select the award instrument type. Appropriate language will be included in resultant awards for non-fundamental http://www.darpa.mil/work-with-us/contract-management#OtherTransactions http://www.darpa.mil/work-with-us/contract-management#OtherTransactions

HR001119S0082 FASTNICS 17

research to prescribe publication requirements and other restrictions, as appropriate. This language can be found at http://www.darpa.mil/work-with-us/additional-baa.

For certain research projects, it may be possible that although the research to be performed by a potential awardee is non-fundamental research, its proposed subawardee’s effort may be fundamental research. It is also possible that the research performed by a potential awardee is fundamental research while its proposed subawardee’s effort may be non-fundamental research.

In all cases, it is the potential awardee’s responsibility to explain in its proposal which proposed efforts are fundamental research and why the proposed efforts should be considered fundamental research.

C. Disclosure of Information and Compliance with Safeguarding Covered Defense Information Controls

The following provisions and clause apply to all solicitations and contracts; however, the definition of “controlled technical information” clearly exempts work considered fundamental research and therefore, even though included in the contract, will not apply if the work is fundamental research.

DFARS 252.204-7000, “Disclosure of Information” DFARS 252.204-7008, “Compliance with Safeguarding Covered Defense Information Controls” DFARS 252.204-7012, “Safeguarding Covered Defense Information and Cyber Incident Reporting”

The full text of the above solicitation provision and contract clauses can be found at http://www.darpa.mil/work-with-us/additional-baa#NPRPAC.

Compliance with the above requirements includes the mandate for proposers to implement the security requirements specified by National Institute of Standards and Technology (NIST) Special Publication (SP) 800-171, “Protecting Controlled Unclassified Information in Nonfederal Information Systems and Organizations” (see https://doi.org/10.6028/NIST.SP.800-171r1) that are in effect at the time the BAA is issued.

For awards where the work is considered fundamental research, the contractor will not have to implement the aforementioned requirements and safeguards. However, should the nature of the work change during performance of the award, work not considered fundamental research will be subject to these requirements.

http://www.darpa.mil/work-with-us/additional-baa http://www.darpa.mil/work-with-us/additional-baa#NPRPAC https://doi.org/10.6028/NIST.SP.800-171r1

HR001119S0082 FASTNICS 18

III. Eligibility Information

A. Eligible Applicants

DARPA welcomes engagement from all responsible sources capable of satisfying the Government's needs, including academia (colleges and universities); businesses (large, small, small disadvantaged, etc.); other organizations (including non-profit); other entities (foreign, domestic, and government); FFRDCs; minority institutions; and others.

DARPA welcomes engagement from non-traditional sources in addition to current DARPA performers.

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

a. FFRDCs FFRDCs are subject to applicable direct competition limitations and cannot propose to this BAA in any capacity unless they meet the following conditions. (1) FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector. (2) FFRDCs must provide a letter, on official letterhead from their sponsoring organization, that (a) cites the specific authority establishing their eligibility to propose to Government solicitations and compete with industry, and (b) certifies the FFRDC’s compliance with the associated FFRDC sponsor agreement’s terms and conditions. These conditions are a requirement for FFRDCs proposing to be awardees or subawardees.

b. Government Entities Government Entities (e.g., Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations. Government Entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority and contractual authority, if relevant, establishing their ability to propose to Government solicitations and compete with industry. This information is required for Government Entities proposing to be awardees or subawardees.

c. Authority and Eligibility At the present time, DARPA does not consider 15 U.S.C. § 3710a to be sufficient legal authority to show eligibility. While 10 U.S.C.§ 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider FFRDC and Government Entity eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the proposer.

2. Foreign Participation Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

HR001119S0082 FASTNICS 19

B. Organizational Conflicts of Interest

FAR 9.5 Requirements In accordance with FAR 9.5, proposers are required to identify and disclose all facts relevant to potential OCIs involving the proposer’s organization and any proposed team member (subawardee, consultant). Under this Section, the proposer is responsible for providing this disclosure with each proposal submitted to the BAA. The disclosure must include the proposer’s, and as applicable, proposed team member’s OCI mitigation plan. The OCI mitigation plan must include a description of the actions the proposer has taken, or intends to take, to prevent the existence of conflicting roles that might bias the proposer’s judgment and to prevent the proposer from having unfair competitive advantage. The OCI mitigation plan will specifically discuss the disclosed OCI in the context of each of the OCI limitations outlined in FAR 9.505-1 through

FAR 9.505-4.

Agency Supplemental OCI Policy In addition, DARPA has a supplemental OCI policy that prohibits contractors/performers from concurrently providing Scientific Engineering Technical Assistance (SETA), Advisory and Assistance Services (A&AS) or similar support services and being a technical performer.

Therefore, as part of the FAR 9.5 disclosure requirement above, a proposer must affirm whether the proposer or any proposed team member (subawardee, consultant) is providing SETA, A&AS, or similar support to any DARPA office(s) under: (a) a current award or subaward; or (b) a past award or subaward that ended within one calendar year prior to the proposal’s submission date.

If SETA, A&AS, or similar support is being or was provided to any DARPA office(s), the proposal must include:

The name of the DARPA office receiving the support;

The prime contract number;

Identification of proposed team member (subawardee, consultant) providing the support; and An OCI mitigation plan in accordance with FAR 9.5.

Government Procedures In accordance with FAR 9.503, 9.504 and 9.506, the Government will evaluate OCI mitigation plans to avoid, neutralize or mitigate potential OCI issues before award and to determine whether it is in the Government’s interest to grant a waiver. The Government will only evaluate OCI mitigation plans for proposals that are determined selectable under the BAA evaluation criteria and funding availability.

The Government may require proposers to provide additional information to assist the Government in evaluating the proposer’s OCI mitigation plan.

If the Government determines that a proposer failed to fully disclose an OCI; or failed to provide the affirmation of DARPA support as described above; or failed to reasonably provide additional information requested by the Government to assist in evaluating the proposer’s OCI mitigation plan, the Government may reject the proposal and withdraw it from consideration for award.

HR001119S0082 FASTNICS 20

C. Cost Sharing/Matching

Cost sharing is not required; however, it will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument (e.g., OTs under the authority of 10 U.S.C. § 2371).

D. Other Eligibility Requirements

1. Ability to Receive Awards in Multiple Technical Areas - Conflicts of Interest While proposers may submit proposals for all three Technical Areas, proposers selected for Technical Area 3 cannot be selected for any portion of the other two Technical Areas, whether as a prime, subcontractor, or in any other capacity from an organizational to individual level.

This is to avoid OCI situations between the Technical Areas and to ensure objective test and evaluation results. The decision as to which proposal to consider for award is at the discretion of the Government.

IV. Application and Submission Information

A. Address to Request Application Package

This document contains all information required to submit a response to this solicitation. No additional forms, kits, or other materials are needed except as referenced herein. No request for proposal (RFP) or additional solicitation regarding this opportunity will be issued, nor is additional information available except as provided at the Federal Business Opportunities website (https://www.fbo.gov) or referenced herein.

B. Content and Form of Application Submission

1. Proposals Proposals consist of Volume 1: Technical and Management Proposal (including mandatory Appendix A and optional Appendix B); Volume 2: Cost Proposal; the Level of Effort Summary by Task Excel spreadsheet; and the PowerPoint summary slide.

All pages shall be formatted for printing on 8-1/2 by 11-inch paper with 1-inch margins, single-line spacing, and font size no smaller than 12 point. Font sizes of 8 or 10 point may be used for figures, tables, and charts. Document files must be in .pdf, .odx, .doc, .docx, .xls, or .xlsx formats. Submissions must be written in English. All pages of Volume 1 should be numbered.

A summary slide of the proposed effort, in PowerPoint format, should be submitted with the proposal. A template slide is provided as an attachment to the BAA. Submit this PowerPoint file in addition to Volumes 1 and 2 of your full proposal, and the Level of Effort Summary by Task Excel spreadsheet. This summary slide does not count towards the total page count.

Reminder – Each proposal submitted in response to this BAA shall address only one TA.

Organizations may submit multiple proposals to any one TA, and they may propose to multiple TAs.

https://www.fbo.gov/

HR001119S0082 FASTNICS 21

Proposals not meeting the format prescribed herein may not be reviewed.

a. Volume 1: Technical and Management Proposal The maximum page count for Volume 1 is 40 pages, including all figures, tables, and charts but not including the cover sheet, table of contents or appendices. A submission letter is optional and is not included in the page count. Appendix A does not count against the page limit and is mandatory. Appendix B does not count against the page limit and is optional.

Additional information not explicitly called for here must not be submitted with the proposal, but may be included in the bibliography in Appendix B. Such materials will be considered for the reviewers’ convenience only and not evaluated as part of the proposal.

Volume 1 must include the following components:

i. Cover Sheet: Include the following information.

Label: “Proposal: Volume 1” BAA number (HR001119S0082) Technical Area Proposal title Lead organization (prime contractor) name Type of organization, selected from the following categories: Large Business, Small Disadvantaged Business, Other Small Business, HBCU, MI, Other Educational, or Other Nonprofit

Technical point of contact (POC) including name, mailing address, telephone number, and email address

Administrative POC including name, mailing address, telephone number, and email address

Award instrument requested: procurement contracts or OT.1 Total amount of the proposed effort Place(s) and period(s) of performance…