PD1676SMXG55701_Processor_-_15_Feb_2017.pdf

PD1676SMXG55701

CAGE 98748

15 February 2017

Purchase Description (PD) For

Electronic System Test Set (ESTS)

- Processor

1.1 SCOPE

This purchase description identifies the performance requirements for a stand-alone, embedded Processor that will be part of the Electronic System Test Set (ESTS) used to test the Unit Under Test (UUT). The Processor shall provide command and control functions in response to software programs to control the automatic test system which ultimately is used to functionally test and fault isolate the UUT. The Processor will be supplied with all the necessary items to perform command and control functions, such as the system hardware, interconnects, embedded software, licensing, and connecting components; and all technical data/licensing necessary to operate, maintain, repair and modify either the hardware or software.

1.2 Function

The Processor is a device that functions to provide command and control functions in response to software programs to control the automatic test system which ultimately is used to functionally test and fault isolate the UUT. Programs are loaded from external devices, inputs are accepted from the operator and/or attached devices; processing of commands and data occurs; and outputs are produced to the operator and/or devices to accomplish various test functions.

AMSC N/A

FSC 6685

Distribution Statement A Approved for public release; distribution is unlimited

INCH POUND

Comments, suggestions, or questions on this document should be addressed to: OC-ALC, 76SMXG, 557SMXS/MXDEB, Tinker AFB, OK 73145. Since contact information can change, you may want to verify the currency of this address information using the ASSIST Online database at www.dodssp.daps.mil.

http://www.dodssp.daps.mil/

2 APPLICABLE DOCUMENTS

The following documents, of the exact issues shown, form a part of this purchase description to the extent specified herein. The affectivity of specifications or documents cited within these documents shall be the issues in effect January 1975, unless otherwise specified.

Specifications

Military MIL-STD-461A, Notice 3, Electromagnetic Interference Characteristics, Requirements for

Category B-1 Equipment

MIL-STD-462 Electromagnetic Interference Characteristics, Measurement of

MIL-E-6051 Electromagnetic compatibility requirements, systems

MIL-HDBK-217F Reliability Prediction of Electronic Equipment

Mil-STD-810G Environmental Test Methods

Mil-STD-130N Identification Marking of U.S. Military Property

Mil-STD-143 Specifications and Standards: Orders of Precedence for the Selection of

Mil-STD-415 Test provisions for electronic systems and associates equipment, Design Criteria for

Mil-STD-1472 Human engineering design criteria for military system, equipment and Facilities

Mil-STD-955 Parts Control Program

MIL-STD-1686C Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment.

Commercial

IEEE Standard 488-1975 Standard Digital Interface for Programmable Instrumentation (IEEE-

488.1), ASCII

IEC 61010 Safety requirements for electrical equipment for measurement, control and laboratory use

Documents

02109-90014, Aug 1980 HP 1000 E-series reference manual 02109-90014.

3. BRAND NAME OR EQUAL SPECIFICATION

3.1. HP1000 E-Series Processor Requirements:

The Processor shall:

1. Be new and composed of the manufacturer's current production model. A current production model is defined as the manufacturer's current product, which on the date this document is issued, has been designed, engineered, sold, or is being offered for sale through advertisements or manufacturer's published catalogs or brochures. Products such as a prototype unit, pre-production model or an experimental unit do not qualify as meeting the requirements of this purchase description.

2. Include all components parts, software, firmware and functions necessary to meet the performance requirements specified herein.

3. Support execution of HP Real Time Executive (RTE) version -IVA Operating software.

4. Execute at a minimum all the same HP 1000 instruction sets as the HP 2113E as documented in the HP 1000 E-series reference manual 02109-90014.

5. Execute I/O drivers written for use with the RTE-IVA operating system.

6. Be capable of matching or exceeding the overall performance of the HP 1000 E-series with the option to adjust the overall execution rate of the processor equal to the rate of the original.

7. Be equipped with an Input/Output (I/O) backplane assembly that provides programmed I/O and

Direct Memory Access (DMA) to legacy E-series devices not otherwise emulated; and is fully compatible with HP E-series I/O circuit cards and can simultaneously support at least 10 mated cards.

8. I/O Card Cage: The Processor shall duplicate the rear panel location and configuration of the HP

2113E in form, fit and function in respect to the Input/Output card cage and interfacing. This is required to accommodate existing I/O interface cards that the Processor must control and operate.

9. Be equipped with sufficient forced air cooling to meet the ambient temperature/humidity operating requirements.

10. Support 3 MB/sec transmission speeds.

11. Communicate with terminals and other systems in the following ways:

a. With display terminals via an original HP 12966A Buffered Asynchronous Interface card.

b. With other subsystems via two original HP 12566C Microcircuit interface cards.

c. With HP-IB equipment using two original HP 59310B HP-IB interface cards.

d. With HP Disc subsystem using an original HP 13175B Disc Controller Interface card.

e. With HP peripherals using an original HP 12845B Line Printer Interface card.

f. By using an original HP 12539C Time Base Generator card.

12. Operate without error or degradation within the following conditions:

Ambient Temperature: Operating 50°F to 110°F, Storage -30°F to 150°F.

Relative Humidity 5 to 75 ±5 percent in the temperature range of 30 to 40 degrees Celsius, 5 to 45 ±5 percent in the temperature range above 40 degrees Celsius.

13. Not exceed the following dimensions: 12.25” high, by 19” wide, by 23” deep.

14. Not exceed 75 lbs total weight.

15. Meet or exceed an Operational Availability of 99% (see Note 1).

16. Not display any intermittent and/ or anomalous characteristics, or overheating for any extended period of not less than 120 hours of continuous operation.

17. Not require a battery to operate, nor to maintain data or settings.

18. Not utilize an internal operating system susceptible to file system corruption.

19. Be capable of immediate power removal at any time and shall be fully operational as defined by this document when power is reapplied.

20. Not be susceptible to damage by Electrostatic Discharge (ESD) as an assembled unit per MIL-

STD-1686C, (section 5.2, Human Body Model (HBM), hardening goal 4000V).

21. Be designed such that it will not be of any hazard to itself or to any person operating or maintaining it using reasonable precautionary procedures and in accordance with safety requirements of IEC 1010.

22. Be tested/certified from the manufacturer not to exceed the Emissions/Susceptibility limits shown in Table 1.

Characteristic tested

Band & Frequency Test Methods Limits Conducted Emissions

CE03

Broad and Narrow 20kHz- 50Mhz per

MIL-STD-462

MIL-STD-461A, Notice

3, Category B-1 Radiated Emissions

RE02

Broadband 14kHz-1Ghz Narrow Band 14kHz-10Ghz

Spike Conducted susceptibility CS06 see limits column entry MIL-STD-461A, Notice 3, Figure 19

Compatibility/Susceptibility Limits

Table 1

3.2. Electrical and Functional Characteristics of the Assembly.

The HP1000 E-Series Processor requires all of the following hardware components assembled and operating as a system to meet the following specifications and minimum requirements:

3.2.1. Power Supply:

Power Loss sustainment: sustains Processor over a line loss of up to 8 ms at minimum AC line voltage.

Input Power: fuse protected, 85 to 264 VAC, 60 Hz +/- 10%, Input Line transient protection: sustains +/- 500V, 50 µs pulse on power lines; +/- 1000V, 100 ns pulse on power lines.

Output Power: +5Vdc at 39A, +12Vdc at 2.5A, -12Vdc at 2.0A, +30Vdc and -2Vdc at 4.0A.

(voltages +/- 5%, protected from overvoltage and overcurrent conditions)

Output Signals: Rear panel PWR CONT OUT connector, Line Power Up (LPU) signal.

Required to monitor power up/down status of power supply.

3.2.2. Central Processing Unit (CPU):

Instructions Sets: At a minimum the processor shall duplicate the performance of the HP 2113E

E-series by execution on all instructions and combinations of the following instruction groups defined in the HP 1000 E-series reference manual 02109-90014:

Base Set

1. Memory Reference Instructions.

2. Register Reference Instructions.

3. Input/Ouput Instructions.

4. Extended Arithmetic Memory Reference Instructions.

5. Extended Arithmetic Register Reference Instructions.

6. Extended Instructions.

7. Floating point Instructions.

8. Alter-Skip Instructions:

9. Shift-Rotate Instructions:

Fast Fortran Instruction Set.

Dynamic Mapping Instructions Set.

Fast Fortran Processor Set.

RTE-IV Set.

CPU Architecture:

Address Space: 4,096 bytes (direct addressing)

65,536 bytes (indirect addressing)

2,097,152 bytes with Dynamic Mapping System (optional)

Word Size: 16 bits

Instruction Set: 128 standard instructions:

Memory Reference: 14

Register Reference: 43

Input/Output: 13

Extended Arithmetic: 10

Index: 32

Bit, Byte, Word Manipulation: 10

Floating Point: 6

Registers: 10

Accumulators: Two (A and B), 16 bits each. Explicitly addressable; also addressable as memory locations.

Index: Two (X and Y), 16 bits each.

Memory Control: Two (T and P), 16 bits each; one (M), 15 bits.

Supplementary: Two (Overflow and Extend), one bit each.

Display: One, 16 bits.

Special Registers: Four (m, t, f, s), m is 7 bits, 16 bits all others.

Register access: All registers can be selected for display or modification via the Front Control

Panel.

Control Processor architecture:

Address Space: 16,384 words (64 modules of 256 words each)

Word Size: 24 bits

Word Formats: Four

Word Fields: Five

Instruction Execution Time: Variable: 175 ns or 280 ns

Micro-Orders (Microinstructions): 211

Operations: 15

Special: 32

ALU and Conditional: 68

Store: 32

S-Bus: 32

Reverse Skip Sense: 32

Initial Binary Loaders: ROM resident; capacity of four 64-word programs callable from operator panel. Equipped with standard disc loader ROM 12992-80002 and Terminal Loader ROM 12992-80009.

Self-Test function: Automatic tests of CPU and memory operating condition. Executed on cold power-up and whenever operator panel IBL/TEST switch is pressed.

Power Fail provisions: When primary line power falls below a predetermined level while the

CPU is running, a power fail warning signal from the power supply causes an interrupt to memory location 00004. Memory location 00004 is intended to contain a Jump-to-subroutine (JSB) instruction to a power fail subroutine, such as that included in the RTE-IVA operating system.

A minimum of 500 microseconds is available to execute the power fail subroutine.

3.2.3. Direct Memory Access:

Equipped with Dual Channel Port Controller (DCPC) 12897-60004.

Number of Channels: Two

Word Size: 16 bits

Maximum Transfer Block Size: 32,768 words

I/O Assignable: Assignable to any two I/O channels; all logic necessary to facilitate bi-directional direct memory transfer to and from I/O is contained on

DCPC.

Transfer Rate: Equipped with HP 2102B Standard Performance Memory

Input w/ DMS: Min. 1.884 Mbytes/s, Max. 2.098 Mbytes/s

Output w/ DMS: Min. 1.626 Mbytes/s, Max. 1.782 Mbytes/s

DCPC Latency (Channel 1): Latency is defined as the time interval between the generation of a

Service Request (SRQ) signal by the I/O device through the intiation of a DCPC channel 1 cycle to the completion of the I/O data transfer to or from the I/O interface card. Subsequent consecutive cycles execute at a specified DCPC rate.

Input and Output Latency Times: Equipped with HP 2102B Standard Performance Memory

Input w/ DMS: Min. 2.84 µs, Max. 3.26 µs.

Output w/ DMS: Min. 3.57 µs, Max. 4.10 µs.

3.2.4. Memory System:

Equipped with two HP 12747-60002 128 K Byte (64K Word) Standard Performance Memory

Modules, and one HP 2102B Standard Performance Memory Controller.

Address Space: up to 2.048 Mbytes with Dynamic Mapping System (DMS).

Word Size: 16 bits plus parity bit

Configuration: Controller plus two 128 K Byte Memory Modules

Page Size: 2,048 bytes

System Cycle Times: READ w/ DMS: Min. 595 ns, Max. 700 ns

WRITE: Min. 595 ns, Max. 700 ns

REFRESH: Min. 595 ns, Max. 700 ns

Volatility Protection: Sustaining power for line loss of no less than 8 ms at the minimum AC line voltage.

Parity Error Detection: Monitors all words read from memory. Switch selectable for either halt or ignore interrupt error when detected. With memory protect or DMS, interrupt on parity error occurs.

3.2.5. Interrupt System:

Vectored Priority Interrupt structure with the priority assignments and select codes as defined in the HP 1000 E-series reference manual 02109-90014 for the 2113E.

3.2.6. Input/Output System

Interrupt Structure: Multilevel vectored priority interrupt; priority determined by interrupt location.

Standard I/O Channels: 14

Compatibility: Instruction set and program compatible with HP 1000 E-Series

Transfer Modes: Programmed or Dual Channel Port Controller

3.2.7. Memory Protection System:

1. Protects a selected block of memory of any size against alteration or entry by programmed instructions. A memory protect violation will interrupt the CPU and save the address of the violating instruction in a register on the memory card, from which it can be made accessible in the A or B register by a single Assembly language instruction.

2. Prohibits execution and generates an interrupt to location 00005 if one of the following instructions either directly or indirectly modifies or enters a location in protected memory, or if any I/O instruction is attempted (including HLT but excluding those I/O instructions addressing select code 01): DST, ISZ, JLY, JMP, JPY, JSB, MVB, MVW, SAX, SAY, SBX, SBY, STA, STB, STX, STY. This limits control of I/O and mapping operations to the operating system or other privileged programs.

3.2.8. Time Base Generator Interrupt: A time base generator interrupt is provided for maintaining a real-time clock. The interrupt request is made when the TBG logic signals, at 10-millisecond intervals, that its internal clock has rolled over.

3.3. Specific Configuration of the Assembly

Processor: a new, not remanufactured, or refurbished, form, fit, function product equal to a complete assembled Hewlett-Packard (HP) 2113E series computer with options 003 and 014 then configured with the following major components:

a. Model 12786B 256K Byte (128K Word) Standard Performance Memory Package, which consists of:

i. Model 2102B Memory Controller kit, with one Part Number (PN) 02102-

60001 Memory Controller circuit card and one PN: 02112-60016 or 12739-

60003 Memory Cable Assembly. Jumpers in “E” and “E-MEM” positions.

ii. Model 12747A 128K byte Standard Performance Memory Module, with two

PN: 12747-60001 128K byte Standard Performance Memory circuit cards; or the 12747H 128 K byte High Performance Memory Module, with two PN:

12747-60002 128K byte High Performance Memory circuit cards. Switch 1 open and 2 thru 4 closed on first module, Switches 1 thru 4 closed on second module.

iii. Model 12892B Memory Protect Module, with one PN: 12892-60003 Memory

Protect circuit card. Jumpers INT and JSB installed. No others.

iv. Model 12731A Memory Expansion Module, with one PN: 12731-60001 circuit card. Jumper W1 set to “B” position. Jumper W2 installed. Jumper

W3 not installed. Jumper W4 set to “A” position.

b. Model 12539C Time Base Generator, with one PN: 12539-60005 or PN: 12539-60006 Time

Base Generator circuit card. Jumpers W1 and W2 are set to “A” position.

c. Model 12897B Dual Channel Port Controller, with one PN: 12897-60004 Dual Channel Port

Controller circuit card. Jumper W1 set to “E” position. Equipped with PN: 12897-60002 cable assembly.

d. Model 13304A Firmware Accessory Board (FAB) Kit, with one PN: 5061-1339 Firmware

Accessory Board circuit card and one PN: 5061-1336 cable assembly, and the following

ROMs installed:

a. Model 13306B Fast Fortran Processor (FFP) Read-Only Memory (ROM) Set, which consists of:

i. PN: 5090-0589 FFP ROM #1, installed in FAB socket XU406-B4

ii. PN: 5090-0590 FFP ROM #2, installed in FAB socket XU408-B5

iii. PN: 5090-0591 FFP ROM #3, installed in FAB socket XU409-B6

b. Model 92067R RTE-IV EMA Firmware Set, which consists of:

i. PN: 92067-80001 EMA ROM #1, installed in FAB socket XU201-C1

ii. PN: 92067-80002 EMA ROM #2, installed in FAB socket XU202-C1

iii. PN: 92067-80003 EMA ROM #3, installed in FAB socket XU204-C1

c. Model 13037B Dynamic Mapping Instruction ROM Set, which consists of:

i. PN: 13307-80033 DMI ROM #1, installed in FAB socket XU401-B1

ii. PN: 13307-80034 DMI ROM #2, installed in FAB socket XU402-B2

iii. PN: 13307-80035 DMI ROM #3, installed in FAB socket XU404-B3

And the FAB circuit card switches and jumpers set as follows:

a. Jumpers 9A to 12A, 10B to 12B, 11C and 12C set to 0 position

b. Jumpers 10C, 10D to 12D, and 13 set to 1 position

e. PN: 5061-1400 Central Processing Unit (CPU) circuit card with the following ROMs installed:

a. Model 12992C Terminal Loader ROM PN: 1816-0857 or PN: 12992-80009 installed in Loader ROM socket 11.

b. Standard Disc Loader ROM PN: 5081-2361 or PN:12992-80002 installed in Loader

ROM socket 10.

c. Base Set/Extended Instruction Group (EIG)/Floating Point ROM Set, which consists of:

i. PN: 02113-80006 ROM #1, installed in CPU socket XU23

ii. PN: 02113-80007 ROM #2, installed in CPU socket XU43

iii. PN: 02113-80008 ROM #3, installed in CPU socket XU83

And the CPU circuit card switches and jumpers set as follows:

a. A1S1 switch set to INT/IGNORE (Left)

b. A1S2 switch set to ARS (left)

c. Remote Program Loader (RPL) S1 thru S8 set to the OPEN position

d. Jumper W3 set to the R15 position

e. Jumper U121 set to the 8K position

f. PN: 5061-1343 Front Control Panel circuit card. Equipped with cable assemblies PN:5061-

1364 and PN: 5061-1397.

g. PN: 02112-60002 Memory Backplane Assembly.

h. PN: 02112-60001 I/O Backplane Assembly.

i. PN: 5061-1388 Cross-over Board Assembly.

j. PN: 5061-6615 Power Supply Assembly. Equipped with cable assembly PN:5061-6612.

3.4. Technical Data Package (TDP):

The Processor shall be provided with a complete data package that accurately depicts the final product.

The TDP shall provide the necessary design, engineering, manufacturing, testing, and quality assurance requirements information necessary to enable the procurement or manufacture of an interchangeable item that duplicates the physical and performance characteristics of the original product, without additional design engineering effort or recourse to the original design activity.

Product data shall reflect the approved, tested, and accepted configuration of the defined delivered item. All engineering product definition data created as a result of this contract shall be considered a part of the TDP. This data includes, but is not limited to CAD data, models and model based definition data sets, and Gerber data. (DI-SESS-81000E, CDRL A001). The TDP shall include the following:

1. Software Data:

The contractor shall deliver all proprietary application software documentation and associated software documentation in the latest version for software delivered under paragraph 3.5. Software documentation shall include: build guides and instructions for all actions necessary to modify and build the complete Processor software package that is delivered, detailed data such as software title, file names, build numbers, versions, and revisions, configuration numbers and any included special options included as part of the individual software packages. In the instance another contract modifies any of the software documentation, the updated version(s) shall be submitted to the Government.

2. Technical Manual:

The contractor shall deliver a technical manual (user and service manual) that includes sections fully describing the following categories: Safety, General Information; Preparation For Use, Storage, and Shipment; Manual Operation; Remote Operation Inspection, Performance

Verification, Maintenance and Trouble Analysis to the component level; Repair Instructions;

Alignment; Illustrated Parts Breakdown. Mandatory method of supplying manual is electronically on CD/DVD-ROM in Indexed Portable Document Format (iPDF). The manuals shall comply with

Data Item Description (DID) TM 86-01N, Technical Manual Contractual Requirement, CDRL

A002.

3.4.1 Supplemental requirements. The following are supplemental requirements for the TDP.

Indentured data lists. TDP indentured data list, (excludes nationally recognized military and industry specifications and standards). This list shall include:

(a) a sequence of both part numbers and associated drawing numbers comprising the end item in a lateral and descending family tree/top down breakdown

(b) a top down breakdown of the end item including all lower level items, listing every assembly, subassembly and part;

(c) every item listed in its relationship to the end item, subassembly, assembly or system of which it is a part

(d) a relationship as shown by means of physical indenture or numeric sequence, with the indenture indicating that the item is a part of the preceding item

Circuit Card Assemblies (CCA) Drawings. CCA drawings shall include specific input and output requirements, design specifications and acceptance test requirements.

3.5. Software:

1. Software:

The contractor shall deliver all application and operating executable software required to operate and provide maintenace support for the Processor. The contractor shall also recommend the required software necessary to rehost the delivered contractor-developed application software from the delivered specific variant of the Microsoft Windows® Operating System to an Open-Source software Operating System such as SE Linux. The contractor shall provide all hardware/software necessary to operate and support a software maintenance laboratory, containing the minimum amount of equipment to produce code, test, and integrate the rehost software at the subsystem and system level. This shall include, but is not limited to, any applicable Computer-Aided Software

Engineering tools, data in these tools, compilers, test tools, test data, simulations, emulations, utilities, configuration management tools, databases and data files. The contractor shall provide the Government determined software data in accordance with CDRL A003.

2. Source Code:

The contractor shall deliver all Processor application source code and driver source code in the latest version. The source code shall be in the native format used by the development environment with all associated modified or non-standard libraries and modules; and in human-readable format.

The contractor shall provide all associated tools required to read or view source code that are not readily available for commercial purchase or through open source. The contractor shall provide the

Government determined source data in accordance with CDRL A003.

3.6. Data Rights and Licensing:

The Government shall have Unlimited Rights to all technical data and computer software provided or produced under this contract.

License(s) for software installed into the Processor and/or required for Processor maintenance and/or alignment shall be provided and valid for the life of the equipment and included in the Processor purchase price.

TDP OPTION SELECTION WORKSHEET

SYSTEM: Processor

A. CONTRACT NO.

B. EXHIBIT/ATTACHMENT

NO. A

C. CLIN

D. CDRL DATA ITEM NO.

1. TDP Level (X and complete as applicable.)

A. CONCEPTUAL LEVEL

DEVELOPMENTAL LEVEL

PRODUCTION LEVEL

B. REMARKS:

2. TYPE AND FORMAT (X all that apply and complete as applicable)

A.

TYPE 2D: 2D DRAWINGS

TYPE 3D: 3D MODEL ONLY

TYPE 3D: 3D MODELS WITH

ASSOCIATED 2D DRAWINGS

B.

NATIVE CAD (SPECIFY TYPE) ______________________________

ISO 10303 STEP FORMAT (Specify STEP PROTOCOL AP203, AP 214 etc.)

ISO32000 PORTABLE DOCUMENT FORMAT: ISO 32000-1:2008

OTHER ELECTRONIC FORMAT (SPECIFY TYPE)

HARDCOPY: SUPPORT for TECH REVIEWS AND TECHEVAL

REMARKS: ________________________________________________________

3. CAGE Code AND DOCUMENT

NUMBERS

A. CONTRACTOR CAGE AND DOCUMENT NUMBERS

GOVERNMENT CAGE (COMPLETE 3B & 3C OR 3D)

D. To Be Assigned By:

B. USE CAGE CODE: C. USE DOCUMENT NUMBERS:

4. DRAWING FORMATS (X one and complete as applicable)

CONTRACTOR FORMAT.

GOVERNMENT FORMAT.

REMARKS: _________________________________________________________________________________________

5. TDP ELEMENTS REQUIRED (X all that apply)

ELEMENTS REQUIRED TO BE DETERMINED BY CONTRACTOR-OR THE FOLLOWING ARE REQUIRED:

CONCEPTUAL DRAWINGS/MODELS AND ASSOCIATED LISTS

DEVELOPMENTAL DESIGN DRAWINGS/MODELS AND ASSOCIATED LISTS

PRODUCT DRAWINGS/MODELS AND ASSOCIATED LIST

COMMERCIAL DRAWINGS/MODELS AND ASSOCIATED LIST

QUALITY ASSURANCE PROVISIONS

SPECIAL INSPECTION EQUIPMENT (SIE) DRAWINGS/MODELS AND ASSOCIATED LISTS

SPECIFICATIONS

SOFTWARE DOCUMENTATION

SPECIAL PACKAGING INSTRUCTIONS (SPI) DRAWINGS/MODELS AND ASSOCIATED LIST

6. ASSOCIATED LISTS (X and complete as applicable)

A. PARTS LIST (X ONE) (1) INTEGRAL (2) SEPARATE

B. DATA LIST (X ONE) (1) NOT REQUIRED (2) REQUIRED (SPECIFY LEVELS OF ASSEMBLY)

C. INDEX LIST (X ONE) (1) NOT REQUIRED (2) REQUIRED (SPECIFY LEVELS OF ASSEMBLY)

D. WIRINGLIST (X ONE) (1) NOT REQUIRED (2) REQUIRED (SPECIFY LEVELS OF ASSEMBLY)

E. INDENTURE DATA LIST (X ONE) (1) NOT REQUIRED (2) REQUIRED (SPECIFY LEVELS OF ASSEMBLY)

F. APPLICATION LISTS (X ONE) (1) NOT REQUIRED (2) REQUIRED (SPECIFY LEVELS OF ASSEMBLY)

7. APPLICABILITY OF STANDARDS. The following Standards apply: (X as applicable)

ASME Y14.100

ENGINEERING DRAWING

PRACTICES WITH

APPENDICES

B C D E

ASME Y14.24 TYPES AND APPLICATIONS OF

ENGINEERING DRAWINGS

ASME Y14.34 ASSOCIATED LIST

ASME Y14.35 REVISION OF ENGINEERING DRAWINGS

AND ASSOCIATED LIST

ASME Y14.41 DIGITAL PRODUCT DATA PRACTICES

ASME Y14.5 DIMENSIONING AND TOLERANCES

OTHER STANDARDS APPLY AS

DESCRIBED:

COMPANY STANDARDS

PERMITTED: YES NO

8. OTHER TAILORING

Block 6 When individual detail piece parts are assembled as an inseparable assembly, those details may be shown on a multi-detail drawing, provided that none of the detail parts will be provisioned as spare or repair parts.

4 QUALITY ASSURANCE PROVISIONS

4.1 CONTRACTOR CERTIFICATION

The manufacturer shall identify to the procuring office the part number and configuration of the equipment to be delivered. The manufacturer shall certify, maintain and provide substantiating evidence that the product offered meets the requirement of this document and that the product conforms to the manufacturer’s own drawings, specifications, workmanships standards and quality assurance practices.

4.2 GOVERNMENT VERIFICATION

The government reserves the right to require proof that the Processor meets the requirements of this document prior to the delivery of the first unit and thereafter as may be required. The government shall be provided access to all drawings, reports, procedures, and facilities as may be required to ensure that the product offered will perform as specified. The government reserves the right to test the units for conformance to the specified requirements after delivery.

4.3 FIRST ARTICLE TESTS

4.3.1 EXAMINATION AND CONFORMANCE TESTS

A sample unit shall be provided for First Article Test (FAT) as specified in FAR 9.308-2 (Testing performed by the Government). As specified in FAR 52.209-4, (First Article Approval—Government

Testing) FAT approval is contingent on successful completion of both contractor in-plant testing and follow-on government testing. Contractor is responsible for shipping the FAT unit to the government test facility as specified in the contract order. In case of failed government FAT, the contractor is responsible for shipping the unit to/from the In-plant facility for retest. On disapproved First Article, the contractor will be given 30 days to correct failure and resubmit for testing within the government.

Contractor In-plant Testing

The contractor is responsible for performing all inspections and quality checks at the point of fabrication, or as necessary, to ensure performance, as specified herein. In addition to all elements of this purchase description, all commercially available components provided with this system must, as a minimum, satisfy their commercially published performance specifications. A report containing all results, test data, details and supporting evidence that demonstrates the First Article's design and performance is as specified herein, shall be provided.

Follow-on Government Testing The Processor shall be examined and tested by representatives of the procuring activity to determine conformance with the requirements of this purchase description. This item will be verified with test equipment having parameters equal to or better than those required to assure specified performance requirements are met. Test equipment used is traceable to the National Institute of Standards and

Technology and/or United States approved National Metrology Institute when/where required. Tests will be performed to assure the item meets the requirements of this purchase description. Physical, electrical, command & control Integration with the designated ATE will be verified. The contractor is invited to witness government testing at their own expense.

5 WARRANTY

The Processor shall be warranted against defects in material and workmanship for a period of at least three years from date of shipment. During the warranty period, the contractor will, at its option, either repair or replace components which prove to be defective.

6 PREPARATION FOR DELIVERY

6.1 Preservation, Packing and Marking

Preservation, packing and marking shall be as specified in MIL-STD-2073-1E with the following applicable codes:

Preservation Method: 32

Cleaning Procedure: 1

Wrapping Material: K3

Cushioning and Donnage: NB

Thickness of Cushioning or dunnage: H

Unit & Intermediate container: 10

Military Packing Requirements: A

Minimal Packaging Requirements: L

Special Marking: 01, 06, 28

NOTES

NOTE 1: Operational Availability (OA). OA covers all time that the equipment is intended to be operational, a combination of up time and down time. Up time includes operating time and standby time. Down time includes active time, which is comprised of total unscheduled down time and total preventative maintenance time. The second component of down time is delay time. This includes administrative and logistics lead time.