DSP_Software Developement DRAFT SOW.pdf
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- ELECTRONIC SUPPORT MEASURES (ESM) DIGITAL SIGNAL PROCESSING (DSP) and SOFTWARE DEVELOPMENT SERVICES
- Solicitation number
- N0017325SSNDH02
About this file
This document is a Draft Statement of Work (SOW) for Electronic Support Measures (ESM) Digital Signal Processing (DSP) and Software Development Services for the Naval Research Laboratory (NRL). The SOW requires a contractor to provide qualified personnel to perform research in five key areas: RF Analog-to-Digital Conversion Hardware Integration, Digital Signal Processing Software Development, Electronic Support Software Development, Software Validation and Verification, and Configuration Management and Control.
The contract involves advanced research and development of passive electronic warfare systems, with specific tasks including developing DSP software techniques for FPGA hardware, creating electronic support software for identifying and locating threat emitters, implementing graphical user interfaces, conducting software testing, and managing configuration controls. The work will primarily be performed at NRL in Washington, D.C., other government facilities, and contractor locations. All full-time on-site contractor personnel must possess security clearances up to Secret or Top Secret/SCI. This is currently a Sources Sought Notice (SSN) with NAICS code 541715, seeking to determine the availability of qualified contractors capable of meeting the draft SOW specifications.
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STATEMENT OF WORK FOR
ELECTRONIC SUPPORT MEASURES (ESM)
DIGITAL SIGNAL PROCESSING (DSP) and SOFTWARE DEVELOPMENT SERVICES
Naval Research Laboratory
4555 Overlook Ave., SW Washington, DC 20375
1.0 Introduction
The Electronic Warfare Support Measures (ESM) Branch at the Naval Research Laboratory (NRL) is engaged in the research and development (R&D) of advanced passive electronic warfare systems. ESM branch employees conduct R&D, prototype design, and operational testing of ESM systems/subsystems associated with all disciplines of modern ESM systems. Research activity areas include:
o Digital Receiver Design and Implementation o Advanced Digital Signal Processing (DSP) o Precision Direction Finding (PDF) Techniques o Precision Passive Geolocation Techniques o Miniaturized Electronic Support (ES) Payloads for Unmanned Platforms o RF Design (Board and System Level) o RF ASIC Design o
The ESM Branch at NRL has a long history of directly supporting the warfighter through a combination of long term system developments as well as the delivery of quick reaction capabilities (QRC). The ESM
Branch also provides support to the Intelligence Community, particularly in the area of special signal collection.
1.1 Mission
NRL ESM Branch scientists aim to make both immediate and long-range contributions to the advancement of Navy EW programs. These R&D programs apply state-of-the-art techniques and system concepts to optimally achieve program objectives. These development efforts encompass all related phases of engineering including applied research of emerging techniques and components, conceptual design and analysis, detailed hardware/software design, modeling and simulation, and prototype development.
1.2 Background
Utilizing a proprietary development environment from Annapolis Micro Systems, Inc., called COREFIRE, the NRL ESM Branch has rapidly prototyped DSP algorithms for EW applications. Over the course of many years, NRL has developed functional code libraries that permit rapid reuse of tried and tested techniques within the COREFIRE design environment.
NRL has successfully built and deployed over 15 systems utilizing the COREFIRE rapid implementation process. Annapolis Micro Systems maintains and continually updates products and support for the
COREFIRE environment, permitting NRL immediate access to emerging and cutting edge technologies.
The coupling of software, hardware, and streamlined/dedicated support make COREFIRE and Annapolis
Micro Systems the development platform of choice for NRL rapid prototyping.
2.0 Scope
The Contractor shall provide qualified personnel to perform research for the ESM Branch in the following areas:
o RF Analog-to-Digital Conversion (ADC) Hardware Integration o Digital Signal Processing (DSP) Software Development o Electronic Support (ES) Software Development o Software Validation and Verification o Configuration Management and Control
DSP is concerned with the practical aspects of representing information bearing signals in digital form, and with using computers or special purpose digital hardware to extract that information (amplitude, RF, BW, PW, FM, and AM) or to transform the signals in useful ways.
Efforts in support of the tasks delineated in Section 3 SOW Tasks, below will be conducted in coordination with Principal Investigator (PI) led research teams that may include Government scientists and other
Contractors. In the performance of some of the tasks listed in Section 3, Contractor personnel may occasionally travel to support system installation, maintenance, or testing aboard Navy platforms.
Government assessment of the quality and timeliness of the provider's contribution to the work will be evaluated in terms of its impact on the success of the overall project.
3.0 SOW TASKS
The following section specifies the Performance Objectives and Performance Elements for the contract.
DSP applications are ever changing and commercial-off-the-shelf (COTS) products that have proven performance will be used to satisfy these requirements when applicable and within budgetary constraints.
3.1 Radio Frequency (RF) Analog-to-Digital (ADC) Hardware Integration
The Contractor shall conduct research and development to integrate high-speed Analog-to-Digital Converter
(ADC) boards with state-of-the art DSP boards for extraction of RF emitter characteristics from a dense analog RF signal environment.
Data transfer rates under study exceed 100 Gbps and may be implemented in numerous bus technologies including RACEway, PCI, Compact-PCI, PCIExpress, PXI. VME, VXI, VPX, and other state-of-the art serial electronic or optical bus technologies. DSP processor boards under investigation include Annapolis
Micro System's Wildstar platform as well as other COTS products with similar performance.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems or issues encountered
c) STD: Timely
AQL: 60 days after the end of an annual period of performance
d) STD: Comprehensive
AQL: Addresses key issues associated with integrating high-speed ADC boards to state-of-the DSP boards.
Deliverables
A001 Monthly Progress and Status Report - STDs a, b
A002 Contractor Summary Technical Report – STDs c, d
3.1.1 The Contractor shall use VHDL and Verilog programming environments to program firmware for implementing ADC to DSP board hardware interfaces.
Performance Standards
a) STD: Timely
AQL: 30 days after completion of verification and validation of firmware source code
b) STD: Comprehensive
AQL: Meets 100% of the requirements listed in the VDD Guide data description provided in the DD1423
Contract Requirements Data List (CDRL) attached.
Deliverables
A003 Version Description Document
3.2 Digital Signal Processing (DSP) Software Development
The Contractor shall conduct research and development to implement DSP software techniques in state-of-the-art FPGA hardware for identifying specific emitter characteristics in a high-density RF signal environment.
Techniques to be implemented include Fast Fourier Transforms (FFTs), convolution, digital filters, number system conversions, vector algebra, trigonometry, and other more esoteric, mathematically based algorithms that take advantage of the increased throughput of the integrated FPGA based DSP boards. Emitter characteristics to be determined include technical parameters of the emitter signal (e.g. Pulse Width, PRF, PRI, Frequency, Modulation Type, Scan Rate, Antenna Beam Width, etc.) as well as positional or geo-location parameters (e.g. angle of arrival, line of bearing, depression angle, etc.).
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems
c) STD: Timely
AQL: 30 days after completion of verification and validation of a specific algorithm source code
d) STD: Comprehensive
AQL: Addresses key issues associated with developing and implementing a specific DSP software technique/algorithm in state-of-the art FPGAs.
Deliverables
A001 Monthly Progress and Status Report – STD’s a, b
A005 Technical Studies Reports – STD’s c, d
3.2.1 The Contractor shall use Annapolis Micro System's COREFIRE software development environment to develop and optimize FPGA based DSP algorithms for use with Annapolis Micro System's Wildstar hardware platform.
Performance Standards
a) STD: Timely
AQL: 30 days after completion of verification and validation of a specific algorithm source code
b) STD: Comprehensive
AQL: Meets 100% of the requirements listed in the VDD Guide data description provided in the DD1423
Contract Requirements Data List (CDRL) attached.
Deliverables
A003 Version Description Document
3.3 Electronic Support (ES) Software Development
The Contractor shall provide electronic support involving actions taken to search for, intercept, identify and locate radiated electromagnetic energy for the purpose of immediate threat recognition. It provides a source of information required for immediate decisions involving electronic countermeasures (ECM), electronic countercountermeasures (ECCM) and other tactical actions such as avoidance, targeting and homing.
Some initial algorithm development under this task may be accomplished using test code developed on a desktop workstation or on any of several commercially available mathematical packages such as The
Mathworks product, MatLab. Integration of third party mathematics packages may be required as part of this task.
In addition to advanced algorithm development for automatic analysis techniques and real-time process control, this task includes development of custom software to be used for engineering development integration and test purposes but not necessarily delivered in production versions of these EW systems.
3.3.1 The Contractor shall develop electronic support software to perform automated processing and analysis of emitter data provided by state-of-the-art DSP boards for assisting shipboard operators in identifying and locating threat emitters.
The current and projected emitter environment requires emphasis on advanced EW support systems that can simultaneously detect and process a large number of emitters. State-of-the-art DSP boards being developed for the Shipboard Electronic Warfare Improvement Program (SEWIP) provide a significant upgrade in the amount of emitter data that can be obtained from the threat environment and, hence, requires new capabilities in the electronic support software to handle the increased throughput.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems or issues encountered
c) STD: Timely
AQL: 60 days after the end of an annual period of performance
d) STD: Comprehensive
AQL: Addresses key issues associated with processing and analysis of increased volume of emitter data provided by state-of-the-art DSP boards.
A001 Monthly Progress and Status Report – STD’s a, b
A002 Contractor Summary Technical Report – STD’s a, b
3.3.2 The Contractor shall develop and integrate GUI software to provide real-time, interactive process control, and display of threat emitter data for review, analysis, and response by a EW system operator.
In addition to the automated functions of identifying and locating threat emitters, electronic support software provides a Graphical User Interface (GUI) to display emitter data and allow operator interaction with processing routines to assist an operator to make decisions on how and when to respond to threats.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems
c) STD: Timely
AQL: 60 days after the completion of a specific system integration effort.
d) STD: Comprehensive
AQL: Fully describes architecture and implementation of integration of subject Graphical User Interface
(GUI) to front-end electronics support hardware and software.
A006 Software Design Description – STD’s c, d
3.4 Software Subsystem and System Testing
In specifying this task the following definitions will be used:
Validation: The process of evaluating software to determine whether the systems and subsystems satisfy the conditions imposed by the government or research sponsor i.e. does it perform as required in its operational environment.
Verification: The process of evaluating software to determine whether it satisfies the specified requirements i.e. was it built correctly.
3.4.1 The Contractor shall conduct software tests to validate that software subsystems and systems meet their software specifications in the environment for which the systems/subsystems were designed to operate.
Testing in the operational environment requires contractor personnel to travel to NRL offsite locations with the NRL developers of the systems/subsystems. Test documentation forms will be provided by the government or research sponsors of the specific systems/subsystems under test.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems or issues encountered
c) STD: Timely
AQL: 30 days after completion of a specific test
d) STD: Identify test engineer conducting the test
e) STD: Identify requirement to be satisfied
f) STD: Identify the module(s) that satisfy the requirement
g) STD: Identify any discrepancies
h) STD: Timely
AQL: 5 days after completion of test
i) STD: Comprehensive
AQL: Provides all information needed to describe software discrepancies, if they occur during field testing.
A007 Software Test Report – STD’s c, d, e, f, g
A008 Software Discrepancy Report – STD’s h, i
3.4.2 The Contractor shall coordinate with NRL developers in developing software modifications to systems and subsystems for resolving software discrepancy reports (SDRs) resulting from field testing.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems or issues encountered
c) STD: Timely
AQL: 30 days after completion of verification and validation software fix
d) STD: Completeness
AQL: Meets 100% of the requirements listed in the VDD Guide data description provided in the DD1423
Contract Requirements Data List (CDRL) attached.
Deliverables
A001 Monthly Progress and Status Report – STD’s a, b
A003 Version Description Document – STD’s c, d
3.4.3 The Contractor shall develop automated test software for verifying that delivered software baselines perform as specified.
It is intended that the test software developed under this task (once validated) be maintained with the relevant software baseline in the CMS described in task 3.5.1 below.
Performance Standards
a) STD: Timely
AQL: 5 days after last day of month in which work was accomplished
b) STD: Comprehensive
AQL: Include: hours expended on tasks, resources assigned to tasks, meeting/reviews attended, problems or issues encountered
c) STD: Automatically generates a Verification Report
d) STD: Identifies the System/Subsystem being verified
e) STD: Identifies baseline specification requirements satisfied
f) STD: Identifies any errors
g) STD: Timely
AQL: 30 days after completion of verification and validation automatic test software
h) STD: Completeness
AQL: Meets 100% of the requirements listed in the VDD Guide data description provided in the DD1423
Contract Requirements Data List (CDRL) attached.
A003 Version Description Document – STD – g, h
A004 Verification Report – STD’s c, d, e, f
3.5 Configuration Management and Control
3.5.1 The Contractor shall use a Government provided automated configuration management system (CMS) to document new and current software baselines and modifications thereto for all firmware and software development and testing tasks.
The CMS provides a repository of all current software baselines, new software developments, baseline upgrades, maintenance patches, test results, Software Discrepancy Report (SDR) fixes, and generates automated reports necessary to document the results of all configuration management and control efforts.
Performance Standards
a) STD: Timely
AQL: Agreed upon timeline determined by the COR
b) STD: Baseline all new developed software
c) STD: Release software baseline upgrades
d) STD: Release maintenance patches e.g. when change does not required baseline update
e) STD: Release SDR fixes
A001 Monthly Progress and Status Report
4.0 Deliverables
The Contractor shall provide deliverables with the schedule and format as described in section 3.0 and outlined in the CDRL's listed below.
Identifier Name
A001 Monthly Progress and Status Report
A002 Contractor Summary Technical Report
A003 Version Description Document
A004 Verification Report
A005 Technical Studies Reports
A006 Software Design Description
A007 Software Test Report
A008 Software Discrepancy Report
5.0 Place of Performance
It is anticipated that work will be performed at the following locations:
o NRL (Washington, D.C) o Other Government facilities o Contractor facilities
6.0 Security
All full-time on-site contractor personnel shall possess clearances up to Secret or Top Secret/SCI, and be eligible for immediate adjudication by appropriate cognizant security authority upon the date of task order award.
Individuals with Interim-Secret security clearances will only carry out unclassified work. This includes: scoping studies, theoretical calculations and simulations, general estimates, and experimental measurements and analysis, where all the materials involved are unclassified and the results of the work is also unclassified. The general topic areas for this work include electromagnetic wave energy propagation and measurement, detection instrumentation and design, detector and antenna design, data acquisition instrumentation, and RF detection design and instrumentation.
Individuals with Interim Secret will be permitted to work in Building 210.
Interim-Secret security clearances are allowed on a temporary basis for new-hires with written approval by the relevant program sponsor(s) and NRL Code 1200. Contractors issued a DoD Interim-Secret security clearance may only work on specific projects covered by SOW Sections 3. Unclassified IA or IT positions are NOT authorized with a DoD issued Interim-Secret clearance. Contractors with an Interim-Secret clearance shall be escorted at all times in classified spaces.
Contractors with an Interim-Secret security clearance are prohibited from having any access to the following types of classified information:
o Communications Security (COMSEC) o Special Compartmented Information (SCI) o Special Access Program (SAP) Information o North Atlantic Treaty Organization (NATO) Information o Critical Nuclear Weapons Design Information (CNWDI) o Restricted Data (RD) (and Formerly Restricted Data) o Naval-Nuclear Propulsion Information (NNPI) o Foreign Government Information (FGI)
The Contractor shall ensure that all classified material is handled in accordance with the National Security Program
Operating Manual (NISPOM) (DoD 5220.22M) and applicable Security Program Guides/Directives.
7.0 Travel
TBD
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