CHIPS NAPMP NOFO 2_for publish.pdf

U.S. Department of Commerce, NIST, National Advanced Packaging Manufacturing Program (NAPMP) Advanced Packaging Research and Development (R&D)

2025-NIST-CHIPS-NAPMP-01

Funding Opportunity Description:

Applications such as high performance computing and low-power electronics, both needed for artificial intelligence (AI), require leap-ahead advances in semiconductor advanced packaging. This Notice of Funding Opportunity (NOFO) seeks proposals for R&D activities that will establish and accelerate domestic semiconductor advanced packaging through investments in five (5) R&D Areas: (1) Equipment, Tools, Processes, and Process Integration; (2) Power Delivery and Thermal Management; (3) Connector Technology, including Photonics and Radio Frequency (RF); (4) Chiplets Ecosystem;

and (5) Co-design/Electronic Design Automation (EDA).

Announcement Type: Initial Funding Instrument: Other transaction agreements (OTs), as authorized by 15 U.S.C.

§ 4659(a)(1).

Assistance Listing (CFDA Number):

11.042 – CHIPS R&D

Award Project Period: Five (5) years Goals & Objectives: The NAPMP seeks to drive U.S. leadership in advanced packaging and provide the technology and skilled workforce needed for packaging manufacturing in the United States.

Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, domestic advanced packaging industry where advanced-node chips manufactured in the United States and abroad can be packaged in appropriate volumes within the United States and innovative designs and architectures are enabled through leading-edge packaging capabilities. In combination with other CHIPS for America education and workforce efforts, NAPMP-funded activities will produce the diverse and capable workforce needed for the success of the domestic packaging sector.

The objective of this NOFO is to enable, through R&D, innovative new advanced packaging flows suitable for adoption by U.S. industry.

Eligible Projects: This NOFO envisions projects in five (5) R&D Areas: (1) Equipment, Tools, Processes, and Process Integration; (2) Power Delivery and Thermal Management; (3) Connector Technology, including Photonics and RF; (4) Chiplets Ecosystem; and (5) Co-design/EDA.

Eligible Applicants: Eligible applicants are domestic non-profit organizations;

domestic accredited institutions of higher education; State, local, and Tribal governments; and domestic for-profit organizations. A domestic entity is one that is incorporated within the United States (including a U.S. territory) with its principal place of business in the United States (including a U.S.

territory).

Funding Amount: CHIPS R&D anticipates making available up to approximately $1,550,000,000 for funding multiple awards of varying size and scope, with anticipated amounts ranging from approximately $10,000,000 to approximately $150,000,000 in Federal funds per award over a five (5) year period of performance.

Anticipated total funding and approximate maximum award sizes per R&D Area are as follows:

R&D Area Total Funding

Anticipated Maximum

Award Equipment, Tools, Processes, and Process Integration

$450M $150M

Power Delivery and Thermal Management $250M $50M

Connector Technology, Including Photonics and Radio Frequency (RF)

$250M $100M

Chiplets Ecosystem $300M $75M Co-design/Electronic Design Automation (EDA) $250M $100M

CHIPS R&D anticipates reserving up to $50,000,000 to support recipients under this NOFO pursuing prototyping activities, to be awarded once the NAPMP National Advanced Packaging Piloting Facility (NAPPF) has established a baseline capability.

Prototypes will focus on application areas such as high-performance computing and low-power systems needed for AI.

Funding for prototyping activities will be executed as add-on projects to existing awards based on information that will be requested by CHIPS R&D at a later date.

Cost Share/Matching Requirements:

A non-Federal cost share over the lifetime of an award is strongly encouraged but not required. CHIPS R&D will give preference to proposals that demonstrate committed cost share in their Concept Paper and Full Application Project Narrative, Budget Narrative and Justification. The non-Federal cost share is that portion of the project costs not borne by the Federal government. Cost share may include cash, services, and third-party in-kind contributions, as described at 2 C.F.R. § 200.306.

Applicants may propose other types of cost share, provided that the proposed cost share is necessary and reasonable for accomplishment of the project objectives and approved by

NIST.

Estimated Number and Type of Award(s):

Multiple awards for projects varying in scope and funding amount are expected under this NOFO.

How to Apply: The submission of a concept paper is required. Eligible applicants may submit only one concept paper per R&D Area.

Each concept paper may only include one R&D Area.

Applicants may submit separate concept papers on different R&D Areas. Following concept paper evaluation, CHIPS R&D will invite and accept full applications from selected applicants only.

Applicants must submit concept papers and full applications through Grants.gov. Paper or emailed submissions will not be accepted. Applicants should be aware and factor into their submission planning that the Grants.gov system closes periodically for routine maintenance. Applicants should visit Grants.gov for information on any scheduled closures. Please note that an active registration in the System for Award Management (SAM) is required to submit concept paper and full application materials through Grants.gov. CHIPS R&D encourages prospective applicants and subrecipients to begin the process of registering in SAM.gov as early as possible.

Relevant Events and Dates

Concept papers must be received no later than 11:59 p.m.

Eastern Time, December 20, 2024, 60 days after publication.

Full applications will be due 60 days from the date of invitation.

Concept papers and full applications received after the specified deadlines will not be reviewed or considered.

Prior to the relevant concept paper and full application deadlines and within two weeks from the date of this announcement, CHIPS R&D plans to host a Proposers Day to promote awareness of the funding opportunity and provide a

Advanced Packaging R&D NOFO Key Dates Proposers Day(s) October 22, 2024

Concept Papers Due December 20, 2024, 60 days after publication

Invited Full Applications Due

Full applications will be due 60 days from the date of the invitation to submit.

https://www.sam.gov/ https://www.sam.gov/ forum for organizations to identify prospective partners. After Proposers Day, CHIPS R&D will post a series of recorded webinars with more detail on the R&D Areas in this announcement. Questions about the funding opportunity, eligibility requirements, evaluation and award criteria, selection process, and the general characteristics of a competitive application will be addressed at Proposers Day and by e-mail for inquiries sent to research@chips.gov with “2025-NIST- CHIPS-NAPMP-01 Questions” in the subject line. Proposers Day participants must register in advance at National Advanced Packaging Manufacturing Program (NAPMP) Proposers Day (nist.gov). There is no cost to attend the informational webinars, but participants must register in advance at National Advanced Packaging Manufacturing Program (NAPMP) Proposers Day (nist.gov). Participation in Proposers Day and/or the informational webinars is not required and will not be considered in the review and selection process. Information about these events can be found on the CHIPS for America Webinars website.

Review and Selection Process:

The CHIPS R&D merit review process will assess both concept papers and full applications against the following five criteria:

(1) relevance to economic and national security; (2) overall scientific and technical merit; (3) project management, resources, and budget; (4) transition and impact strategy; and

(5) education and workforce development. The evaluation will be qualitative, not numerical. Following the merit review, an evaluation panel consisting of CHIPS R&D staff and/or other Federal employees with the appropriate expertise will conduct a panel review of the rated applications. The Selecting Official, the NIST Director or designee, will make final award recommendations to the NIST Agreements Officer.

Agency Contacts: Programmatic and Technical Questions:

E-mail: research@chips.gov with “2025-NIST-CHIPS- NAPMP-01 Questions” in the subject line

Award Rules and Regulations:

Lisa Ko E-mail: NOFO@nist.gov with “2025-NIST-CHIPS-NAPMP-01 Questions” in the subject line

CHIPS R&D also maintains a public website that includes a Frequently Asked Questions page and other information pertaining to this funding opportunity.

Additional Information: The U.S. Department of Commerce may amend this NOFO at any time. It may also close the funding opportunity with at least mailto:research@chips.gov https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://events.nist.gov/profile/web/index.cfm?PKwebID=0x9425abcd https://www.nist.gov/chips/chips-america-webinars https://www.nist.gov/chips/chips-america-webinars mailto:research@chips.gov mailto:NOFO@nist.gov https://www.nist.gov/chips/chips-RD-funding-opportunities https://www.nist.gov/chips/research-development-programs/national-advanced-packaging-manufacturing-program

60 days’ notice. Any changes will be communicated via https://www.grants.gov and https://www.chips.gov.

https://www.grants.gov/ https://www.chips.gov/

Table of Contents

1 PROGRAM DESCRIPTION

1.1 NAPMP Program Overview

1.1.1 CHIPS R&D Mission and Goals

1.1.2 NAPMP Objectives

1.1.3 NAPMP Advanced Packaging R&D NOFO Objectives

1.2 Definitions

1.3 Background

1.3.1 Program Drivers

1.4 Funding Opportunity Detailed Description

1.4.1 Project Activities

1.4.2 Project Structure

1.4.3 R&D Areas Overview

1.4.4 Milestones and Phase-Specific Targets

1.5 General Roles of Award Recipients and NIST

1.5.1 Substantial Involvement

1.5.2 Recipient Responsibilities

1.5.3 Involvement of NIST and CHIPS R&D

1.6 R&D Area-specific Information for Project-Level Technical Plans

1.6.1 R&D Area 1: Equipment, Tools, Processes, and Process Integration

1.6.2 R&D Area 2: Power Delivery and Thermal Management

1.6.3 R&D Area 3: Connector Technology, Including Photonics and Radio Frequency (RF) 48

1.6.4 R&D Area 4: Chiplets Ecosystem

1.6.5 R&D Area 5: Co-design/Electronic Design Automation (EDA)

1.7 Project Level Non-Technical Plans

1.7.1 Education and Workforce Development (EWD) Plans

1.7.2 Commercial Viability and Domestic Production (CVDP) Plans

1.8 Broader Impacts

1.8.1 Commitments to Future Investment

1.8.2 Support for other R&D Programs

1.8.3 Creating Inclusive Opportunities

1.8.4 Environmental Responsibility

1.8.5 Community Impact and Support

1.9 Project Coordination

1.10 Project Assessments

1.11 Government-Furnished Property (GFP) and Government Furnished Information (GFI)

2 FEDERAL AWARD INFORMATION

2.1 Funding Instrument

2.2 Multi-Year Funding Policy

2.3 Funding Availability

2.3.1 Eligible Uses of Funds

2.4 Indirect (F&A) Costs

2.5 Public Access to CHIPS R&D Research

2.6 Fundamental Research

2.6.1 Fundamental Research Declaration

2.6.2 On-Campus Research

2.6.3 Pre-Publication Reviews

2.7 Research Security

2.7.1 Research Security Definitions

2.7.2 Authorities

2.7.3 Requirement for a Research Security Plan or Program

2.7.4 Covered Individuals

2.7.5 Foreign Entities of Concern

2.7.6 Research Security Review and Risk Determination

2.7.7 Non-Discrimination

2.7.8 Potential for Mitigation

2.7.9 Requirement for Recipients to Update Research Security-Related Information

2.8 Intellectual Property (IP) and Domestic Production

2.8.1 Domestic Production

2.8.2 Domestic Control

3 ELIGIBILITY INFORMATION

3.1 Eligible Applicants

3.1.1 Federally Funded Research and Development Centers

3.1.2 Federal Entities

3.1.3 Individuals and Unincorporated Sole Proprietors

3.1.4 Foreign Partners and Foreign Research Activities

3.2 Cost share

3.2.1 Provisions

3.2.2 Allocation

3.3 Allowable Costs

4 APPLICATION AND SUBMISSION INFORMATION

4.1 Overview

4.2 Address to Request Applications Package

4.3 Page Count Guidance

4.4 Submission Format

4.4.1 Amendments

4.4.2 Proprietary and Sensitive Business Information

4.5 Concept Paper Instructions

4.5.1 Required Forms and Documents

4.5.2 Concept Paper Format and Guidelines

4.6 Full Applications

4.6.1 Required Forms and Documents

4.6.2 Attachment of Required Documents

4.6.3 Full Application Format and Guidelines

4.7 Application Replacement Pages

4.8 Unique Entity Identifier and System for Award Management (SAM)

4.9 Submission Dates and Times

4.9.1 Concept Papers

4.9.2 Full Applications

4.10 Intergovernmental Review

4.11 Funding Restrictions

5 APPLICATION REVIEW INFORMATION

5.1 Concept Paper Evaluation Criteria

5.1.1 Relevance to economic and national security

5.1.2 Overall Scientific and Technical Merit

5.1.3 Project Management

5.1.4 Transition and Impact Strategy

5.1.5 Education and Workforce Development (EWD)

5.2 Concept Paper Selection Factors

5.3 Full Application Evaluation Criteria

5.3.1 Relevance to Economic and National Security

5.3.2 Overall Scientific and Technical Merit

5.3.3 Project Management, Resources, and Budget

5.3.4 Transition and Impact Strategy

5.3.5 Education and Workforce Development (EWD)

5.4 Selection Factors

5.5 Review and Selection Process

5.5.1 Initial Review of Applications

5.5.2 Review of Concept Papers

5.5.3 Review of Full Applications

5.6 Additional Information

5.6.1 Safety

5.6.2 Notification to Unsuccessful Applicants

5.6.3 Retention of Unsuccessful Applications

6 Federal Award Administration Information

6.1 Federal Award Notices

6.2 Administrative and National Policy Requirements

6.2.1 Terms and Conditions

6.2.2 Funding Availability and Limitation of Liability

6.2.3 Collaborations with CHIPS R&D and Other Federal Agencies

6.2.4 Use of Federal Government-Owned Intellectual Property

6.2.5 Export Controls

6.2.6 Post-Award Negotiation and Modification

6.3 Reporting

6.3.1 Reporting Requirements

6.3.2 Audit Requirements

6.3.3 Federal Funding and Accountability Transparency Act of 2006

7 AGENCY CONTACTS

8 OTHER INFORMATION

8.1 Personal and Business Information

8.2 Public Website

8.3 Attachment A – Associate Recipient Agreements

Full Announcement Text

1 PROGRAM DESCRIPTION

The statutory authorities for the National Advanced Packaging Manufacturing Program (NAPMP) Advanced Packaging R&D Notice of Funding Opportunity (NOFO) are 15 U.S.C. § 4656(d) and 15 U.S.C. § 4659, as amended,1 and 15 U.S.C. § 272(b)(4).

1.1 NAPMP PROGRAM OVERVIEW

The 2022 CHIPS and Science Act appropriated $50 billion to the U.S. Department of Commerce (the Department’s) CHIPS for America program, to support semiconductor research and development (R&D) and to expand semiconductor manufacturing capacity in the United States.

This includes $39 billion for the Department to expand domestic semiconductor manufacturing capacity through an incentives program and $11 billion to advance U.S. leadership in semiconductor R&D. These R&D advances are being realized through four programs: (1) the National Semiconductor Technology Center (NSTC), (2) the NAPMP, (3) the CHIPS Metrology Program, and (4) a CHIPS Manufacturing USA Institute. These investments, across both the R&D and incentives programs, seek to strengthen U.S. competitiveness, support domestic production and innovation, create, across the country, good jobs with working conditions consistent with the Good Jobs Principles published by the Departments of Commerce and Labor, and advance U.S. economic and national security.

1.1.1 CHIPS R&D Mission and Goals

Within the CHIPS for America program, the mission of the National Institute of Standards and Technology’s (NIST) CHIPS Research and Development Office (CHIPS R&D) is to accelerate the development and commercial deployment of foundational semiconductor technologies by establishing, connecting, and providing access to domestic research efforts, tools, resources, workers, and facilities. CHIPS R&D aims to achieve the following goals by 2030:

• U.S. Technology Leadership: The United States improves its capacity to invent, develop, prototype, manufacture, and deploy the foundational semiconductor technologies of the future.

• Accelerated Ideas to Market: The best ideas achieve commercial scale as quickly and cost effectively as possible.

• Robust Semiconductor Workforce: Inventors, designers, researchers, developers, engineers, technicians, and staff sustainably meet evolving domestic government and commercial sector needs.

1.1.2 NAPMP Objectives

The NAPMP seeks to drive U.S. leadership in advanced packaging and provide the technology and skilled workforce needed for packaging manufacturing in the United States. Coupled with

1 DOC CHIPS activities are authorized by Title XCIX—Creating Helpful Incentives to Produce Semiconductors for America of the William M. (Mac) Thornberry National Defense Authorization Act for Fiscal Year 2021 (Pub. L. 116-283, referred to as the CHIPS Act).

https://www.dol.gov/general/good-jobs/principles

CHIPS manufacturing incentives, NAPMP-funded objectives will establish a vibrant, self-sustaining, profitable, domestic advanced packaging industry where advanced-node chips manufactured in the United States and abroad can be packaged in appropriate volumes within the United States and innovative designs and architectures are enabled through leading-edge packaging capabilities. In combination with other CHIPS for America education and workforce efforts, NAPMP-funded activities will produce the diverse and capable workforce needed for the success of the domestic packaging sector.

1.1.3 NAPMP Advanced Packaging R&D NOFO Objectives

The objective of this NOFO is to enable, through R&D, innovative new advanced packaging flows suitable for adoption by U.S. industry. To pursue this objective, CHIPS R&D designed the NOFO with the following elements.

• First, the NOFO sets out, across multiple R&D areas, key challenges and technology gaps in advanced packaging which must be addressed.

• Second, it provides for coordinated R&D efforts aligned through common technical targets so that results collectively contribute to composable and implementable advanced packaging flows.

• Finally, it provides for demonstrating the benefits of R&D results through a combination of prototypes and baseline packaging flows.

1.2 DEFINITIONS

For purposes of this NOFO, the terms listed below have the following meanings.

(1) 3DHI – Three-dimensional heterogeneous integration (3DHI) refers to the ability to stack separately manufactured components – chips or wafers originating in different facilities, containing different semiconductors and materials – within a single package to improve functionality and performance.

(2) Applied Research – “Original investigation undertaken in order to acquire new knowledge.”2

(3) ASIC – An application-specific integrated circuit (ASIC) is a chip that is designed for a particular application or use.

(4) Associate Recipient – A Recipient that agrees to cooperate with other Recipients by sharing information, data, technical knowledge, expertise, and/or resources essential to meet the objectives of the program under a mutual agreement that protects the proprietary information and intellectual property of both parties.

(5) Basic Research – “Experimental or theoretical work undertaken primarily to acquire new knowledge of the underlying foundations of phenomena and observable facts.

Basic research may include activities with broad or general applications in mind, such as the study of how plant genomes change, but should exclude research directed towards a specific application or requirement, such as the optimization of the genome of a specific crop species.”3

2 OMB Circular A-11 84.2.(c).1 3 OMB Circular A-11 84.2.(c).2

(6) Bring up – An iterative, phased process including initial testing, debugging, adjusting, and validating a device or system to achieve readiness for production or manufacturing.

(7) Chip – An assembly of electronic components, including miniaturized active and passive devices and their interconnections, that are built up on a semiconductor material, forming an integrated circuit.4

(8) Chiplet – A small, functionally targeted semiconductor chip that, when assembled at tight pitch and placement, results in a highly functional subsystem. Examples of chiplets in an ecosystem include common functions such as CPU, input/output devices, memory, domain-specific accelerators, etc.

(9) Cluster – A sequence of packaging steps, including relevant equipment and processes, that enables a key part of the packaging flow.

(10) CMP – Chemical Mechanical Planarization, a process to remove excess materials and smooth surfaces through a combination of chemical and mechanical methods.

(11) Design Targets – Information provided to applicants for this NOFO to inform their technology design and implementation choices; design targets in this NOFO are not mandatory but are provided to facilitate adoption by industry and make design efforts more manageable by focusing design options.

(12) Die – A small block of semiconducting material on which a given functional circuit is fabricated.

(13) Exemplar Application – An application area that serves as a model or archetype representing a broad range of computing system needs and challenges. For purposes of this NOFO, Exemplar Applications are limited to high-performance computing (e.g. for artificial intelligence) or low-power systems (e.g. hand-held mobile devices).

(14) Heterogeneous Integration – The integration of separately manufactured components into a higher-level assembly that, in the aggregate, provides enhanced functionality and improved operating characteristics.5

(15) High-performance computing (HPC)6 – The use of supercomputers or computer clusters to solve advanced, intensive computational problems such as artificial intelligence applications or extreme-scale models and simulations.

(16) Low-Power Systems – Computational systems in which power is a primary limiting factor such as battery-powered, hand-held mobile devices.

(17) Milestones – Actions or events marking a significant change or stage in developments in a project.

(18) Non-Technical Target – Specific non-technical objectives in either education and workforce development, environmental sustainability, or commercial viability and domestic production to be achieved by the end of a project phase or at the end of the project as specified in the NOFO.

(19) PDK/ADK – A process design kit (PDK) is a set of files created by a semiconductor foundry to model and simulate the design and performance of the foundry fabrication

4 https://www.britannica.com/technology/integrated-circuit 5 https://eps.ieee.org/technology/heterogeneous-integration-roadmap.html 6 https://ieeexplore.ieee.org/abstract/document/6345493 processes. An assembly design kit (ADK) extends many of the benefits of PDKs to semiconductor packaging or assembly.

(20) Phase-specific Target – Includes both technical and non-technical targets, derived from applicant-specified milestones, to inform go/revise/no-go points for the transition from one project phase to the next. Phase-specific technical targets focus on measurable progress toward Project-Level Technical Targets. Phase-specific non-technical targets focus on measurable progress towards the Project-Level Non- Technical Targets defined by the applicant’s Education and Workforce Development plan and Commercial Viability and Domestic Production plan. CHIPS R&D may identify additional phase-specific targets, including to address other applicant-defined plans.

(21) Power Delivery Network or Power Distribution Network (PDN) – A network of devices, traces, and planes that supply power to a chiplet(s). The purpose of the PDN is to ensure that the correct voltages and currents are delivered to each device without being over- or under-designed for the application.

(22) Process integration – Sequences and combinations of Unit Processes in which the end result is influenced by the unit process parameters and interactions between the processes.

(23) Project – All activities funded under a single award made under this NOFO, including but not limited to all planning and management; basic and applied research; systems, equipment, tools, and software systems development and production as appropriate to the R&D area; commercial viability analyses and domestic production preparation, integrated education and workforce development, and prototype production.

(24) Project-level Technical Target – Specific technical advances to be achieved by the end of the project (See Section 1.6).

(25) Project-level Non-Technical Target – Specific non-technical targets in either education and workforce development, environmental sustainability, or commercial viability and domestic production to be achieved by the end of the project (See Section 1.7).

(26) Prototype – A functional system and the end-to-end process flow for producing that system, both of which are designed for the purpose of measuring the characteristics of the flow and the resulting system. These characteristics include packaging process characteristics such as process stability, yield, reliability, and defectivity; and system characteristics such as functionality, performance, power/energy consumption, and thermal dissipation.

(27) Recipient – The entity that receives an award directly from a Federal awarding agency to carry out an activity under a financial assistance program.

(28) Semiconductor – An integrated electronic device or system, most commonly manufactured using materials such as, but not limited to, silicon, silicon carbide, or III- V compounds, and processes such as, but not limited to, lithography, deposition, and etching. Such devices and systems include but are not limited to analog and digital electronics, power electronics, and photonics, for memory, processing, sensing, actuation, and communications applications.

(29) SMART– A framework for writing objectives that are Specific, Measurable, Achievable, Relevant, and Time-Bound and provide the details for how an organization will achieve an objective.

(30) Subassembly – An assembled unit designed to be incorporated with other units in a finished product.7

(31) Subrecipient – An entity that receives a subaward from a pass-through entity (Recipient) to perform part of a program or project in accord with terms of a subaward.

A subrecipient may also be a recipient of another award made by a Federal awarding agency.

(32) Substrate – The foundation or supporting platform on which or within which the elements of a semiconductor device are fabricated or attached.8

(33) Substrate material – The class of materials from which a substrate is made. Substrates relevant to this NOFO are organic, glass, and semiconductor-based (e.g., silicon-based) classes of materials.

(34) Tape out – The final stage of the design process for integrated circuits or printed circuit boards before they are sent for manufacturing.9

(35) Technical Targets – Technical specifications, such as line spacing, set by CHIPS R&D as objectives for project outputs to promote innovation.

(36) Technology Demonstrator – A functional device or system specifically designed to assess technologies and capabilities created by funded projects through scale-down, scale-out, and chiplets ecosystem approaches in comparison to conventional technologies.

(37) Technology Node, Process Node, or Node – While historically used to refer to chip feature sizes, such as gate length or line pitch, these terms are now widely used, including in this NOFO, to refer to a particular generation of chip technologies.10

(38) TSV – Through silicon via, a vertical electrical connection that passes through a silicon wafer or die.11

(39) Unit process – A discrete operation in a semiconductor manufacturing flow, such as lithography, deposition, or etching.

1.3 BACKGROUND

The technical focus and R&D area goals of this NOFO are informed by a series of industry roadmaps, including the 2024 IEEE Heterogeneous Integration Roadmap and International Roadmap for Devices and Systems, the Semiconductor Research Corporation (SRC) Microelectronics Advanced Packaging Technologies Roadmap; the UCLA and SEMI Manufacturing Roadmap for Heterogeneous Integration and Electronics Packaging (MRHIEP);

and the iNEMI 5G/6G mmWave Materials and Electrical Test Technology Roadmap.

7 https://www.merriam-webster.com/dictionary/subassembly 8 Derived from the JEDEC general dictionary at https://www.jedec.org/standards-documents/dictionary/terms/substrate-semiconductor-device-1-general# 9 https://en.wikipedia.org/wiki/Tape-out 10 https://semiengineering.com/knowledge_centers/manufacturing/process/nodes/ 11 https://en.wikipedia.org/wiki/Through-silicon_via https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2024-edition.html https://irds.ieee.org/editions https://irds.ieee.org/editions https://srcmapt.org/ https://chips.ucla.edu/page/MRHIEP%20Project/MRHIEP%20Final%20Report https://www.inemi.org/article_content.asp?adminkey=cc22bf8eb1bfb8248c594509fe54dd9b&article=275

Collectively, these roadmaps emphasize that emerging technologies like high performance computing and artificial intelligence, advanced telecommunications, biomedical devices, and autonomous vehicles require leap-ahead advances in microelectronics capabilities.12

In the past, the semiconductor industry has largely addressed performance needs by increasing the number and density of transistors on a chip, a process known as transistor scaling. However, the previous pace of transistor scaling, as expressed by Moore’s Law, is slowing and cannot alone provide the performance improvements needed for emerging microelectronics technologies. Improving all aspects of system performance to support the breadth of new semiconductor applications will require innovations in advanced packaging.

Semiconductor packaging serves two general purposes. One is to protect the chip mechanically, thermally, and environmentally. The other is to enable reliable inter-chip communication and data processing, power delivery, and a stable test and system integration platform. Advanced packaging and related capabilities, such as heterogeneous integration, are designed to increase all aspects of system performance by linking multi-component assemblies with large numbers of interconnects to achieve a degree of integration that blurs the line between chip and package.

1.3.1 Program Drivers

Aligned with the industry roadmaps referenced above and the objectives outlined in Section 1.1.2, NAPMP has identified multiple program drivers required for domestic improvements in advanced packaging, as detailed in the subsections set out below.

1.3.1.1 Scale Down and Scale Out

The first program driver is the ability in advanced packaging to scale down and scale out.

Scaling down refers to shrinking the size of the features on the package and increasing interconnect densities. Scaling out refers to increasing the number of chips assembled on the substrate and overall functional density in both two-dimensional (2D) and three-dimensional (3D) architectures. Examples of scaling down goals and targets can be found in the MRHIEP roadmap.

The primary driver for advanced 2D and 3D packaging technologies is the need for increased interconnect densities to support [heterogeneous integration] and deliver increasing bandwidth in a power efficient manner while enabling efficient power delivery.

2024 IEEE Heterogeneous Integration Roadmap (Chapter 22, p. 14)

Accordingly, in their planning activities, applicants should consider interdisciplinary, team-based approaches that contribute to scaling down and scaling out in advanced packaging.

12 These roadmaps are cited in this NOFO for informational purposes. The fact that the roadmaps are cited does not necessarily mean that the entire content of these publications reflects the views of the Department of Commerce, CRDO and/or NIST.

https://chips.ucla.edu/page/MRHIEP%20Project/MRHIEP%20Final%20Report https://eps.ieee.org/technology/heterogeneous-integration-roadmap/2024-edition.html

1.3.1.2 Heterogeneous Integration Including Chiplets

The second program driver is advancing capabilities for three-dimensional heterogeneous integration (3DHI), including chiplets. This driver focuses on the NAPMP vision for creating “an advanced packaging ecosystem based on heterogeneous chiplet technology to promote widespread and easy use of the technologies developed.” NAPMP Vision Paper (p. 3)

Heterogeneous Integration is essential to maintain the pace of progress with higher performance, lower latency, smaller size, lighter weight, lower power requirement per function, and lower cost. IEEE Heterogeneous Integration Roadmap 2021 (Chapter 1, p. 12)

[T]he exponential growth in package pin counts and I/O power consumption, domain-specific architectures, technical and business models of [intellectual property] reuse, and mixed technology node chiplets will drive advances in HI and advanced packaging. SRC Microelectronics Advanced Packaging Technologies Roadmap (p. 154)

In developing proposals, applicants should incorporate considerations for heterogeneous integration and chiplets-based architectures.

1.3.1.3 End-to-End Advanced Packaging Flows

The third program driver is enabling end-to-end advanced packaging flows suitable for adoption by industry. This driver, per the NAPMP Vision Paper, addresses the NAPMP objective to “develop packaging platforms capable of both high-volume and customized manufacturing.”

The CHIPS Research and Development Office has designed the NAPMP to include an Advanced Packaging Piloting Facility ([N]APPF) where successful development efforts will be transitioned and validated for scaled transition to U.S. manufacturing. NAPMP Vision Paper (p. 3)

To address this driver, applicants should plan for implementing their research outputs in a full packaging flow.

1.3.1.4 Prototypes for Demonstrating Functionality

The fourth driver is demonstrating functionality in prototypes to provide evidence for new capabilities, increased efficiencies, lowered production costs, reduced environmental impact, or other benefits resulting from research advances. This driver addresses the NAPMP vision, per the NAPMP Vision Paper, for enabling “successful advanced packaging development efforts to be validated and transitioned at scale to U.S. manufacturing.” This NOFO includes support for designing prototypes in two exemplar application areas: high performance computing (HPC), including artificial intelligence (AI), and low-power systems, such as handheld mobile devices.

1.3.1.5 Aligning R&D Efforts for Implementable Packaging Flows.

The final program driver is aligning R&D efforts so that R&D results are not isolated or incompatible but instead collectively contribute to implementable advanced packaging flows.

Successful applicants should expect to participate in coordination and information-sharing across projects in all R&D areas, consistent with Section 1.5.

https://www.nist.gov/system/files/documents/2023/11/19/NAPMP-Vision-Paper-20231120.pdf https://eps.ieee.org/images/files/HIR_2021/ch01_overview.pdf https://srcmapt.org/wp-content/uploads/2024/03/SRC-MAPT-Roadmap-2023-v4.pdf https://srcmapt.org/wp-content/uploads/2024/03/SRC-MAPT-Roadmap-2023-v4.pdf

1.4 FUNDING OPPORTUNITY DETAILED DESCRIPTION

1.4.1 Project Activities

Project activities are expected to include, but not necessarily be limited to, all of the following:

basic and applied research; systems, equipment, tools, and software systems development and production as appropriate to the R&D area; commercial viability analyses and domestic production preparation; integrated education and workforce development; and prototype production.

CHIPS R&D expects that applicants assembling teams (i.e., an applicant from industry or academia working with one or more eligible subrecipients) may be best suited to collectively provide the full range of expertise and capabilities needed to achieve the program objectives and to successfully strengthen U.S. advanced packaging innovation. Equally important, effective partnerships can promote inventiveness, clarify future demand, improve transparency and security, solidify business and domestic manufacturing plans (including plans for technology adoption by defense and commercial partners), develop environmentally sustainable manufacturing solutions, help educate the future workforce, mitigate the risk of future chip shortages or oversupply, and support a more productive, efficient, and self-sustaining semiconductor ecosystem.

CHIPS R&D therefore strongly encourages proposals from teams that demonstrate collaboration across the innovation, manufacturing, supply chain, and customer landscape, as well as across the industry, non-profit, and academic sectors.

1.4.2 Project Structure

Consistent with the objectives described in Section 1.1.2 and Section 1.1.3, applications under this NOFO must describe projects that:

(1) Focus on one of the R&D areas described in Section 1.4.3

(2) Propose achieving specific R&D area Technical Targets and Project-Level Non-

Technical Targets, as described in Sections 1.6 and 1.7

(3) Define milestones marking measurable progress toward those targets

(4) Provide for supplying any required demonstration devices to CHIPS R&D and to other entities for research purposes, as described under each R&D area in Sections 1.6.1 through 1.6.5

(5) Sub-divide project activities into four phases, with each phase ranging in length as described under each R&D area in Sections 1.6.1 through 1.6.5

(6) Are structured around a five (5) year period of performance

1.4.3 R&D Areas Overview

Consistent with the NAPMP Vision Paper, this NOFO calls for Concept Papers and invited Full Applications in the following five R&D areas:

(1) Equipment, Tools, Processes, and Process Integration https://www.nist.gov/document/vision-national-advanced-packaging-manufacturing-program

(2) Power Delivery and Thermal Management

(3) Connector Technology, Including Photonics and Radio Frequency (RF)

(4) Chiplets Ecosystem

(5) Co-design/Electronic Design Automation (EDA)

To ensure that funded R&D efforts meet the objectives described in Section 1.1technical targets for applicants to achieve are described in each of the five R&D areas described in Sections 1.6.1 through 1.6.5 below. Individual Concept Papers and invited Full Applications must address only one of the R&D areas.

1.4.4 Milestones and Phase-Specific Targets

Applicants should propose milestones that represent measurable steps toward achieving the applicant’s Project-Level Technical Plans under the relevant, applicant-selected R&D areas (see relevant R&D area requirements in Section 1.6). Applicants should also propose milestones that represent measurable steps toward achieving their EWD plans and CVDP plans as described in Sections 1.7.1 and 1.7.2. Applicants may propose additional non-technical milestones.

Milestones for Project-Level Technical plans, EWD plans, and CVDP plans should be SMART and suitable for validation by the applicant, CHIPS R&D staff, independent expert technology evaluators, or a combination of these entities, as appropriate.

The CVDP milestones should complement the technical milestones. For example, technical milestones should, as appropriate, inform CVDP targets and milestones, such as manufacturing time, cost, performance, and projected customer demand. Additional CVDP milestones may include measurable progress in business plan development, customer identification, investor commitments, technology licensing agreements, and enabling manufacturing in the United States.

In coordination with the Financial Assistance Agreements Management Office (FAAMO), CHIPS R&D may conduct negotiations with applicants deemed meritorious by the evaluation panel and determined by CHIPS R&D to stand a reasonable chance of being funded, in order to

(1) refine the proposed milestones (2) define phase-specific targets derived from the proposed milestones, and (3) address other matters as determined by CHIPS R&D. These phase-specific targets will inform go/revise/no-go points for the transition from one project phase to the next.

1.5 General Roles of Award Recipients and NIST

1.5.1 Substantial Involvement

CHIPS R&D will have ongoing and substantial programmatic involvement with award recipients throughout the award period of performance, although primary responsibility for project activities will reside with award recipients.

1.5.2 Recipient Responsibilities

This program is subject to Attachment A – Associate Recipient Agreements (see Section 8.3).

The success of funded activities under this NOFO hinges upon continuous collaboration and coordination across funding recipients. Therefore, any resultant award will contain terms and conditions pursuant to the stipulations outlined in Attachment A.

CHIPS R&D may further require the recipients to:

(1) Attend a kick-off conference, held at the beginning of the performance period, to help ensure that recipients have a clear understanding of the program and its components; and

(2) If applicable, coordinate with NIST in the development of collaborations with other Federal agencies, including NIST laboratory programs, or other CHIPS-funded activities.

1.5.3 Involvement of NIST and CHIPS R&D

NIST / CHIPS R&D may provide, as appropriate:

(1) Programmatic and financial oversight of the Institute award;

(2) Input or direction relevant to the coordinated provision of information or deliverables across recipients, consistent with any requirements to protect intellectual property;

(3) Subject matter experts to support collaborative research;

(4) Coordination and engagement with other Federal agencies or with other CHIPS-funded activities; and

(5) Research security and other relevant support, as described in Section 2.7and Section

3.1.4.

In an award agreement issued under this NOFO, NIST and potentially other Federal agencies may require access to research material and data.

1.6 R&D AREA-SPECIFIC INFORMATION FOR PROJECT-LEVEL TECHNICAL

PLANS

The following subsections provide information specific to each R&D area to assist applicants in preparing responsive Project-Level Technical Plans for both Concept Papers (see Section 4.5) and Full Applications (see Section 4.6).

1.6.1 R&D Area 1: Equipment, Tools, Processes, and Process Integration

1.6.1.1 Anticipated Amounts

For the Equipment, Tools, Processes, and Process Integration R&D area, CHIPS R&D anticipates making available up to approximately $450,000,000 for funding multiple awards in amounts ranging from approximately $10,000,000 to approximately $150,000,000 in Federal funds per award, with a five (5) year period of performance per award. While cost share is not required, CHIPS R&D will give preference to proposals that demonstrate credible cost share commitments, consistent with Section 3.2.

1.6.1.2 Background

Advances in packaging processes and equipment are required to achieve the scaled down dimensions set out in the previous NAPMP Materials and Substrates NOFO (see Table 2, page 14 in that document) and to enable innovative, manufacturable advanced packaging flows suitable for adoption by U.S. industry. The processes and equipment that are the focus for this R&D area are those that will enable end-to-end advanced packaging flows suitable for high-volume manufacturing, customized manufacturing, piloting, and prototyping. The new tools and processes that emerge from this R&D activity will create a need for education and training programs to supply a skilled equipment and process workforce to a vibrant and growing U.S.

advanced packaging sector.

Proposals within this R&D area should focus on developing: (1) advanced, flexible, extensible process technologies and integration sequences required to produce a packaged subassembly;

and (2) packaging equipment to run the advanced processes and to handle the required substrates, wafers and dies, all at scaled down dimensions and designed for use at commercial scale.

This investment in equipment, tools, processes, and process integration is intended to achieve the following outcomes.

• 3-5 years: New tools, processes, and integrated flows from R&D projects are installed in the NAPPF to assess efficacy and extendibility and to gather insights into suitability for commercial adoption. Tools and processes are incorporated in NAPPF prototyping flows.

Programs are established to improve tool and process performance and packaging flow manufacturability. The first new graduates emerge from new education and training programs for advanced packaging equipment and process technology. Enrollments are diverse and growing.

• 10 years: Robust production equipment and environmentally sustainable, integrated advanced packaging processes for chiplet-based manufacturing at commercial scale are available for use by U.S. industry. End-to-end advanced packaging flows composed of the equipment, processes, and integration sequences developed in this R&D area are being used by U.S. industry in chiplet-based heterogenous integration and 3D architectures. Graduates from education and training programs are employed in good jobs in the advanced packaging sector.

1.6.1.3 Equipment, Tools, Processes, and Process Integration Objectives

The objective of this R&D area is to develop, demonstrate and deliver advanced tools, processes, process integration sequences and fine-pitch assembly methods required for chiplet-based packaging architectures and 3DHI. Development activities are organized around packaging process clusters, with a cluster defined as a sequence of steps that enable a key part of the packaging flow.

The five process clusters relevant to this R&D area are the following.

1. Chiplet Singulation: Producing singulated chiplets from incoming wafers that are fully patterned with dies for subsequent assembly https://www.nist.gov/document/nofo-national-advanced-packaging-manufacturing-program-napmp-materials-substrates

2. Chiplet to Substrate Assembly and Bonding: Positioning and attaching chiplets with ultra-fine-pitch bonding pads to substrates in dense arrays with close chiplet-to-chiplet spacing

3. 3DHI: Forming heterogeneous chiplet stacks with ultra-fine bonding pad pitches

4. Collective Chiplet Processing: Methods to simultaneously process an array of singulated chiplets using a handler wafer or other suitable substrate

5. Finishing: Incorporating advanced power delivery, passivation, thermal management, and connectors, using technologies included but not limited to photonics, into the packaged device

Applications for this R&D area must address one or both of the following two categories:

1) Process Cluster Development: Applications in this category must address full tool and process solutions for one or more of the five packaging process clusters described above.

Successful applications will present a comprehensive R&D approach that encompasses integrated tool and process development, interactions between process steps, and step sequencing within each cluster and between clusters as appropriate. Applicants are strongly encouraged to incorporate in their applications innovative and potentially transformative technologies to improve cluster performance and capabilities.

2) End-to-End Advanced Packaging Flows: Applications in this category must focus on sequencing multiple clusters into end-to-end packaging process flows to create a functional, testable packaged system (or subsystem) with all the required elements and with performance characteristics that leverage the advanced packaging constructs being funded. These complete systems can be targeted for specific applications such as high-performance computing, artificial intelligence, and low-power systems (including low power sensor nodes, IoT, and biomedical applications), among others. If the intended end-to-end flow requires additional tools or processes not covered in the clusters, they need to be developed or provided as part of the application and included in the proposed budget.

For this category, applications are sought that will include plans for the following:

1. Developing an integrated end-to-end packaging process flow based on the process technology and equipment developed in this R&D area

2. A performer-developed Bring-up Assembly Vehicle (described in Section 1.6.1.9) to demonstrate the integrated process flow

3. Plans to transition the integrated process flow to the NAPPF

The subsections below describe objectives for each of the five clusters and end-to-end packaging flows.

1.6.1.4 Cluster 1 - Chiplet Singulation

The R&D objective for this cluster is to develop advanced, extensible, manufacturable process flows and associated equipment to produce singulated chiplets from incoming wafers that are patterned with dies.

Advanced packaging architectures based on heterogeneous chiplet technology use advanced bonding methods to attach chiplets with ultra-fine-pitch bonding pads to substrates. The singulation cluster must therefore produce chiplets that are free from surface particles, defects, and contaminants that negatively impact bond quality, yield, and reliability. Close chiplet spacing is an important parameter for system-level performance scaling. The singulation cluster must therefore produce chiplets with repeatable dimensions and sidewalls free from defects such as cracks and chips that limit chiplet-to-chiplet spacing. Also, flexible tools and processes will be required to singulate a variety of incoming wafers, which may include, for example:

• Different wafer sizes (e.g., 300 mm, 200 mm, 150 mm, 100 mm)

• Full thickness wafers and thinned wafers, with and without thru silicon vias (TSVs)

• Different materials (e.g., Si, SiC, GaAs, GaN)

• Assembled 3DHI wafer stacks

Successful R&D proposals will center on advanced, high-precision,…