CHIPS NAPMP MATERIALS AND SUBSTRATES NOFO.pdf

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NOTICE OF FUNDING OPPORTUNITY (NOFO)

National Advanced Packaging Manufacturing Program (NAPMP) Materials & Substrates

Executive Summary

Federal Agency Name: National Institute of Standards and Technology (NIST), United States Department of Commerce (DOC)

Funding Opportunity Title: FY2024 CHIPS R&D National Advanced Packaging Manufacturing Program (NAPMP) Materials & Substrates

Announcement Type: Initial

Funding Opportunity Number: 2024-NIST-CHIPS-NAPMP-01

Assistance Listing Number(s): 11.042 – CHIPS R&D

Funding Opportunity Description: This NOFO seeks applications for research and development activities that will establish and accelerate domestic capacity for advanced packaging substrates and substrate materials. Through this NOFO, the NAPMP program seeks to achieve the following objectives:

(1) Accelerate domestic R&D and innovation in advanced packaging materials and substrates;

(2) Translate domestic materials and substrate innovation into U.S. manufacturing, such that these technologies are available to U.S. manufacturers and customers, including to significantly benefit U.S. economic and national security;

(3) Support the establishment of a robust, sustainable, domestic capacity for advanced packaging materials and substrate R&D, prototyping, commercialization, and manufacturing; and

(4) Promote a skilled and diverse pipeline of workers for a sustainable domestic advanced packaging industry.

NAPMP plans to release subsequent NOFOs relevant to other research areas and for an Advanced Packaging Piloting Facility (APPF), where successful development efforts will be transitioned and validated for scaled transition to U.S. manufacturing. The APPF is expected to be a key facility for technology transfer to high-volume manufacturing.

Dates: Relevant dates in the application process are listed in Table 1 and described in the text that follows.

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The Department of Commerce may amend this NOFO at any time. It may also close the funding opportunity with at least 60 days’ notice. Changes will be communicated via https://www.grants.gov and https://www.chips.gov.

Webinar Information Session: The National Institute of Standards and Technology (NIST) CHIPS Research and Development Office (CHIPS R&D) will host an informational webinar on March 1, 2024, to provide general information regarding this NOFO, offer general guidance on preparing applications, and answer questions. Proprietary technical discussions about specific project ideas will not be permitted during the webinar, and CHIPS R&D staff will not critique or provide feedback on specific project ideas while they are being developed by an applicant, brought forth during the webinar, or at any time before the deadline for all applications. However, questions about the funding opportunity, eligibility requirements, evaluation and award criteria, selection process, and the general characteristics of a competitive application will be addressed at the webinar and by e-mail to research@chips.gov with “2024-NIST-CHIPS-NAPMP-01 Questions” in the subject line.

There is no cost to attend the webinar, but participants must register in advance.

Participation in the webinar is not required and will not be considered in the review and selection process.

Proposers Day and Teaming Meetings: In addition to the informational webinar described above, CHIPS R&D plans to host a proposers day March 12, 2024, to promote awareness of the funding opportunity and provide a forum for organizations to identify prospective partners. Information about the event can be found on the CHIPS for America events website.

Concept Papers: The submission of a concept paper is required for submission of a full application. Applicants must send an email to research@chips.gov with “2024-NIST-CHIPS- NAPMP-01 Concept Papers” in the subject line to request instructions for submitting Concept Papers. Applicants are strongly advised not to wait until the last minute to request submission instructions. The CHIPS R&D Program will respond by email with instructions for securely submitting a Concept Paper. Concept Papers must be received no later than 11:59 p.m. Eastern Daylight Time, April 12, 2024. Concept papers received after this deadline will not be reviewed or considered.

Table 1. Materials & Substrates NOFO Key Dates

Webinar Information Session March 1, 2024 Proposers Day March 12, 2024 Concept Papers Due April 12, 2024 Invited Full Applications Due July 3, 2024 https://www.grants.gov/ https://www.chips.gov/ https://www.nist.gov/news-events/events/napmp-materials-and-substrates-proposers-day

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Full Applications: Full applications will be accepted only from those applicants invited after concept paper evaluation. Full applications must be received at Grants.gov no later than 11:59 p.m. Eastern Time, July 3, 2024. Applications received after this deadline will not be reviewed or considered. Applicants should be aware, and factor in their application submission planning, that the Grants.gov system closes periodically for routine maintenance. Applicants should visit Grants.gov for information on any scheduled closures.

Full Application Submission Address: Full applications must be submitted using Grants.gov. Paper applications will not be accepted.

Anticipated Amounts: In FY24, CHIPS R&D anticipates making available approximately $300,000,000 for funding of multiple awards in amounts up to approximately $100,000,000 over up to 5 years per award, not including voluntary co-investment, though additional funding may be provided to applicants who address more than one technical area.

Funding Instrument: Awards in this program will be made as cooperative agreements or other transactions, as appropriate for the selected project. See Section 2.1 of this document for additional information regarding the type of award agreement.

Eligibility: Eligible applicants include domestic for-profit organizations; non-profit organizations; accredited institutions of higher education including community and technical colleges; and state, local, territorial, and Indian tribal governments.

Eligible applicants may only submit one concept paper under this NOFO. Entities may not be included as subrecipients on more than two concept papers.

Applicants and recipients are required to have an active registration in SAM.gov and are encouraged to begin the process of registering as early as possible.

Co-investment (cost share) Requirements: Co-investment (cost share) is not required in this program. CHIPS R&D will, however, give preference to applications that demonstrate committed co-investment in their Project Narrative and Budget Narrative and Justification.

See Sections 4.6.1.6 and 4.6.1.8 of this NOFO for additional information.

Public Website, and Frequently Asked Questions (FAQs): CHIPS R&D has a public website with a “Frequently Asked Questions” page and other information pertaining to this Funding Opportunity.

Agency Points of Contact (POC): Section 7 identifies Agency Points of Contact. Applicants must submit all questions in writing to the appropriate agency point of contact with “2024- NIST-CHIPS-NAPMP-01” in the subject line. All inquiries regarding this NOFO must be submitted to the email addresses in that section.

https://www.nist.gov/chips/chips-RD-funding-opportunities https://www.nist.gov/chips/chips-RD-funding-opportunities

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Table of Contents

1 PROGRAM DESCRIPTION

1.1 NAPMP Program Overview

1.1.1 CHIPS R&D Mission and Goals

1.1.2 NAPMP Objectives

1.1.3 NAPMP Materials and Substrates NOFO Objectives

1.2 Definitions

1.3 Background

1.4 Funding Opportunity Detailed Description

1.4.1 Project Activities

1.4.2 Project Structure

1.4.3 Technical Areas

1.5 Project-level Technical Targets

1.5.1 CHIPS R&D-specified Technical Targets

1.5.2 Embedded Substrate Features

1.6 Project-level Non-Technical Targets

1.6.1 Education and Workforce Development (EWD) Targets

1.6.2 Commercial Viability and Domestic Production (CVDP) Targets

1.6.3 Milestones and Phase-Specific Targets

1.7 Demonstration Devices

1.8 Project Phases

1.8.1 Phase 1

1.8.2 Phase 2

1.8.3 Phase 3

1.8.4 Phase 4

1.8.5 Provision of Substrates for CHIPS R&D-Designated Research Projects

1.9 Broader Impacts

1.9.1 Commitments to Future Investment

1.9.2 Support for other R&D Programs

1.9.3 Creating Inclusive Opportunities

1.9.4 Environmental Responsibility

1.9.5 Community Impact and Support

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1.10 PROJECT ASSESSMENTS

1.11 Government-Furnished Property (GFP) and Government Furnished Information (GFI)

2 FEDERAL AWARD INFORMATION

2.1 Funding Instrument

2.2 Multi-Year Funding Policy

2.3 Funding Availability

2.3.1 Eligible Uses of Funds

2.4 Indirect (F&A) Costs

2.5 Public Access to CHIPS R&D Research

2.6 Fundamental Research

2.6.1 Fundamental Research Declaration

2.6.2 On-Campus Research

2.6.3 Pre-Publication Reviews

2.7 Research Security

2.7.1 Research Security Definitions

2.7.2 Authorities

2.7.3 Requirement to Submit a Research Security Plan

2.7.4 Covered Individuals

2.7.5 Foreign Entities of Concern

2.7.6 Research Security Review and Risk Determination

2.7.7 Non-Discrimination

2.7.8 Potential for Mitigation

2.7.9 Requirement for Recipients to Update Research Security-Related Information

2.8 Intellectual Property (IP) and Domestic Production

3 ELIGIBILITY INFORMATION

3.1 Eligible Applicants

3.1.1 Federally Funded Research and Development Centers

3.1.2 Federal Entities

3.1.3 Individuals and Unincorporated Sole Proprietors

3.1.4 Foreign Partners and Foreign Research Activities

3.2 Co-Investment

3.2.1 Provisions

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3.2.2 Allocation

3.3 Allowable Costs

4 APPLICATION AND SUBMISSION INFORMATION

4.1 Overview

4.2 Address to Request Applications Package

4.3 Page Count Guidance

4.4 Submission Format

4.4.1 Amendments

4.4.2 Proprietary and Sensitive Business Information

4.5 Concept Papers

4.5.1 Required Forms and Documents

4.5.2 Concept Paper Format and Guidelines

4.6 Full Applications

4.6.1 Required Forms and Documents

4.6.2 Attachment of Required Documents

4.6.3 Full Application Format and Guidelines

4.7 Full Application Replacement Pages

4.8 Unique Entity Identifier and System for Award Management (SAM)

4.9 Submission Dates and Times

4.9.1 Concept Papers

4.9.2 Full Applications

4.10 Intergovernmental Review

4.11 Funding Restrictions

5 APPLICATION REVIEW INFORMATION

5.1 Concept Paper Evaluation Criteria

5.1.1 Relevance to economic and national security

5.1.2 Overall Scientific and Technical Merit

5.1.3 Project Management

5.1.4 Transition and Impact Strategy

5.2 Concept Paper Selection Factors

5.3 Full Application Evaluation Criteria

5.3.1 Relevance to economic and national security

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5.3.2 Overall Scientific and Technical Merit

5.3.3 Project Management, Resources, and Budget

5.3.4 Transition and Impact Strategy

5.4 Selection Factors

5.5 Review and Selection Process

5.5.1 Initial Review of Applications

5.5.2 Review of Concept Papers

5.5.3 Review of Full Applications

5.6 Additional Information

5.6.1 Safety

5.6.2 Notification to Unsuccessful Applicants

5.6.3 Retention of Unsuccessful Applications

6 Federal Award Administration Information

6.1 Federal Award Notices

6.2 Administrative and National Policy Requirements

6.2.1 Terms and Conditions

6.2.2 Funding Availability and Limitation of Liability

6.2.3 Collaborations with CHIPS R&D and Other Federal Agencies

6.2.4 Post-Award Involvement of Foreign Entities

6.2.5 Use of Federal Government-Owned Intellectual Property

6.2.6 Export Controls

6.3 Reporting

6.3.1 Reporting Requirements

6.3.2 Audit Requirements

6.3.3 Federal Funding and Accountability Transparency Act of 2006

7 AGENCY CONTACTS

8 OTHER INFORMATION

8.1 Personal and Business Information

8.2 Public Website

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Full Announcement Text

1 PROGRAM DESCRIPTION

The statutory authority for the National Advanced Packaging Manufacturing Program (NAPMP) Materials & Substrates NOFO is 15 U.S.C. §4656(d) and 15 U.S.C. §4659, as amended,1 and 15 U.S.C. §272(b)(4).

1.1 NAPMP PROGRAM OVERVIEW

The CHIPS and Science Act appropriated $50 billion to the Department of Commerce’s CHIPS for America program both to support semiconductor research and development (R&D) and to expand semiconductor manufacturing capacity in the United States. This includes $39 billion for the Department of Commerce (the Department) to expand domestic semiconductor manufacturing capacity through an incentives program and $11 billion to advance U.S. leadership in semiconductor R&D. These R&D advances will be realized through four programs: the National Semiconductor Technology Center (NSTC), the National Advanced Packaging Manufacturing Program (NAPMP), the CHIPS Metrology Program, and Manufacturing USA institute(s). These investments, across both the R&D and incentives programs, seek to strengthen U.S. competitiveness, support domestic production and innovation, create, across the country, good jobs with working conditions consistent with the Good Jobs Principles published by the Departments of Commerce and Labor, and advance U.S. economic and national security.

1.1.1 CHIPS R&D Mission and Goals

Within CHIPS for America, the mission of the National Institute of Standards and Technology’s (NIST) CHIPS Research and Development Office (CHIPS R&D) is to accelerate the development and commercial deployment of foundational semiconductor technologies by establishing, connecting, and providing access to domestic research efforts, tools, resources, workers, and facilities. CHIPS R&D aims to achieve the following goals by 2030:

• U.S. Technology Leadership: The United States improves its capacity to invent, develop, prototype, manufacture, and deploy the foundational semiconductor technologies of the future.

• Accelerated Ideas to Market: The best ideas achieve commercial scale as quickly and cost effectively as possible.

• Robust Semiconductor Workforce: Inventors, designers, researchers, developers, engineers, technicians, and staff sustainably meet evolving domestic government and commercial sector needs.

1 DOC CHIPS activities were authorized by Title XCIX—Creating Helpful Incentives to Produce Semiconductors for America of the William M. (Mac) Thornberry National Defense Authorization Act for Fiscal Year 2021 (Pub. L. 116-283, often referred to as the CHIPS Act).

https://www.dol.gov/general/good-jobs/principles

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1.1.2 NAPMP Objectives

NAPMP seeks to drive U.S. leadership in advanced packaging and provide the technology and skilled workforce needed for packaging manufacturing in the United States. Within a decade, NAPMP-funded activities, coupled with CHIPS manufacturing incentives, will establish a vibrant, self-sustaining, profitable, domestic advanced packaging industry where advanced-node chips manufactured in the United States and abroad can be packaged in appropriate volumes within the United States and innovative designs and architectures are enabled through leading-edge packaging capabilities. In combination with other CHIPS for America education and workforce efforts, NAPMP-funded activities produce the diverse and capable workforce needed for the success of the domestic packaging sector.

As the global microelectronics industry continues to make an expensive and technologically challenging, yet essential, leap from conventional packaging to advanced packaging, the United States has a once-in-a-generation opportunity to establish a competitive advanced packaging sector. To promote the emergence of domestic packaging innovations, NAPMP will invest in four hardware-related development areas:

• Materials and Substrates

• Equipment, Tools, and Processes

• Power Delivery and Thermal Management

• Photonics and Connectors

Additionally, NAPMP will invest in two interrelated areas that address the chiplet and co-design ecosystem and in an Advanced Packaging Piloting Facility (APPF), where successful R&D efforts will be further developed and validated for scaled transition to U.S.

manufacturing.

1.1.3 NAPMP Materials and Substrates NOFO Objectives

This NOFO, the first under the NAPMP, seeks applications for activities that will achieve the following objectives:

(1) Accelerate domestic R&D and innovation in advanced packaging materials and substrates;

(2) Transition domestic materials and substrate innovation into U.S. manufacturing, such that these technologies are available to U.S. manufacturers and customers, including to significantly benefit U.S. economic and national security;

(3) Support the establishment of a robust, sustainable, domestic capacity for advanced packaging materials and substrate R&D, prototyping, commercialization, and manufacturing; and

(4) Promote a skilled and diverse pipeline of workers for a sustainable domestic substrate manufacturing sector.

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1.2 DEFINITIONS

This section provides definitions for purposes of this NOFO.

• Basic and Applied Research – Basic research refers to experimental or theoretical work undertaken primarily to acquire new knowledge of the underlying foundations of phenomena and observable facts. Basic research may include activities with broad or general applications in mind, such as the study of how plant genomes change, but should exclude research directed towards a specific application or requirement, such as the optimization of the genome of a specific crop species. For the purpose of this NOFO, the term "applied research" refers to original investigation undertaken in order to acquire new knowledge. Applied research is, however, directed primarily towards a specific practical aim or objective.2

• Demonstration device – The Integration of dielets onto the substrate to create a functional and testable device. The design of a demonstration device may include (but is not limited to) embedding of passive and active components in/on the substrate, small testable dielet assemblies on the substrate at pitches relevant to project technical targets, and dielet assemblies on both sides of the substrate.

• Dielet – A small block of semiconducting material carrying an integrated circuit with reduced size and potentially limited or focused functionality in comparison to a conventional scale semiconductor die.

• Milestones – Actions or events marking a significant change or stage in developments in a project.

• Phase-specific Target –Includes both technical and non-technical targets, derived from applicant-specified milestones, to inform go/revise/no-go points for the transition from one project phase to the next. Phase-specific technical targets focus on measurable progress toward Project-Level Technical Targets. Phase-specific non-technical targets focus on measurable progress towards the applicant’s Education and Workforce Development plan and Commercial Viability and Domestic Production Plan. CHIPS R&D may identify additional phase-specific targets, including to address other applicant-defined plans.

• Project – All activities funded under a single award made under this NOFO, including but not limited to all planning and management, basic and applied research, substrate and demonstration device development and production, commercial viability and domestic production preparation, integrated workforce education and training, and pilot-level substrate production activities.

• Project-level Technical Target – Specific technical advances in materials and substrate technologies to be achieved by the end of the project (See Section 1.5).

2 The definitions of basic and applied research are taken from Office of Management and Budget Circular A-11 (2023).

https://www.whitehouse.gov/wp-content/uploads/2018/06/a11.pdf https://www.whitehouse.gov/wp-content/uploads/2018/06/a11.pdf

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• Project-level Non-Technical Target – Specific non-technical targets in either education and workforce development or commercial viability and domestic production to be achieved by the end of the project (See Section 1.6).

• Semiconductor – An integrated electronic device or system, most commonly manufactured using materials such as, but not limited to, silicon, silicon carbide, or III-V compounds, and processes such as, but not limited to, lithography, deposition, and etching. Such devices and systems include but are not limited to analog and digital electronics, power electronics, and photonics, for memory, processing, sensing, actuation, and communications applications.

• Substrate – The foundation or supporting base on which or within which the elements of a semiconductor device are fabricated or attached.3

• Substrate material – The class of materials from which a substrate is made. This NOFO focuses on organic, glass, and semiconductor-based (e.g., silicon-based) classes of materials.

• Substrate sample – Samples provided to CHIPS R&D or to an independent evaluator along with relevant documentation, including process assumptions, design manual, process design kit (PDK, compatible with NAPMP-specified formats), reliability criteria, and electrical specifications for purposes of evaluation of progress toward phase-specific technical targets.

1.3 BACKGROUND

Emerging technologies like artificial intelligence, advanced telecommunications, biomedical devices, and autonomous vehicles require leap-ahead advances in microelectronics capabilities. In the past, the semiconductor industry has largely addressed performance needs by increasing the number and density of transistors on a chip, a process known as miniaturization. However, the previous pace of miniaturization, as expressed by Moore’s Law, is slowing and cannot alone provide the performance improvements needed for emerging microelectronics technologies. Improving all aspects of system performance to support the breadth of new semiconductor applications will require advanced packaging.

Semiconductor packaging serves two general purposes. One is to protect the chip mechanically, thermally, and environmentally. The other is to enable reliable inter-chip communication and data processing, power delivery, and a stable test and system integration platform. Advanced packaging and related capabilities, such as heterogeneous integration, encompass the need to integrate multi-component-assemblies with large numbers of interconnects to achieve a degree of integration that blurs the line between chip and package. The ability to “scale-down and scale-out” will be critical to advanced

3 Derived from the JEDEC general dictionary at https://www.jedec.org/standards-documents/dictionary/terms/substrate-semiconductor-device-1-general# https://www.jedec.org/standards-documents/dictionary/terms/substrate-semiconductor-device-1-general https://www.jedec.org/standards-documents/dictionary/terms/substrate-semiconductor-device-1-general

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Advanced packaging allows semiconductor manufacturers to make improvements in device performance and function and to shorten time to market through enabling versatile use of components. Additional benefits include a reduced physical footprint, lower power, increased chip reuse, improved security, and potentially decreased costs, allowing for more diverse and customizable manufacturing lots.

Currently, the vast majority of advanced packaging manufacturing capacity resides in Asia.4 As the CHIPS for America program invests in leading-edge semiconductor design and fabrication, the United States will also need a cost effective and efficient domestic advanced packaging capability to enable semiconductors made in the United States to be packaged in the United States. The United States will need this capability to sustain its global competitiveness and to maintain supply chain security and resilience.

Materials and substrates are foundational to advanced packaging. Moreover, materials and substrates R&D, particularly applied R&D, is critical to expanding the U.S. packaging ecosystem.

1.4 FUNDING OPPORTUNITY DETAILED DESCRIPTION

1.4.1 Project Activities

Project activities are expected to include, but not necessarily be limited to, basic and applied research, substrate and demonstration device development and production, commercial viability and domestic production preparation, integrated education and workforce development and pilot-level substrate production.

CHIPS R&D encourages collaborative proposals under this NOFO. Though not required, CHIPS R&D expects that applicants assembling teams (comprising one or more subrecipients and potentially unfunded collaborators) may be best suited to collectively provide the full range of expertise and capabilities needed to achieve the program objectives, including the proposed project-level targets. All subrecipients must meet the applicant eligibility requirements stated in Section 3.1.

1.4.2 Project Structure

Applications under this NOFO must describe projects that, consistent with the objectives under Section 1.1.3:

4 North American Advanced Packaging Ecosystem Gap Assessment — Critical Systems, Capability, Capacity

Analysis and Recommendations IPC Industry Research Report — November 2021

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1. Focus on one or more of the Technical Areas described in Section 1.4.3;

2. Propose achieving specific Project-level Technical Targets and Project-level Non-

Technical Targets, as described in Sections 1.5 and 1.6;

3. Define milestones marking measurable progress toward those targets, as described in Section 1.6.3;

4. Provide for supplying substrate samples and demonstration devices to CHIPS R&D and to other entities, as described in Section 1.7 and 1.8;

5. Sub-divide project activities into four phases, with each phase ranging in length from 3 to 18 months, as described in Section 1.8;

6. Are designed to achieve pilot-scale production of new substrates in Phase 4 (see

Section 1.8.4); and

7. Are structured around a period of performance (PoP) not to exceed five years.

1.4.3 Technical Areas

This NOFO seeks applications relevant to one or more of the following technical areas:

Technical area 1 (TA1), focused on organic materials and substrates (including fan-out);

technical area 2 (TA2), focused on glass materials and substrates; and technical area 3 (TA3), focused on semiconductor-based substrates. Applicants may address one or more technical areas in a single proposal. The focus in all technical areas is to achieve the objectives of this NOFO (See Section 1.1.3), including by advancing U.S. leadership in “scale-down and scale-out" (See Section 1.3), driving the development of new substrate industry solutions, and demonstrating manufacturability for future sustainable domestic production. Composite substrates using fan out wafer level packaging, including substrates for flexible and biomedical applications, are in scope for this NOFO. Projects involving traditional boards, silicon or glass interposers, and small area substrates, are not in scope for this NOFO.

1.5 PROJECT-LEVEL TECHNICAL TARGETS

Project-Level Technical Targets set out the specific technical advances to be achieved by the end of the project. These targets comprise two categories: CHIPS R&D-specified Technical Targets and Embedded Substrate Features.

1.5.1 CHIPS R&D-specified Technical Targets

Table 2 establishes a set of ten technical target categories and associated technical targets, selected by CHIPS R&D for their potential to improve the performance, manufacturability, and cost effectiveness of advanced substrates and associated manufacturing processes, among other factors. In some but not all cases, CHIPS R&D-specified Technical Targets differ across TA1, TA2, and TA3.

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Applicants must describe, for each of the CHIPS R&D-specified Technical Targets relevant to their selected technical area(s), whether they expect to:

(1) exceed the target;

(2) meet the target;

(3) partially meet the target; or

(4) not need to meet the target.

Applicants may propose additional Project-Level Technical Targets in addition to the CHIPS R&D-specified Technical Targets described in Table 2.

Technical targets for substrate wiring, via pitches, and number of levels on both sides of the substrate are expected to be aggressive and the substrate is expected to be compatible with direct attach at fine pitch of advanced node CMOS, legacy nodes, and non-silicon dielets. In cases where the applicant does not intend to meet or exceed a technical target in Table 2 and/or opts to include additional technical targets, the applicant should carefully explain how their proposed approach nonetheless represents a significant technical advance relative to the global state of the art and will accomplish the CHIPS R&D mission and goals (See Section 1.1.1) and the specific objectives of this NOFO as described in Section 1.1.3.

Table 2: CHIPS R&D-specified Technical Targets

Technical Target Category

CHIPS R&D-specified Technical Targets

TA 1

(Organic)

TA 2

(Glass)

TA3

(Semiconductor-Based)

1. Minimum Line Width, Spacing, and Pitch

1 µm line width, 1 µm line spacing, 2 µm pitch

0.5 µm line width, 0.5 µm line spacing, 1 µm pitch

0.25 µm line width, 0.25 µm line spacing, 0.5 µm pitch

2. Coplanarity at Die

Attach (Bonding Area)

Below 0.5 µm over dielet area, where dielet area can vary between 1 mm x 1 mm to 10 mm x 10 mm

Below 0.5 µm over dielet area, where dielet area can vary between 1 mm x 1 mm to 10 mm x 10 mm

Below 0.5 µm over dielet area, where dielet area can vary between 1 mm x 1 mm to 10 mm x 10 mm

3. Interlevel via diameter 1 µm 0.5 µm 0.25 µm

4. Through substrate via diameter

Less than 100 µm Less than 100 µm Less than 100 µm

5. Max wire thickness Equal to wiring pitch Equal to wiring pitch Equal to wiring pitch

6. Max number of

Layers (hierarchical) 10+10 (side 1 + side 2), or 15 single sided for Fan Out wafer level packaging

10+10 (side 1 + side 2)

15+15 (side 1 + side 2)

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7. Effective coefficient of thermal expansion (CTE) of the multilayer stack

6 to 10 parts per million (ppm) -77 °C to 350 °C

6 to 10 parts per million (ppm) -77 °C to 350 °C

6 to 10 parts per million (ppm) -77 °C to 350 °C

8. Max substrate size 500 mm x 500 mm 500 mm x 500 mm or 300 mm diameter

210 mm x 210 mm or 300 mm diameter

9. Max thickness 3 mm 2 mm 1 mm

10. Warpage

Should be consistent with lithographic requirements for specified minimum line width and spacing

11. Applicant-Defined Target(s)

If consistent with the objectives of this NOFO, the Applicant may propose one or more additional technical targets, such as targets addressing environmental sustainability.

1.5.2 Embedded Substrate Features

Advanced substrates may include one or more passive or active components embedded in the substrate for enhanced functionality. For all technical areas, applicants are strongly encouraged to consider providing additional embedded substrate features, including active and passive devices, that may advance / enhance U.S. leadership in substrate offerings.

Examples include, but are not limited to, the following:

• Advanced voltage regulation structures

• Advanced RF antenna structures

• Advanced substrate thermal solutions (e.g., substrate heat pipes and/or thermal vias)

• Advanced high density decoupling capacitors

• Substrate inductor or resistor structures

• Cross substrate waveguides and/or TLVs (Through Light Vias)

• Substrate trackability / traceability structures or substrate tags

• Substrate radiation shielding structures

• Substrate cavity, curvature, or geometric flexibility provisions, or biomedical applications.

1.6 PROJECT-LEVEL NON-TECHNICAL TARGETS

1.6.1 Education and Workforce Development (EWD) Targets

NAPMP investments under this NOFO are intended to create innovation-driven domestic substrate manufacturing capability, which requires fostering a diverse and capable domestic workforce with access to good jobs, such as those consistent with the Good Jobs Principles. The combination of expertise, facilities, and equipment required to meet the technical targets defined in this NOFO provide exceptional opportunities for tailored EWD programs.

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Applicants must provide an EWD plan that leverages capabilities supported through the proposed project to address domestic advanced packaging workforce needs, including educational opportunities arising from engaging students in research. CHIPS R&D encourages applicants to, in providing an EWD plan, describe any efforts to attract and retain a diverse student and trainee population and to demonstrate that the EWD efforts are worker centered, industry-aligned, and promote high-quality jobs.

Examples of relevant activities in an EWD plan may, but are not required, to include paid research internships and fellowships focused on project activities, paid research experiences for undergraduates, and training programs that take advantage of the project’s facilities, including in-person and virtual programs, partnerships with employers, labor, and the public workforce system, as well as any other institutions key to the delivery of quality employment and training pathways, such as educational institutions, government agencies, industry organizations, and programs focused on training for underserved communities, as defined by Executive Order 13985, Advancing Racial Equity and Support for Underserved Communities Through the Federal Government (Jan. 20, 2021) and Executive Order 14091, Further Advancing Racial Equity and Support for Underserved Communities Through the Federal Government (Feb. 16, 2023). Applicants must propose SMART (Specific, Measurable, Achievable, Relevant, and Time-Bound) EWD targets, such as the number of students trained or engaged in research and subsequently placed in good jobs in the domestic semiconductor industry, to be achieved under the EWD plan.

Educational and workforce activities not unique to project capabilities, such as developing general curriculum or generic training program design, will not be funded under this

NOFO.

1.6.2 Commercial Viability and Domestic Production (CVDP) Targets

Consistent with promoting a robust, sustainable domestic capacity for substrate R&D, prototyping, and production, and in keeping with the provisions of Executive Order 14104 and the CHIPS Act domestic production requirements (15 U.S.C. §4656(g)), CHIPS R&D requires applicants to develop and provide a Commercial Viability and Domestic Production Plan describing activities to be funded as part of the project. The CVDP plan must include a realistic business model for the funded innovations (e.g., manufactured substrates), include a technology transition plan, and describe pathways to benefitting national and economic security, such as through the domestic availability of the technology and successful adoption by commercial or defense partners. Applicants should propose measurable CVDP targets that demonstrate the viability of the proposed business model and of domestic production. Where relevant, CVDP milestones should complement technical milestones.

Strong applications will present evidence of existing or potential demand for the funded innovations; identify existing or potential customers, or categories of customers, at https://www.govinfo.gov/content/pkg/FR-2021-01-25/pdf/2021-01753.pdf https://www.govinfo.gov/content/pkg/FR-2023-02-22/pdf/2023-03779.pdf https://www.federalregister.gov/documents/2023/08/02/2023-16636/federal-research-and-development-in-support-of-domestic-manufacturing-and-united-states-jobs

17 | P a g e volumes necessary for commercial viability; provide an initial assessment of marketability in terms of cost and value proposition that can be updated as the project advances;

describe existing or potential competitors and competing technologies; and demonstrate the potential to attract private capital, such as venture capital.

CHIPS R&D strongly encourages applicants to identify approaches to maximizing market advantages of the funded innovation, such as by reducing manufacturing costs and improving yields (e.g., optimizing process times and achieving economies of scale through increasing volume). Other approaches could include addressing performance, availability, conformance to technical standards, and environmental sustainability.

For the purposes of 15 USC §4656(g) and the CVDP, “production” includes the manufacture, integration, assembly, testing, and packaging of semiconductor substrates and substrate materials. CHIPS R&D does not require the covered “production” to occur exclusively within the United States. However, applicants that are unable to conduct certain “production” activities in the United States should explain, to the extent practicable at the current level of technology development, why such production may not be possible, considering the following factors:

• The availability or lack of availability of domestic production capabilities, which may consider:

o Planned or previous efforts made to locate, develop, or contract for the production of the CHIPS R&D-funded technology, or relevant similar technologies, in the United States;

o Access to resources and other material inputs required for production;

o The expected additional product development time or cost required to make

U.S. production of the CHIPS R&D-funded technology commercially feasible;

• The relative costs of domestic versus foreign production of the CHIPS R&D-funded technology, at relevant production volumes;

• Commercial adoption risks and benefits, such as o Risks to the market acceptance and to the value proposition for the CHIPS-funded technology, resulting from U.S. production;

o Expected commercial, economic, or national security benefits to the United States resulting from distributed production among U.S. and overseas sites;

• Any other factors that important to the success of the CHIPS R&D-funded technology.

1.6.3 Milestones and Phase-Specific Targets

Applicants should propose milestones that represent measurable steps toward achieving the applicant’s Project-Level Technical Targets. Applicants should also propose milestones that represent measurable steps toward achieving the applicant’s Project-level EWD Targets and CVDP Targets, as described in Sections 1.6.1 and 1.6.2. Applicants may also propose additional non-technical milestones.

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Milestones for technical targets, EWD plan, and CVDP targets should be SMART (Specific, Measurable, Achievable, Relevant, and Time-Bound) and suitable for validation by the applicant, CHIPS R&D staff, independent expert technology evaluators, or a combination of these entities, as appropriate.

CVDP milestones should complement the technical milestones. For example, technical milestones should, as appropriate, inform CVDP targets and milestones such as manufacturing time, cost, performance, and projected customer demand. Additional CVDP milestones may include measurable progress in business plan development, customer identification, investor commitments, technology licensing agreements, and enabling manufacturing in the United States.

If an application stands a reasonable chance of being funded, CHIPS R&D may negotiate with the applicant to 1) refine the proposed milestones, and 2) define phase-specific targets derived from the proposed milestones. These phase-specific targets will inform go/revise/no-go points for the transition from one project phase to the next.

1.7 DEMONSTRATION DEVICES

Applicants should describe the design of a demonstration device appropriate to the intended substrate design and suitable for demonstrating the ability to successfully integrate the substrate into a simple, functional, and testable package. The design of the demonstration device may include (but is not limited to) embedding of passive and active components in/on the substrate, small testable dielet assemblies on the substrate at pitches relevant to project technical targets, and dielet assemblies on both sides of the substrate. The design of the device should be suitable for evaluation by an independent evaluator of the substrate’s intended functionality, as set out in the application.

1.8 PROJECT PHASES

Applicants must propose a step-by-step technical plan (as defined in Section 4.6.1), for achieving both Project-Level Technical Targets and Project-Level Non-Technical Targets (i.e., EWD and CVDP targets). The technical plan must propose 4 phases of work, with each phase ranging in length from 3 months to 18 months. The project’s total proposed period of performance must not exceed five years.

A hypothetical project timeline with the required four phases is shown in Figure 1 below.

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Figure 1: Hypothetical Project Timeline

1.8.1 Phase 1

CHIPS R&D expects activities in Phase 1 to include, as necessary, acquiring any required equipment and staff, demonstrating the capability for prototype-level substrate production, gathering appropriate data to refine CVDP plans, conducting initial education/workforce outreach efforts, and similar activities.

Phase 1 technical milestones should define progress toward achieving prototype-level substrate production. Phase 1 commercial viability and domestic production milestones should include, for example, progress in refining the CVDP plan, including gathering any relevant data.

Award recipients will be expected to deliver to CHIPS R&D or independent evaluators as applicable—

(1) Substrate samples for evaluation, including relevant documentation such as process assumptions, design manuals, process design kits (PDK), reliability criteria, and electrical specifications, each compatible with formats specified by CHIPS R&D during negotiation and with appropriate licensing provisions to protect IP rights;

(2) A refined CVDP plan; and

(3) Evidence of successful EWD outreach efforts.

Phase-specific targets marking go/revise/no-go decision points for transition from Phase 1 to Phase 2 will be finalized at the time of award.

1.8.2 Phase 2

CHIPS R&D expects activities in Phase 2 to include, for example, basic and applied research, innovations in process engineering, development and application of advanced metrology and testing capabilities, refining the CVDP plan based on technical progress, and implementing the EWD plan.

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Phase 2 technical milestones should define progress toward achieving Project-level technical targets. Phase 2 CVDP milestones should leverage research and engineering progress to inform refinement and implementation of the CVDP plan and demonstrate progress towards the relevant project-level non-technical targets. Phase 2 EWD milestones should include implementing relevant programs, collecting data for assessing success metrics, and demonstrating progress towards the relevant project-level non-technical targets.

Award recipients will be expected to deliver to CHIPS R&D or to independent expert evaluators as applicable—

(1) Substrate samples for evaluation, including relevant documentation such as process assumptions, design manuals, process design kits (PDK), reliability criteria, and electrical specifications, each compatible with formats specified by CHIPS R&D during negotiation and with appropriate licensing provisions to protect IP rights;

(2) A refined CVDP plan and a detailed description of progress against the plan; and

(3) A refined EWD plan and a detailed description of progress against the plan.

Phase-specific targets marking go/revise/no-go decision points for transition from Phase 2 to Phase 3 will be finalized at the time of award.

1.8.3 Phase 3

CHIPS R&D expects activities in Phase 3 to include, for example, continued work on substrate development, additional basic and applied R&D on substrate integration and integration process engineering, development of device-level metrology and testing capabilities, refining and progressing against the CVDP plan, and continued progress against the EWD plan.

Phase 3 technical milestones should focus on achieving the project-level technical targets.

Phase 3 CVDP milestones should leverage research and engineering progress to inform refinement and implementation of the CVDP plan and demonstrate progress towards the relevant project-level non-technical targets. Phase 3 EWD should include implementing relevant programs, collecting data and success metrics, and demonstrating progress towards relevant project-level non-technical targets.

Award recipients will be expected to deliver to CHIPS R&D or to independent evaluators as applicable—

(1) Substrate samples for evaluation, including relevant documentation such as process assumptions, design manuals, process design kits (PDK, compatible with NAPMP-specified formats and with appropriate licensing provisions to protect IP rights), reliability criteria, and electrical specifications;

(2) Demonstration devices in lots sufficient for independent evaluation (approximately 25 per lot);

(3) A refined CVDP plan and evidence of progress against the plan; and

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(4) Data-driven evidence of progress against the EWD plan.

Phase-specific targets marking go/revise/no-go decision points for transition from Phase 3 to Phase 4 will be defined at the time of award.

1.8.4 Phase 4

CHIPS R&D expects Phase 4 activities to include—

(1) Scaling up from prototype-level substrate production (i.e., lots in the range of 25 substrate samples) to pilot-level substrate production (i.e., lots in the range of 250 substrate samples);

(2) Reimbursable provision of advanced substrates emerging from work in previous phases for use in other research projects designated by CHIPS R&D;

(3) Refining and implementing the CVDP plan based on initial pilot-level production experience; and

(4) A data-enabled analysis of EWD program progress.

Phase 4 technical milestones should focus on steps toward pilot-level production. Phase 4 CVDP milestones should reflect lessons learned in the process of scaling to pilot level substrate production. Phase 4 EWD should focus on data gathering and analysis of funded EWD programs.

1.8.5 Provision of Substrates for CHIPS R&D-Designated Research Projects

During Phase 4, CHIPS R&D aims to provide substrates developed under this NOFO to research projects in other areas of packaging research that would benefit from access to advanced substrates. Examples of these other research areas include new equipment, tools, and processes; innovation in power delivery and thermal management; novel chiplet and dielet technologies; and wired, radio frequency, and optical connectors. Examples of research projects include those associated with the APPF, the NSTC, Manufacturing USA Institutes, or other Federally funded research programs.

CHIPS R&D will expect recipients to deliver, along with substrate samples for use by other research projects, tools and documentation including process assumptions, design manuals, process design kits (PDK, compatible with NAPMP-specified format), and electrical specifications. CHIPS R&D will work with award recipients to ensure appropriate protections for the recipient’s IP rights (see Section 2.8). For Phase 4 budgeting purposes, applicants should plan for a minimum of 100 substrate samples and a maximum of 1,000.

NIST will allow award recipients to recover costs for producing these substrates for CHIPS R&D-designated research projects.

Options for providing substrates are direct, reimbursable provision of substrates by the applicant; licensing to other NAPMP-approved U.S.-based entities with capacity for

22 | P a g e reimbursable production of substrates at pilot scale; or installing manufacturing capability in an NAPMP-funded facility, such as the planned APPF.

1.9 BROADER IMPACTS

CHIPS R&D is committed to building strong communities that share in the prosperity of the semiconductor industry, as well as ensuring that taxpayer investments maximize benefits for the U.S. economy. CHIPS R&D also strongly supports inclusion, diversity, equity, and access, and firmly believes that the semiconductor industry cannot succeed unless all Americans have an opportunity to participate, including individuals from underserved communities. In its evaluation and selection processes, CHIPS R&D will consider how projects will create broader impacts across the following dimensions:

1.9.1 Commitments to Future Investment

Ensuring U.S. leadership in semiconductor technology and the security and resilience of the domestic semiconductor supply chain will require sustained capital, R&D, and workforce investments. CHIPS R&D encourages applications that can induce larger-scale, private domestic investments into domestic prototyping and manufacturing facilities and equipment that would not have occurred absent an award under this NOFO. CHIPS R&D also encourages applications that demonstrate collaborations across the supply chain to clarify future demand, improve transparency and security, mitigate the risk of future chip shortages or oversupply, and support a more productive, efficient, and self-sustaining semiconductor ecosystem. In selecting applications for award, CHIPS R&D will therefore prioritize applications that include credible commitments, from the applicant or other entities participating in the project, to investing in R&D or semiconductor substrate manufacturing in the United States, as evidenced, for example, by letters of commitment or interest.

1.9.2 Support for other R&D Programs

Strengthening the role of the United States in semiconductor technology requires a robust and collaborative innovation ecosystem. Applicants should help ensure that this innovation ecosystem – which is critical to the semiconductor industry’s long-term success – can flourish. CHIPS R&D will favorably consider applications that demonstrate a commitment to participating in the NSTC, the APPF, and if applicable, other semiconductor-related R&D initiatives established by the CHIPS Act5 or CHIPS and Science Act (P.L. 117-167). These initiatives may include but are not limited to the NIST Manufacturing USA Institute(s) focused on semiconductor manufacturing; NIST Metrology research for microelectronics;

5 For the purposes of this NOFO, the term “CHIPS Act” refers to Title XCIX of the William M. (Mac) Thornberry National Defense Authorization Act for Fiscal Year 2021, as amended (United States Code Title 15 Chapter 72A).

23 | P a g e the NSTC Workforce Center of Excellence; the Department of Defense (DoD) National Network for Microelectronics Research and Development, also known as the…