Attachment A - 4H-SiC Silicon Carbide (SiC) Integrated Circuit Processing On 100 mm Diameter SiC Wafers.pdf

STATEMENT OF WORK (SOW)

TITLE: 4H-SiC SILICON CARBIDE (SiC) INTEGRATED CIRCUIT PROCESSING ON 100 mm DIAMETER SiC WAFERS

1. BACKGROUND

The scope of this work is described online at https://www1.grc.nasa.gov/research-and-engineering/silicon-carbide-electronics-and-sensors/. NASA is developing extreme environment-durable integrated circuits (ICs) to advance the capabilities of a variety of planned NASA missions including Venus landers. Towards this end, NASA Glenn Research Center is seeking prototype fabrication of increasingly capable silicon carbide (SiC) junction field effect transistor (JFET) ICs. In particular, this procurement is seeking fabrication of particular integrated SiC device structures (JFETs and resistors) via a particular fabrication process flow to the following specifications on NASA-provided 100 mm diameter 4H-SiC epilayered wafers using NASA-provided device-layout design files.

2. SCOPE

This procurement is seeking fabrication of specific integrated SiC device structures (JFETs and resistors) via a particular fabrication process flow designated as the “Gen. 12b” prototype wafer fabrication run to the following specifications on NASA-provided 100 mm diameter 4H-SiC epilayered wafers using NASA-provided device-layout design files. After the SiC device structures of the following statement of work are completed, the wafers will be delivered back to NASA for additional processing of bondpads and the back-side contact that will complete the formation of integrated circuits needed for NASA missions. The resulting IC chips produced will be used to implement prototype extreme-environment electronic systems and demonstrations. A technical primer (overview) of the IC technology being implemented is online at https://www1.grc.nasa.gov/research-and-engineering/silicon-carbide-electronics-and-sensors/jfet-ic-tech-guide/ . The posted “IC. Gen. 12” mask layout design rules and related IC Gen. 12 documentation within this website is to be used for this prototype wafer fabrication run.

3. CONTRACT DESCRIPTION AND REQUIREMENTS

In accordance with the following specifications, including semiconductor microfabrication process flow and device structure cross-sectional diagrams/depictions, the Contractor shall fabricate and deliver to NASA, interconnected 4H-SiC JFET and resistor (JFET-R) device structures arrayed across the silicon-face surface area of five (5) NASA-provided 100 mm diameter 4H-SiC wafers according to NASA design files to be provided to the contractor in Graphic Database System II (GDS) format.

Additional process witness silicon wafers: Blank 100 mm diameter silicon wafers provided/purchased by the contractor shall be included in certain (NASA-specified) batch processing steps along with the NASA provided 100 mm diameter 4H-SiC epi-wafers as requested/denoted/specified below. Process witness silicon wafers shall be delivered/transferred to NASA for further Governmental examination and use.

The Contractor shall perform the following fabrication process flow tasks that are illustrated in drawings and descriptions below. Drawings shown in this SOW are depictive representations simplified for purposes of clarity and do not constitute highly accurate depictions of actual device layouts found in NASA-supplied GDS design files.

The 4H-SiC JFET-R device structures delivered to NASA by the contractor shall conform to the salient features shown in the Figure 1 schematic depiction of the (a) cross-section and (b) top view of an example integrated 4H-SiC JFET-R device to be implemented with the NASA-provided 4H-SiC wafer:

(a) Cross-section (b) Layout top view

Figure 1: Simplified schematic illustration detail of example 4H-SiC JFET and resistor (JFET-R) devices as they will be interconnected at the conclusion of all tasks.

The contractor shall fabricate the above depicted device structure using the following sequence order of major semiconductor device processing steps (i.e., “Major Steps”) described and illustrated as follows starting from the Figure 2 simplified schematic depiction of (illustrating a small closeup portion of) the NASA-provided 4H-SiC wafer with epilayers:

Figure 2: Simplified schematic cross-section illustration of epilayer structure on NASA-provided 100 mm diameter 4H-SiC wafers.

The three SiC epilayers present on the NASA-provided silicon-face wafer surface critical to NASA-desired device functionality illustrated in Figure 2 are (from top wafer surface to bottom 4H-SiC wafer substrate) as follows:

p+ Gate Epilayer with initial thickness 200 nanometers (nm) ± 20 nm n Channel Epilayer with initial thickness 0.35 micrometers (µm) ± 0.05 µm p-type Epilayer with initial thickness > 5 µm

The NASA-provided 100 mm diameter 4H-SiC wafers each conform to SEMI specification M55-4-0315 including “major” and “minor” wafer flats corresponding to crystallographic orientations.

After the completion of each major step listed below, the contractor shall E-mail required data/documentation listed in each major step to the NASA Technical Monitor (TM) so that NASA can verify and quantify contractor progress and workmanship during the performance of this Statement of Work. The contractor shall additionally also explicitly note any and all off-nominal observations and processing detected and provide accompanying relevant data. Examples of off-nominal observations include larger than 10% non-uniformities in deposited film thicknesses, or etch depths, de-lamination, buckling, or peeling of metal films, cracking or peeling of dielectric films, etc. in any wafer regions farther than 4 mm from a wafer edge.

Major Step 0, Pre-fabrication activities: The contractor shall conduct the following steps prior to start of device processing initiated at Major Step 1:

A. Conduct review and finalization of CAD layouts provided by NASA, which also include contractor-provided cells such as alignment marks and other process control and monitoring devices/features necessary for successfully contractor processing of the wafers.

B. Conduct non-destructive inspection measurements characterizing particles/defects of all NASA-provided SiC wafers. One such non-destructive inspection shall be conducted using an automated defect inspection tool to produce defect density maps for each NASA provided wafer and particle/defect count vs particle/defect size histograms, that shall be summarized and electronically reported to the NASA TM.

C. Procure the necessary quantity of 100 mm diameter silicon additional process witness wafers.

Major Step 1, p+ gate pattern definition: The contractor shall implement processing consisting of Part A and Part B that results in intermediary device structure depicted in Figure 3 as follows:

Part A: Implement deposition and photolithographic process patterning of a suitable “p+ gate” etch masking material that reproduces the “p layer” pattern in the NASA-provided GDS design file.

The NASA-provided design file for this p layer pattern has a minimum feature width of 1 μm and minimum feature separation spacing distance of 4 μm, but in limited/small “Process Control Monitor” (PCM) wafer regions smaller features and spacing will be implemented on a best-effort basis. The reproduced and resulting p+ gate etch masking pattern defined onto the wafer shall be aligned with the major wafer flat to within ± 0.5 degree rotational angle and shall not laterally deviate from the NASA-provided design file by more than 0.2 μm for the 3 μm width p+gate finger features patterned onto the wafer. The thickness and composition of this p+ gate mask shall be of durability and thickness that it can remain on the wafer and provide for:

(i) Masking of phosphorous ions implanted during Major Step 2 from penetration into the n channel layer residing beneath p+ gate.

(ii) Complete removal of the p+ gate mask material at the start of Major Step 3.

Part B: Implement plasma-based etch removal of 0.25 µm ± 0.05 µm thickness of SiC (i.e., the entire p+ Gate Epilayer thickness) in regions not covered by the “p layer” p+ gate metal etch mask. This plasma-based etch removal process shall be free of micro-masking resulting in a smooth SiC surface with average roughness less than 15 nm.

The following data/documentation shall be measured and electronically summarized to NASA TM after completion of Major Step 1 and prior to initiation of Major Step 2:

• Optical microscope images clearly showing JFET gate finger patterns and etched SiC surface regions.

Figure 3: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 1 processing.

Major Step 2, Self-aligned n-type ion implantation: The contractor shall ion implant Phosphorus impurities into the patterned (silicon-face) wafer surface at wafer tilt angle of less than 0.5° at an energy of 130 keV and total dose of 7.0e12 cm-2 at a temperature near 25 °C that results in the intermediary device structure schematically depicted in Figure 4.

Figure 4: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 2 processing.

Major Step 3, n mesa pattern definition: The contractor shall implement processing consisting of Parts A, B, and C that results in intermediary device structure depicted in Figure 5 as follows:

Part A: Completely strips/removes the “p+ gate etch mask” material without removing any (< 1 nm) of the 4H-SiC wafer surface.

Part B: Implement deposition and photolithographic process patterning of a suitable n mesa etch masking material that reproduces the “n and p layer” layer pattern in the NASA-provided GDS design file onto the wafer. The NASA-provided CAD file for this n layer pattern has a minimum feature width of 1 μm and a minimum feature separation spacing distance of 4 μm, but in limited/small “Process Control Monitor” (PCM) wafer regions smaller features and spacing will be implemented on a best-effort basis. This n mesa metal etch mask shall be deposited and patterned in a manner that aligns to and covers p+ gate features produced on the wafer during Major Step 1 to within 0.2 μm. The reproduced and resulting “n and p layer” n mesa etch masking pattern defined onto the wafer shall not laterally deviate from the NASA provided design file dimensions by more than 0.2 μm for n mesa features patterned onto the wafer. The thickness and composition of this n etch mask shall be sufficiently durable that it can remain on the wafer and provide for:

(i) Masking of aluminum ions implanted during Major Step 4 from penetration into the underlying n Channel Layer.

(ii) Complete removal of the n and p mesa etch mask material during Major Step 5.

Part C: Implement plasma-based etch removal of the entire n Channel Epilayer thickness in regions not covered by the “n and p layer” etch mask resulting in removal of 0.9 μm ± 0.1 μm of SiC in the etched regions. This plasma-based etch removal process shall be free of micro-masking resulting in a smooth SiC surface with less than 50 nm surface roughness.

completion of Major Step 3 Part A:

• Optical microscope images clearly showing JFET gate finger patterns and etched SiC surface regions.

• Surface profilometer data recorded in SiC wafer central region and wafer near-edge region (1 cm from major wafer flat) showing measured step heights and RMS roughness of p+ gate finger/mask feature compared to etched SiC surface.

In addition, the following data/documentation shall be measured and electronically summarized to NASA TM after completion of Major Step 3 Part C:

• Optical microscope images clearly showing JFET n-mesa patterns and etched SiC surface regions between separate n mesas.

Figure 5: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 3 processing.

Major Step 4, Self-aligned p-type ion implantation: The contractor shall ion implant aluminum impurities into the patterned (silicon-face) wafer surface at wafer tilt angle of less than 0.5° at temperature near 25 °C that results in the intermediary device structure schematically depicted in Figure 6. The three aluminum implant energies with corresponding doses that shall be implanted by the contractor for this step are 150 keV to dose of 6 e17cm-2, 70 keV to dose of 3.6e12cm-2, and 30 keV to dose of 1.6e12cm-2 keV.

Figure 6: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 4 processing.

Major Step 5, Removal of gate and mesa etch masks: The contractor shall employ material-selective etchants to entirely remove the “n and p layer” etch masks without removing any (< 1 nm) of the 4H-SiC wafer surface, resulting in the intermediary device structure schematically depicted in Figure 7.

The following data/documentation shall be measured and electronically summarized to the NASA TM after completion of Major Step 5:

• Optical microscope images clearly showing JFET n mesa patterns and etched SiC surface regions between separate n mesas.

• Surface profilometer data recorded in SiC wafer central region and wafer near-edge region (1 cm from major wafer flat) showing and comparing measured step heights and RMS roughness of n mesa feature, p-gate feature, and etched SiC surface field region.

Figure 7: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 5 processing.

Major Step 6, n+ Contact Implant pattern definition: The contractor shall implement processing consisting of Part A and Part B (whose order of implementation can be interchanged) that results in either of the intermediary device cross-sections depicted in Figure 8(a) or 8(b) as follows:

Part A: Implement deposition and photolithographic process patterning of a suitable “Thick n+ Implant

Mask” that reproduces the “Deep N Well” mask layer pattern in the NASA-provided GDS design file. The NASA-provided design file for this Deep N Well layer has a minimum feature width of 2 μm and a minimum feature separation spacing distance of 3 μm, but in limited/small “Process Control Monitor” (PCM) wafer regions smaller features and spacing will be implemented on a best-effort basis. The reproduced and resulting Thick n+ Implant Mask defined onto the wafer shall not laterally deviate from the NASA-provided design file by more than 0.2 μm of 2 μm x 3 μm n+ Implant Mask features patterned onto the wafer. The thickness and composition of this Thick n+ Implant Mask pattern shall be of durability and thickness that it can provide for:

(i) Complete masking of phosphorous ions implanted at an energy of 180 keV at an implant temperature of at least 700 °C during Major Step 7 from penetration into SiC in regions beneath the thick n+ Implant Mask.

(ii) Complete removal of the thick n+ Implant Mask by NASA following Major Step 7 using wet chemicals without removing any (< 1nm) of SiC.

Part B: Implement a blanket deposition of a “Thin Offset Layer for n+ Implant” of 60 nm ± 10 nm thickness for purposes of achieving a dopant peak at the top SiC crystal surface.

Unless mutually agreed otherwise by NASA, the composition of the materials deposited to accomplish Parts A and B shall be SiO2.

completion of Major Step 6:

• Optical microscope images clearly showing implant mask patterns and their alignment to/within etched SiC JFET mesa features.

• Surface profilometer data recorded in SiC wafer central region and wafer near-edge region (1 cm from major wafer flat) showing measured step heights of implant mask pattern features.

Figure 8: Simplified schematic illustration detail showing (a) & (b) possible cross-sections and (c) layout top view of a device region on a wafer following Major Step 6 processing.

Major Step 7, High temperature phosphorus ion implantation: The contractor shall ion implant phosphorus (31) impurities into the patterned (silicon-face) wafer surface at wafer tilt angle of less than 1° at temperature of at least 700 °C that results in the intermediary device structure schematically depicted in Figure 9. The sequence for this phosphorus ion implantation shall be as follows:

A: The wafer shall be loaded into the ion implanter and positioned for ion implantation.

B: The wafer shall be heated at a thermal ramp-up rate not to exceed 3 °C/minute to the implantation temperature of at least 700 °C.

C: The wafer shall be implanted with phosphorus (31) at an energy of 180 keV to a dose of 1.2e15 cm-2.

D: The wafer shall be implanted with phosphorus (31) at an energy of 130 keV to a dose of 6.0e14 cm-2.

E: The wafer shall be implanted with phosphorus (31) at an energy of 80 keV to a dose of 6.7e14 cm-2.

F: The wafer shall be implanted with phosphorus (31) at an energy of 40 keV to a dose of 3.9e14 cm-2.

Figure 9: Simplified schematic illustration detail showing (a) acceptable cross-section and (c) layout top view of a device region on a wafer following Major Step 7 processing.

Major Step 8, Removal of SiO2 implant mask: The contractor shall implement processing sequentially consisting of Parts A and B that results in intermediary device structure depicted in Figure 10 as follows:

Part A: The contractor shall employ material-selective etchants to entirely remove the Thick Patterned n+

Implant Mask and Thin Offset Layer (both comprised of SiO2 and depicted in Figure 9 prior to their removal) without removing any (< 1 nm) of the 4H-SiC wafer/device surface.

Part B: The contractor shall subsequently “piranha” clean the wafers for no less than 15 minutes followed by thorough deionized water rinse and nitrogen drying (or equivalent spin-rinse-dry process).

Figure 10: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 8 processing.

Major Step 9, Deposit film to protect/preserve SiC surface during subsequent ion implant activation annealing: The contractor shall deposit a film over the entire wafer top surface for the purpose of preserving/protecting the SiC surface integrity/morphology during subsequent Major Step 10 (implant activation anneal). One possible resulting intermediary device structure following Major Step 9 is depicted in Figure 11. However, different implant anneal capping film materials and thicknesses (mutually agreed by NASA) would be acceptable so long as the SiC top surface is sufficiently preserved following Major Steps 10 and 11 and the contactor discloses the composition and thickness of the capping layer employed to NASA. If the capping layer information requested by NASA is considered proprietary, the contractor shall clearly inform/mark the information submitted to NASA as such.

Figure 11: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 9 processing.

Major Step 10, Ion implant activation anneal. The contractor shall perform a thermal anneal to sufficiently electrically activate ion implantations executed during in Major Steps 2, 4, and 7. The activation anneal temperature is 1360 °C for 100 hours in N2.

Major Step 11, Removal of implant anneal cap film: The contractor shall implement processing sequentially consisting of Parts A, B, and C that results in intermediary device structure depicted in Figure 12 as follows:

Part A: The contractor shall employ material-selective etchants to entirely remove the implant anneal cap film without removing any (< 1 nm) of the 4H-SiC wafer/device surface.

Part B: The contractor shall subsequently “piranha” clean the wafers by immersing them in liquid for no less than 15 minutes consisting of mixture of 3 parts sulfuric acid to 1 part hydrogen peroxide.

Part C: The contractor shall thoroughly rinse (in > 10 MOhm-cm deionized water) and nitrogen dry the wafers (or use an equivalent spin-rinse dryer process).

The following data/documentation shall be submitted to NASA TM after completion of Major Step 11:

• Optical microscope images showing a few SiC JFET and resistor mesas.

• Surface profilometer data showing step heights between:

o Field region to n-channel mesa step height o Field region to p-gate mesa step height o N-channel mesa to p-gate mesa step height

Figure 12: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 11 processing.

Major Step 12, Sacrificial thermal oxidation and strip: The contractor shall implement the following processing consisting of Parts A and B below to prepare the wafer for Major Step 13:

Part A: Grow a sacrificial thermal SiO2 layer #1 of 25 nm ± 5 nm in thickness.

Part B: Wet chemical strip entire thermal SiO2 layer #1 using buffered HF acid solution followed by a thorough rinse (in > 10 MOhm-cm deionized water) and a spin-rinse dryer process.

Major Step 13, Final thermal oxidation: The contactor shall Grow high-quality thermal SiO2 layer #2 of, 25 nm ± 5 nm in thickness using oxidation and post-oxidation annealing processes that minimize SiC/SiO2 interface traps and fixed charge density below 2 x 1012 cm-2 that results in intermediary device structure depicted in Figure 13.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 13:

• Optical microscope images showing a few SiC JFET and resistor mesas.

Figure 13: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 12 and 13 processing.

Major Step 14, Deposit first 1.1µm-thick 3-layer dielectric stack: The contactor shall implement further processing consisting of Parts A-C that results in intermediary device structure depicted in Figure 14 as follows:

Part A: The contractor shall deposit 0.5 µm ± 0.05 µm thickness of SiO2 over the entire wafer top surface.

The SiO2 film shall be deposited by Low Pressure Chemical Vapor Deposition (hereafter abbreviated as LPCVD) using tetraethyl orthosilicate (hereafter abbreviated as TEOS) at a deposition temperature of 720 °C. The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part B: The contractor shall deposit 0.1 µm ± 0.01 µm thickness of stoichiometric Si3N4 over the entire wafer top surface. The Si3N4 film shall be deposited by LPCVD at a deposition temperature of 720 °C. The resulting Si3N4 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part C: The contractor shall deposit 0.5 µm ± 0.05 µm thickness of SiO2 over the entire wafer top surface.

The SiO2 film shall be deposited by LPCVD using TEOS at a deposition temperature of 720 °C.

The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Parts A, B, and C above shall be executed during a single continuous run of the LPCVD system, and it is not acceptable for the wafers to be cooled below 720 °C in between execution of each above Parts A-C. A minimum of 5 clean blank silicon process witness wafers shall be included in this LPCVD system run interspersed amongst the NASA-provided 4H-SiC wafers on the LPCVD wafer holder boat.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 14:

• Conduct inspection measurements characterizing particles/defects of at least one of the blank silicon process witness wafer using the automated defect inspection tool. Resulting data from these measurements, including defect density maps and particle/defect count vs particle/defect size histograms, shall be summarized and electronically reported to the NASA TM.

• Conduct film thickness measurements and electronically provide NASA TM with the resulting thickness of the LPCVD film deposited on at least one of the blank silicon process witness wafers.

Figure 14: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 14 processing.

Major Step 15, Photolithography and etching of Via1: The contactor shall implement further processing consisting of Parts A and B that results in intermediary device structure depicted in Figure 15 as follows:

Part A: Implement photolithographic process patterning of a suitable photoresist etch masking material that reproduces the “Via1” layer pattern in the NASA-provided GDS design file onto the wafer.

The NASA-provided design file for this Via1 pattern has a minimum feature width of 3 µm and a minimum feature separation spacing distance of 6 µm. This Via1 etch mask shall be deposited and patterned in a manner that aligns to and covers p+ gate features produced on the wafer to within 0.2 µm. The reproduced and resulting “Via1” etch masking pattern defined onto the wafer shall not laterally deviate from the NASA-provided design file dimensions by more than 0.2 µm for 3 µm x 3 µm Via1 features patterned into the photoresist. The thickness and composition of the photoresist Via1 mask shall be sufficiently durable that it can remain on the wafer and provide for:

(i) Dry etch removal of the entire thickness of dielectrics as specified in Part B.

(ii) Photoresist remaining following dry etch described in Part B is sufficient in thickness and sidewall profile that facilitates liftoff patterning of sputtered Ti + TaSi2 contact plug as specified in Major Step 16.

Part B: Implement etch removal of the first 1.1 µm-thick 3-layer dielectric stack (deposited in Major Step

14) plus removal of entire thickness of high-quality thermal SiO2 layer #3 of 30 nm ± 10 nm (formed in Major Step 13wherein dielectric removal only occurs in those lateral 3 µm x 3 µm regions where patterned photoresist is not residing prior to the start of the dry etch. In each 3 µm x 3 µm region not protected by photoresist, this etch removal of dielectric shall remove all dielectric to form an exposed SiC surface region laterally larger than 1.7 µm x 1.7 µm, but this etch removal of dielectric shall not remove/etch more than 10 nm of depth into the SiC. This etch removal of dielectric shall be implemented by plasma-based dry etching.

Part C: Electrical probing verification of complete removal of SiO2 to expose the 4H-SiC shall be rapidly conducted for each wafer. Probing shall be conducted in ISO 5 or higher clean room environment using tungsten probing tips. Current vs voltage (I-V) measurements of two probe tips being placed laterally near each other touching SiC surface inside at a few locations/vias specified in advance by NASA. All such I-V measurements shall exhibit currents in excess of 100 μA at less than 20 V applied bias in order for that wafer to proceed to Major Step 16 processing. If I-V measurement does not yield satisfactory electrical conduction, the contractor will consult with NASA TM and if NASA requests resume the etch process of Part B for appropriate additional etching time, after which the above electrical probing procedure will then be repeated to electrically ascertain satisfactory dielectric removal to expose bare 4H-SiC surface. A report summarizing these I-V measurements shall be submitted to the NASA TM, but this shall occur after the completion of Major Step 16 to minimize time duration that 4H-SiC surface is exposed to air atmosphere after the completion of Major Step 15.

Figure 15: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 15 processing.

Major Step 16, Deposition of Ti + TaSi2 contact metal: The contactor shall implement further processing consisting of Parts A-D that results in intermediary device structure depicted in Figure 16 as follows:

Part A: The contractor shall load the wafer into an ultrahigh vacuum (UHV) sputter-deposition system equipped with at least two magnetron sputter guns within 24 hours of the completion of Major Step 15. The ultrahigh vacuum chamber shall pump down to vacuum to base pressure less than 5 x 10-7 torr with the wafer at room temperature. The targets and sputter guns shall be preconditioned/pre-sputtered within 12 hours prior to the start of any of the film deposition described in Part B onto the NASA-provided SiC wafers.

Part B: The contractor shall sputter-deposit using Argon a 30 nm ± 2 nm thickness of 99.999% purity titanium (Ti) film across the wafer surface, which shall be immediately followed (within 20 minutes without breaking vacuum) by sputter-deposition using Krypton gas a 130 nm ± 5 nm thickness of TaSi2.

Part C: The contractor shall remove all Ti+TaSi2 metal film that was deposited on top photoresist while leaving in place all Ti+TaSi2 metal film that was deposited into Via1 etched regions by wet acetone solvent dissolving the photoresist to “liftoff” pattern the Ti+TaSi2 metal contact film.

Part D: The contractor shall perform an oxygen (O2) based plasma clean to ensure complete removal of residual photoresist without removal of any depth of metal or oxide films residing on the wafer.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 16:

Figure 16: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 16 processing.

Major Step 17, Deposition of 0.7µm TaSi2 Metal1 film: The contractor shall sputter-deposit 0.7µm ± 0.05µm thickness of TaSi2 using Krypton gas over the entire wafer top surface that results in the intermediary device structure depicted in Figure 17. The targets and sputter guns shall be preconditioned/pre-sputtered within 12 hours prior to the start of any of the film deposition described in Part B onto the NASA-provided SiC wafers. Prior to deposition, the wafer shall be subjected to 300 °C pre-deposition bake for 1 hour under high vacuum and then allowed to cool to a deposition initiation temperature of 60 °C ± 20 °C. The resulting TaSi2 film shall exhibit conformal and continuous coverage over all topographic features up to 2 μm in height across more than 90% of the wafer top surface area.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 17:

Figure 17: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 17 processing.

Major Step 18, Etching of Metal1 pattern: The contactor shall implement further processing consisting of sequential Parts A, B and C that results in intermediary device structure depicted in Figure 18 as follows:

Part A: The contractor shall implement photolithographic process patterning of a suitable photoresist etch masking material that reproduces the “Metal1” layer pattern in the NASA-provided GDS design file onto the wafer. The NASA-provided design file for this Metal1 pattern has a minimum feature width of 6 µm and a minimum feature separation spacing distance of 6 µm. This Metal1 etch mask shall be deposited and patterned in a manner that aligns to and covers p+ gate features produced on the wafer to within 0.2 µm. The reproduced and resulting “Metal1” etch masking pattern defined onto the wafer shall not laterally deviate from the NASA-provided design file dimensions by more than 0.2 µm. The thickness and composition of the photoresist Metal1 mask shall be sufficiently durable that it can remain on the wafer and provide for dry etch removal of the entire thickness of Metal1 film in regions not covered by photoresist during Part B.

Part B: The contractor shall implement plasma-based dry etch removal of the entire 0.7 µm thickness of Metal1 TaSi2 film deposited in Part A across the wafer in those regions where patterned photoresist is not residing prior to the start of the dry etch. In regions not protected by photoresist where the entire thickness TaSi2 is etched, the contractor shall not etch more than 0.2 µm into the underlying SiO2 dielectric film.

Part C: Following completion of the etching in Part B, the contractor shall remove all photoresist masking material from the entire top surface area of the wafer without removal of any depth of metal or oxide films residing on the wafer. The contractor shall perform an O2 plasma clean as the final step in photoresist removal to ensure complete removal of residual photoresist without removal of any depth of metal or oxide films residing on the wafer.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 18:

• Optical microscope images showing a few SiC JFET and resistor mesas.

• Stylus profilometer data showing topographic height of patterned metal edge features both at a wafer center as well as 1 cm from edge of major wafer flat.

• Current vs. Voltage (I-V) probe-test data showing measured current-voltage characteristics of up to 10 NASA-selected diagnostic test devices (including 3-terminal I-V of SiC JFETs and 2-terminal I-V of SiC resistors) on each NASA-provided 4H-SiC wafer. Probing shall be conducted in ISO 5 or higher clean room environment using tungsten probing tips.

Figure 18: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 18 processing.

Major Step 19, Deposit second 1.1µm-thick 3-layer dielectric stack: The contactor shall implement further processing consisting of Parts A-C that results in intermediary device structure depicted in Figure 19 as follows:

Part A: The contractor shall deposit 0.5 µm ± 0.05 µm thickness of SiO2 over the entire wafer top surface.

The SiO2 film shall be deposited by Low Pressure Chemical Vapor Deposition using tetraethyl orthosilicate at a deposition temperature of 720 °C. The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part B: The contractor shall deposit 0.1 µm ± 0.01 µm thickness of stoichiometric Si3N4 over the entire wafer top surface. The Si3N4 film shall be deposited by LPCVD at a deposition temperature of 720 °C. The resulting Si3N4 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part C: The contractor shall deposit 0.5 µm ± 0.05 µm thickness of SiO2 over the entire wafer top surface.

The SiO2 film shall be deposited by LPCVD using TEOS at a deposition temperature of 720 °C.

The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Parts A, B, and C above shall be executed during a single continuous run of the LPCVD system, and it is not acceptable for the wafers to be cooled below 720 °C in between execution of each above Parts A-C.

The 5 silicon process witness wafers that underwent deposition in Major Step 14 shall be included in this LPCVD system run interspersed with the NASA-provided 4H-SiC wafers on the LPCVD wafer holder boat, and at least one new/clean/blank silicon process wafer shall also be included.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 19:

• Optical microscope inspection images showing a few SiC JFET and resistor mesas.

• Conduct inspection measurements characterizing particles/defects of at least one of the blank silicon process witness wafer using an automated defect inspection tool. Resulting data from these measurements, including defect density maps and particle/defect count vs particle/defect size histograms, shall be summarized and electronically reported to the NASA

TM.

• Conduct film thickness measurement and electronically provide NASA TM with the resulting thickness of the LPCVD film deposited on at least one of the new/clean/blank silicon process witness wafers.

Figure 19: Simplified schematic illustration detail showing (a) respective cross-sections and (b) layout top view of a device region on a wafer following Major Step 19 processing.

Major Step 20, Photolithography and etching of Via2: The contactor shall implement further processing consisting of Parts A and B that results in intermediary device structure depicted in Figure 20 as follows:

Part A: Implement photolithographic process patterning of a suitable photoresist etch masking material that reproduces the “Via2” layer pattern in the NASA-provided GDS design file onto the wafer.

The NASA-provided design file for this Via2 pattern has a minimum feature width of 4.5 µm x

4.5 µm. This Via2 etch mask shall be deposited and patterned in a manner that aligns to and covers p+ gate features produced on the wafer to within 0.2 µm. The reproduced and resulting “Via2” etch masking pattern defined onto the wafer shall not laterally deviate from the NASA-provided design file dimensions by more than 0.2 µm for 4.5 µm x 4.5 µm Via2 features patterned into the photoresist. The thickness and composition of the photoresist Via2 mask shall be sufficiently durable that it can remain on the wafer and provide for dry etch removal of the entire thickness of dielectrics as specified in Part B.

Part B: Implement plasma-based dry etch removal of the second 1.1 µm-thick 3-layer dielectric stack (deposited in Major Step 19) dielectric removal only occurs in those lateral 4.5 µm x 4.5 µm regions where patterned photoresist is not residing prior to the start of the dry etch. In each 4.5 µm x 4.5 µm region not protected by photoresist, this etch removal of dielectric shall remove all dielectric to form an exposed TaSi2 Metal1 surface region laterally larger than 3 µm x 3 µm, but this etch removal of dielectric shall not remove/etch more than 0.4 µm of depth into the underlying TaSi2 Metal1.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 20:

• Optical microscope images showing a few SiC JFET and resistor mesas.

• Stylus profilometer data showing topographic height of patterned via edge feature.

• Current vs. Voltage (I-V) probe-test data showing measured current-voltage characteristics of several NASA-selected diagnostic test devices on each wafer. Probing shall be conducted in ISO

5 or higher clean room environment using tungsten probing tips.

Figure 20: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 20 processing.

Major Step 21, Deposition of 0.7 µm TaSi2 Metal2 film: The contractor shall sputter-deposit using Krypton gas 0.7 µm ± 0.05µm thickness of TaSi2 over the entire wafer top surface that results in the intermediary device structure depicted in Figure 21. The targets and sputter guns shall be preconditioned/pre-sputtered within 12 hours prior to the start of any of the film deposition described in Part B onto the NASA-provided SiC wafers. Prior to deposition, the wafer shall be subjected to 300 °C pre-deposition bake for 1 hour under high vacuum and then allowed to cool to a deposition initiation temperature of 60 °C ± 20 °C. The resulting TaSi2 film shall exhibit conformal and continuous coverage over all topographic features up to 2 μm in height across more than 90% of the wafer top surface area.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 21:

Figure 21: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 21 processing.

Major Step 22, Etching of Metal2 pattern: The contactor shall implement further processing consisting of sequential Parts A, B and C that results in intermediary device structure depicted in Figure 22 as follows:

Part A: The contractor shall implement photolithographic process patterning of a suitable photoresist etch masking material that reproduces the “Metal2” layer pattern in the NASA-provided GDS design file onto the wafer. The NASA-provided design file for this Metal2 pattern has a minimum feature width of 6 µm and a minimum feature separation spacing distance of 6 µm. This Metal2 etch mask shall be deposited and patterned in a manner that aligns to and covers p+ gate features produced on the wafer to within 0.2 µm. The reproduced and resulting “Metal2” etch masking pattern defined onto the wafer shall not laterally deviate from the NASA-provided design file dimensions by more than 0.2 µm for 6 µm Metal2 features patterned into the photoresist. The thickness and composition of the photoresist Metal2 mask shall be sufficiently durable that it can remain on the wafer and provide for dry etch removal of the entire thickness of Metal2 film in regions not covered by photoresist during Part B.

Part B: The contractor shall implement plasma-based dry etch removal of the entire 0.7 µm thickness of Metal2 TaSi2 film deposited in Part A across the wafer in those regions where patterned photoresist is not residing prior to the start of the dry etch. In regions not protected by photoresist where the entire thickness Metal2 TaSi2 is etched, the contractor shall not etch more than 0.2 µm into the underlying SiO2 dielectric film.

Part C: Following completion of the etching in Part B, the contractor shall remove all photoresist masking material from the entire top surface area of the wafer without removal of any depth of metal or oxide films residing on the wafer. The contractor shall perform an O2 plasma clean as the final step in photoresist removal to ensure complete removal of residual photoresist without removal of any depth of metal or oxide films residing on the wafer.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 22:

• Optical microscope images showing a few SiC JFET and resistor mesas.

• Stylus profilometer data showing topographic height of patterned metal edge feature.

• Current vs. Voltage (I-V) probe-test data showing measured current-voltage characteristics of up to 10 NASA-selected diagnostic test devices (including 3-terminal I-V of SiC JFETs and 2-terminal I-V of SiC resistors) on each NASA-provided 4H-SiC wafer. Probing shall be conducted in ISO 5 or higher clean room environment using tungsten probing tips.

Figure 22: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 22 processing.

Major Step 23, Deposit third 1.7µm-thick 3-layer dielectric stack: The contactor shall implement further processing consisting of Parts A-C that results in intermediary device structure depicted in Figure 23 as follows:

Part A: The contractor shall deposit 0.8 µm ± 0.08 µm thickness of SiO2 over the entire wafer top surface.

The SiO2 film shall be deposited by Low Pressure Chemical Vapor Deposition using tetraethyl orthosilicate at a deposition temperature of 720 °C. The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part B: The contractor shall deposit 0.1 µm ± 0.01 µm thickness of stoichiometric Si3N4 over the entire wafer top surface. The Si3N4 film shall be deposited by LPCVD at a deposition temperature of 720 °C. The resulting Si3N4 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Part C: The contractor shall deposit 0.8 µm ± 0.08 µm thickness of SiO2 over the entire wafer top surface. The SiO2 film shall be deposited by LPCVD using TEOS at a deposition temperature of 720 °C. The resulting SiO2 film shall have average pinhole density less than 1 cm-2 across more than 90% of the total top wafer surface area.

Parts A, B, and C above shall be executed during a single continuous run of the LPCVD system, and it is not acceptable for the wafers to be cooled below 720 °C in between execution of each above Parts A-C.

The 10 silicon process witness wafers that underwent deposition in Major Steps 14 and 19 shall be included in this LPCVD system run interspersed with the NASA-provided 4H-SiC wafers on the LPCVD wafer holder boat, and at least one new/clean/blank silicon process wafer shall also be included.

The following data/documentation shall be submitted to NASA TM after completion of Major Step 23:

• Conduct inspection measurements characterizing particles/defects of at least one of the blank silicon process witness wafer using automated defect inspection tool. Resulting data from these measurements, including defect density maps and particle/defect count vs particle/defect size histograms, shall be summarized and electronically reported to the NASA TM.

• Conduct film thickness measurements and electronically provide NASA TM with the resulting thickness data of the LPCVD film deposited on at least one of the new/clean/blank silicon process witness wafers.

Figure 23: Simplified schematic illustration detail showing (a) cross-section and (b) layout top view of a device region on a wafer following Major Step 23 processing.

Post-Fabrication Activities:

• Wafer Delivery: Within two weeks of completion of Major Step 23, all NASA-provided SiC wafers as well as all process witness silicon wafers shall be delivered to NASA.

• Final Report: Within one month of completion of Major Step 23, the contractor shall submit an electronic (Word, PowerPoint, or PDF) Final Technical Report adequately summarizing the work conducted under this contract. As a minimum, the report should summarize each major processing step conducted and its outcome and include all measurement data requested and reported to the NASA TM during the work. The Final Report shall also clearly mark/denote any information/data that is considered proprietary.