SVIC_Combined_Salient_Char2.docx

DOCX document 18 KB Posted

Attached to
SV - Integrated Circuits
Solicitation number
W9124Q-16-Q-SVIC
Issued by

About this file

SVIC Salient Specifications

View the file

On GovTribe

Work with this file

  • Download the original file
  • Contacts named in this file
  • Similar government files
  • Ask GovTribe AI about this file

Text version

W9124Q-16-Q-SVIC

Salient Specifications COUNTERFIET AVOIDANCE REQUIREMENT: Potential sources may only include the original manufacturer (Renesas and Microsemi) or their authorized distributors. ONLY the original manufacturer or authorized distributor can provide an authentic Certificate of Conformance and Certificate of Traceability (virtually the pedigree of the part) that deem the component satisfies all the required specifications.

a. Renesas, UPD720101GJ-UEN-A, 144 Pin Plastic LQFP, 620 ea.

The uPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The uPD720101 is integrated 3 host controller cores with PCI interface and USB 2.0 transceivers into a single chip.

uPD720101GJ-UEN-A 144-pin plastic LQFP (Fine pitch) (20 × 20) Lead-free product

• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)

• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a

• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0

• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host controller core for high-speed signaling.

• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.

• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction.

• Configurable number of downstream facing ports (2 to 5)

• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2

• Supports PCI Mobile Design Guide Revision 1.1

• Supports PCI-Bus Power Management Interface Specification release 1.1

• PCI bus bus-master access

• System clock is generated by 30 MHz X’tal or 48 MHz clock input.

− System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see μPD720101 User’s Manual.

• Operational registers direct-mapped to PCI memory space

• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard implementation.

• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.

b. Microsemi, JANTX2N3027, Silicon Controlled Rectifier, 138 ea.

Brief description = Business Sources Sought for the Microsemi JANTX2N3027 (5961-00-333-9602) Silicon Controlled Rectifier Part Number: JANTX2N3027 Mfr Name: Microsemi

CategoryTrigger Devices
Part StatusActive
DescriptionSCR
GenericJANTX2N3027
EU RoHS CompliantNo
Life Cycle StageMature
Life Cycle Code3.98
Availability (YTEOL)4 - 8
Estimated YTEOL5.6
Alert/Prediction Date25-May-2015
DLA QualificationNot Qualified
Trigger Device TypeSCR
Repetitive Peak Off-state Voltage (V)30
Sub CategorySilicon Controlled Rectifiers
On-state Current-Max (mA)500
Holding Current-Max (mA)10
DC Gate Trigger Voltage-Max (V)1.1
Circuit Commutated Turn-off Time-Nom (us)2
Operating Temperature-Min (Cel)-65
Operating Temperature-Max (Cel)150
Terminal FinishTIN LEAD
JESD-609 Codee0
Surface MountNO
DC Gate Trigger Current-Max (mA)1.2
Non-Repetitive Pk On-state Cur (A)5
Leakage Current-Max (mA)0.05
CategorySilicon Controlled Rectifiers
Active Generic1
Active Mfrs1

c. Microsemi, JANTX2N3032, Silicon Controlled Rectifier, 400 ea.

Brief description = Business Sources Sought for the Microsemi JANTX2N3032 (5961-00-153-4656) Silicon Controlled Rectifier Part Number: JANTX2N3032 Mfr Name: Microsemi

CategoryTrigger Devices
Part StatusActive
Description0.785A, 100V, SCR, TO-18
GenericJANTX2N3032
EU RoHS CompliantNo
Life Cycle StageMature
Life Cycle Code3.99
Availability (YTEOL)4 - 8
Estimated YTEOL5.65
Alert/Prediction Date25-May-2015
HTS Code8541.30.00.80
SB Code8541.30.00.80
DLA QualificationNot Qualified
Trigger Device TypeSCR
Number of Elements1
JEDEC-95 CodeTO-18
ConfigurationSingle
Repetitive Peak Off-state Voltage (V)100
JESD-30 CodeO-MBCY-W3
RMS On-state Current-Max (A)0.785
Repetitive Peak Reverse Voltage (V)100
Sub CategorySilicon Controlled Rectifiers
Reference StandardMIL
Package ShapeRound
On-state Current-Max (mA)500
Package Body MaterialMetal
Holding Current-Max (mA)4
Terminal PositionBottom
DC Gate Trigger Voltage-Max (V)0.6
Circuit Commutated Turn-off Time-Nom (us)2
Package StyleCylindrical
Terminal FormWire
Operating Temperature-Min (Cel)65
Number of Terminals3
Operating Temperature-Max (Cel)150
Terminal FinishTin Lead
JESD-609 Codee0
Surface MountNo
DC Gate Trigger Current-Max (mA)0.02
Additional FeatureHigh Reliability
Non-Repetitive Pk On-state Cur (A)5
Leakage Current-Max (mA)0.0001
CategorySilicon Controlled Rectifiers
Active Generic1
Active Mfrs1

COUNTERFIET AVOIDANCE REQUIREMENT: Potential sources may only include the original manufacturer (Renesas and Microsemi) or their authorized distributors. ONLY the original manufacturer or authorized distributor can provide an authentic Certificate of Conformance and Certificate of Traceability (virtually the pedigree of the part) that deem the component satisfies all the required specifications.

File details come from the government source that posted it. Updated .