A02_-_PWS_(Sayma_PCB).DOC

Performance Work Statement (PWS) Sayma version (v) 2.0 Design and Fabrication of Printed Circuit Boards (PCBs) C.1 Background

The Quantum Science Branch (FCDD-RLS-EQ) in the Sensors and Electron Devices Directorate (SEDD) at the Army Research Laboratory (ARL) performs a variety of quantum computing and quantum networking experiments using trapped atomic ion quantum bits (qubits). The complexity of these experiments necessitates substantial automation.

The Advanced Real-Time Infrastructure for Quantum physics (ARTIQ) is an open source operating system (OS) for managing complex automated experiments. Sinara is an ecosystem of printed circuit boards (PCBs) and open standards designed explicitly for the ARTIQ OS that provides functionality including waveform generation, waveform digitization and logical input/output. Sinara specifies standards for clock distribution, data distribution, device interconnect and synchronization.

Hardware and software solutions available in the marketplace do not provide the performance necessary for next-generation quantum information experiments. In particular, there is a need for low-cost, many-channel, phase synchronous waveform generators compatible with ARTIQ and other elements of the Sinara hardware ecosystem. To meet this need ARL supports the development of the Sayma PCB and its integration with the ARTIQ OS. This development will enable quantum computing and networking research conducted by the Quantum Science Branch using trapped atomic ion qubits.

This PWS focuses on the design, assembly and testing of a set of PCBs which together comprise the Deliverables. The system consists of the following PCBs: Sayma Advanced Mezzanine Card (AMC) PCB, Sayma Rear Transition Module (RTM) PCB, BaseMod PCB and Metlino PCB.

Sayma v2.0 is a new revision to an existing open source hardware system, Sayma v1.0 which was developed by Duke University, Oxford University and the University of Maryland in collaboration with scientists at ARL. ARL’s involvement in Sayma v1.0 included development of the software and gateware under contract W911QX17P0075 (2017). Support for Sayma v1.0 is provided in ARTIQ release 4.0:

https://github.com/m-labs/artiq/blob/4.0 The schematics and layout for Sayma v1.0 components are located at the following URL:

https://github.com/sinara-hw/sinara/tree/master/ARTIQ_EE C.2 Objective The Government requires a Contractor with strong familiarity with version 1.0 of the Sayma hardware, ARTIQ, and the Sinara hardware ecosystem to provide engineering support for v2.0 Sayma and Metlino PCBs. This PWS defines a variety of tasks that emphasize design and support for a new revision of the Sayma hardware. The tasks include porting prior work on the v1.0 hardware to the v2.0 hardware.

C.3 Requirements C.3.1 Contractor Qualifications The Contractor shall be capable of meeting the Government’s following requirements to design, assemble and test the necessary PCBs, and shall provide evidence of such capability through past performance:

C.3.1.1 The Contractor shall possess a detailed understanding of the Sayma v1.0 hardware in regards to the schematics, layout, design tradeoffs and flaws. Sayma and Metlino v2.0 are a substantial revision of the v1.0 design that was engineered by Greg Kasprowicz at the Warsaw University of Technology in 2017.

C.3.1.2 The Contractor shall have a demonstrated track record of designing, testing and delivering high-speed digital systems with multiple clock domains. Particular elements of the required background include designs incorporating DDR3 synchronous dynamic random-access memory (SDRAM) to 800 MHz, JESD204b Subclass 2 (greater than > 16 lanes, greater than>5 GHz line rate), Xilinx Kintex Ultrascale field-programmable gate array (FPGA) and Xilinx GTH serial transceivers.

C.3.1.3 The Contractor shall have a demonstrated track record of designing, testing and delivering systems as per C.3.1.2 that also include high-bandwidth analog components. In particular, multi-channel digital to analog converters (DACs) with greater than > one (1) giga-sample per second (GSPS) data rate and JESD204b Subclass 2 synchronization. Designs must have demonstrated cross talk less than -80 decibels (dBc) at greater than or equal to 400 megahertz (MHz) and -60 dBc spurious-free dynamic range (SFDR).

C.3.1.4 The Contractor shall have demonstrated experience with operating and debugging Sinara family hardware with the ARTIQ OS.

C.3.1.5 The Contractor shall have had previous experience working closely with physical scientists as end customers. References may be requested from previous basic science collaboration work.

C.3.1.6 The Contractor shall have previously demonstrated successful implementation of long-term support of an open source project, spanning at least five (5) years.

C.3.2 Technical Requirements Specifications The Contractor shall ensure that the below requirements described in Section 3.3 “Deliverables” meet the following specifications:

C.3.2.1 Definitions and Specifications Note that MicroTCA is an open standard for embedded computing specified by the PCI Industrial Computer Manufacturers Group (PICMG) and PCI is an abbreviation for Peripheral Component Interconnect.

Let TS-MTCA be a MicroTCA crate configured as follows:

· 1 NAT NATIVE-R5 (or -R9)

· 1 (or 2) NAT AC 600D

· 1 NAT-MCH Basic Module v3.5

· Let TS1 be a Sayma test setup consisting of the following

· 1 Sayma AMC+RTM

· Powered by advanced technology eXtended (ATX) connector from benchtop supply

Let TS2 be a Sayma test setup consisting of the following

· Single microTCA chassis configured as TS-MTCA

· 2 Sayma AMC+RTM

· 1 Metlino

· All radio frequency (RF) channels producing 400 MHz sinusoid

· Cards in adjacent slots

Let TS7 be a Sayma test setup consisting of the following

· Single uTCA chassis configured as TS-MTCA

· 6 Sayma AMC+RTM

· 1 Metlino

· All RF channels producing 400 MHz sinusoid

· Cards in adjacent slots

C.3.2.2 Digital Dual Mixer Time Difference (DDMTD) Digital Dual Mixer Time Difference (DDMTD) is the phase detector in the White Rabbit (WR) Phase Lock Loop (PLL) architecture.

C.3.2.3 Data to Analog Converter (DAC) Startup Synchronization

Deterministic phase alignment between DACs on separate Sayma PCBs between power cycles is an important design criterion and should be considered at all stages of design.

Test conditions:

· Smart agile waveform generator (SAWG) output on all channels on two (2) Sayma boards, 400 MHz continuous RF

· Sayma-local transistor-transistor logic (TTL) output at 62.5 MHz

· Use existing ARTIQ real-time input-output (RTIO) infrastructure and TTL PHY

· Laboratory temperature stability +/- 0.5 Celsius (C)

· Cycle crate power 100 times

Target performance:

· ST1: SAWG-SAWG phase alignment error across all power cycles: < 1/f_dac_clk

· ST2: SAWG to TTL alignment error across all power cycles: < 0.5 nanosecond (ns) C.3.2.4 DAC Synchronization Performance

Phase stability between DACs on separate Sayma PCBs is an important design criterion and should be considered at all stages of the design. This assumes that DAC-FPGA synchronization.

Test conditions:

· SAWG output on all channels on two (2) Sayma boards, 400 MHz continuous RF

· Assume laboratory temperature stability +/- 0.5 C

· Duration: 24 hours

Target performance:

· ST3: SAWG-SAWG phase alignment variation less than +/- 0.5 degrees (deg)

· ST4: SAWG-TTL alignment variation less than +/-250 picosecond (ps) C.3.2.5 DAC Noise

Low cross talk between adjacent analog channels on same analog front end (AFE) is an important design criterion and should be considered at all stages of the design (particularly layout).

· Cross talk goal: at 400 MHz < -80 dBc.

Phase noise at 400 MHz (3 dBc margin on AD9154 specification):

· 10 Hz offset, < -94 dBc

· 100 Hz offset, < -103 dBc

· 1000 Hz offset, < -120 dBc

· 10,000 Hz offset, < -126 dBc

Spurs:

· < -60 dBc spurious-free dynamic range (SFDR) across operating range at maximum amplitude

C.3.3 DELIVERABLES

Deliverables shall be provided to ARL according to the following schedule.

If software dependencies are not met by the Delivery Date the Contractor may proceed to ship the HT5 demonstration system (C.3.3.5) without successful completion of the dependent tests ST1, ST2, ST3 and ST4.

If bug fixes are substantial (eg replacing multi-pin SMD), PCBs will be returned to Contractor for repairs. Contractor pays for repair and one-way shipping. Limit to ten (10) shipping round trips. The Contractor shall hold in reserve resources sufficient to prepare up to two (2) replacement PCBs of each type in the case of catastrophic damage or shipping loss.

C.3.3.1 Design review

Review of schematics for all PCBs to include component part numbers, high-level component interconnection, power budget, high-level layout of all PCBs including location of ICs, board-to-board headers, RF shielding, heat sinks, mechanical support and front panel design.

Review of detailed schematics for all PCBs, finished component interconnections, signal integrity analysis, thermal analysis, power analysis, final PCB routing. Post design files to github and tag. By conclusion of the review, layouts should be ready for manufacture.

Delivery is complete when technical point of contact (TPOC) signs off on the drawings.

C.3.3.2 HT3 manufacturing, baseline testing

Fabricate PCBs in the following quantities. TPOC provides sign off prior to commencement of manufacturing.

· Metlino AMC v1.0: print 10 PCBs, stuff 4

· Sayma AMC v2.0: print 10 PCBs, stuff 6

· Sayma RTM v2.0: print 10 PCBs, stuff 6

· BaseMod v2.0: print 20 PCBs, stuff 12

· TestMod v2.0: print 6 PCBs, stuff 6

Expectations for testing of all stuffed PCBs:

· Atomic documentation of tests and bug reporting using the github Issue tracking system.

· Thermal test in TS7

· goal: maximum temperature of measured integrated circuits (IC) < 65 C

· Monitor temperature of a subset of ICs using Module Management Controller (MMC) Intelligent Platform Management Interface (IPMI).

· crate power-on with all boards and with arbitrary RTM unplugged in TS7

· Hot swap arbitrary AMC and RTM boards in TS7

· Power-on with or without RTM unplugged in TS1

· Signal integrity testing using any suitable FPGA intellectual property (IP) (eg Xilinx) for all ICs. Tested individually.

· Design and implement test to simulate heavy loading of a system configured as TS2. The test is expected to simultaneously exercise the following subsystems

· Inter-Integrated Circuit (I2C), serial peripheral interface (SPI), address all ICs round robin at full speed

· 2 TestMod PCBs installed dissipating representative power

· AD built-in DAC JESD pseudo-random binary sequence (PRB)S test at ten (10) gigabits per second (Gb/s) lane for both DACs

· SDRAM PRBS write-then-read

· AMC backplane ethernet PRBS at 1 GSPS

· Small Form-factor Pluggable (SFP) loop-back PRBS at 6 Gb/s

· AMC backplane PRBS at 6 Gb/s

· FPGA Mezzanine Card (FMC) loop-back

· Realistic FPGA fabric load and clock activity

· MMC configuration including power supply sequencing and IPMI

· Contractor shall test MMC firmware on TS7 system prior to distribution.

Publish MCH configuration file used for these tests with TS-MTCA and NATIVE-R5.

Ship hardware to ARL or designated partner labs. The Contractor retains the following PCBs for testing and as backups in case of system integrator hardware failure: 2 Sayma AMC, 2 Sayma RTM, 4 BaseMod, 1 Metlino.

If errors arise after shipping of hardware, Contractor shall debug and test on TS2.

Delivery is complete when the TPOC confirms receipt of hardware.

C.3.3.4 HT4 documentation and MMC

· Develop and document fixes for hardware bugs.

· Each board should have a serial number and a wiki page to document test results and rework.

· MMC and Exar configuration

· Publish source on github within sinara-hw domain.

· Explicit instructions for building and flashing.

· Follow ARTIQ release structure: tag official releases, change log.

· Formal hardware documentation maintained in github

· Use the software tool Sphinx.

· Setup automatic rendering on readthedocs.org with webhook to git pushes.

· Embed link in github.com that links to readthedocs.org.

· scope: Expected content is superset of existing Sayma v1.0 documentation

HT4 delivery is complete when documentation and source is committed to github and accepted by the TPOC.

C.3.3.5 HT5 demonstration system Build a demonstration system that is fully assembled and tested. The system shall consist of the following components.

· TS-MTCA

· 1 Metlino serving as ARTIQ Master

· 2 Sayma v2 (AMC + RTM)

· 4 BaseMod v2

· Test jigs, clock hardware, documentation and ARTIQ Python code needed to demonstrate the following:

· ST1, ST2, ST3 and ST4

· Use SAWG >= 2.0

· Ship demonstration system to ARL.

· ARL will return clock hardware to the Contractor one (1) month after delivery. All other parts will remain property of ARL.

HT5 delivery is complete when ARL confirms receipt of the demonstration system and TPOC successfully runs test code. ARL has 7 business days to conduct tests.

C.3.3.6 HT6 Round Up

Update schematics and layout to remedy bugs.

Publish to github.com factory acceptance tests including test code, expected results and failure criteria.

C.4 DISTRIBUTION STATEMENT

C.4.1 Determination of the PWS Document:

Distribution Statement A: Approved for public release. Distribution is unlimited.

C.4.2 Determination for information generated from the Contract:

Distribution Statement A: Approved for public release. Distribution is unlimited.