W911NF-23-S-0012-01.pdf

DEVCOM Army Research Laboratory

BROAD AGENCY ANNOUNCEMENT FOR

FOUNDATIONS OF SUPERCONDUCTING DIGITAL LOGIC

(FSDL)

W911NF-23-S-0012

Issued by:

U.S. Army Contracting Command-Aberdeen Proving Ground

Research Triangle Park Division

P.O. BOX 12211

Research Triangle Park, NC 27709-2211

I. OVERVIEW OF THE FUNDING OPPORTUNITY:

A. Required Overview Content

1. Federal Agency Name(s):

2. Funding Opportunity Title: Foundations of Superconducting Digital Logic (FSDL)

3. Announcement Type

4. Research Opportunity Number: W911NF-23-S-0012

5. Catalog of Federal Domestic Assistance (CFDA) Number:

6. Response Dates:

B. Additional Overview Information

II. DETAILED INFORMATION ABOUT THE FUNDING OPPORTUNITY

A. Funding Opportunity Description

A.1 Background and Overview of FSDL

A.2 Research Areas A.2.1 Novel Materials and Processing Techniques A.2.1.1 State of the Practice:

A.2.1.2 Technical Challenges:

A.2.2 Josephson Junction Research A.2.2.1 State of the Practice A.2.2.2 Technical Challenges A.2.3 Flux Trapping Research A.2.3.1 State of the Practice A.2.3.2 Technical Challenges A.2.4 Improvements in Logic & Architecture A.2.4.1 State of the Practice A.2.4.2 Technical Challenges

A.3 Proposal Categories A.3.1 Proposals for Exploratory Projects A.3.2 Proposals for Integration Projects

A.4 Target Applications Discussion

A.5 Government Furnished Resources

A.6 References

B. Federal Award Information

1. Procurement Contract

2. Grant

3. Cooperative Agreement

4. Other Transaction for Research

5. Other Transaction for Prototype or Production

6. Grants and cooperative agreements for Institutions of Higher Education, nonprofit organizations, foreign organizations, and foreign public entities

7. Grants and cooperative agreements for for-profit and nonprofit organizations exempted from Subpart E—Cost Principles of 2 CFR Part 200, are primarily governed by the following:

8. OTs for Research

9. OTs for Prototypes or Production

C. Eligibility Information

1. Eligible Applicants:

2. Cost Sharing or Matching:

3. Federally Funded Research and Development Centers (FFRDCs):

D. Application and Submission Information

1. Address to View Broad Agency Announcement

2. Content and Form of Application Submission

3. Unique Entity Identifier and System for Award Management (SAM)

4. Submission Dates and Times:

5. Intergovernmental Review

6. Funding Guidance:

7. Other Submission Requirements:

E. Application Review Information:

1. Criteria:

2. Review and Selection Process:

3. Recipient Qualification

F. Award Administration Information:

1. Award Notices:

2. Administrative and National Policy Requirements:

3. Reporting:

G. Agency Contacts:

H. Other Information:

1. CONTRACT Proposals:

2. GRANT and COOPERATIVE AGREEMENT Proposals

I. OVERVIEW OF THE FUNDING OPPORTUNITY:

A. Required Overview Content

1. Federal Agency Name(s):

DEVCOM Army Research Laboratory – Army Research Office

Issuing Acquisition Office:

U.S. Army Contracting Command-Aberdeen Proving Ground, Research Triangle Park Division (ACC-APG RTP Division)

2. Funding Opportunity Title: Foundations of Superconducting Digital Logic (FSDL)

3. Announcement Type Initial Announcement

4. Research Opportunity Number: W911NF-23-S-0012

5. Catalog of Federal Domestic Assistance (CFDA) Number:

12.431 – Basic Scientific Research

6. Response Dates:

White Papers: 4:00 PM Eastern Daylight Savings Time on: 15 August 2023 Proposals: 4:00 PM Eastern Daylight Savings Time on: 7 November 2023 See Section II. D. 4 for additional information.

B. Additional Overview Information

This Broad Agency Announcement (BAA) which sets forth research areas of interest to the DEVCOM Army Research Laboratory- Army Research Office (ARL-ARO) and the National Security Agency (NSA) is issued under paragraph 6.102(d)(2) of the Federal Acquisition Regulation (FAR), and 10 U.S.C. 4001, 10 U.S.C. 4021, and 10 U.S.C. 4022 which provides for the competitive selection of basic research proposals. Proposals submitted in response to this BAA and selected for award are considered to be the result of full and open competition and in full compliance with the provision of Public Law 98-369, "The Competition in Contracting Act of 1984" and subsequent amendments.

The Department of Defense agencies involved in this program reserve the right to select for award;

all, some, or none of the proposals submitted in response to this announcement. The participating DoD agencies will provide no funding for direct reimbursement of proposal development costs.

Technical and cost proposals (or any other material) submitted in response to this BAA will not be returned. It is the policy of participating DoD agencies to treat all proposals as sensitive, competitive information and to disclose their contents only for the purposes of evaluation.

II. DETAILED INFORMATION ABOUT THE FUNDING OPPORTUNITY

A. Funding Opportunity Description

DEVCOM Army Research Laboratory - Army Research Office (ARL-ARO), in collaboration with the Laboratory for Physical Sciences (LPS), is soliciting proposals for foundational research in superconducting electronics (SCE). SCE is a promising technology for high-speed and energy-efficient digital circuits, but scaling towards denser and more reliable systems has been slow. The goal of the Foundations of Superconducting Digital Logic (FSDL) program is to uncover foundational issues limiting the progress of this technology and to pursue innovative research into overcoming these issues across topics such as materials, Josephson junctions, flux trapping, and architecture.

FSDL aims to provide the foundation to enable breakthroughs in circuit density and reliability for future SCE-based systems.

A.1 Background and Overview of FSDL

Circuitry based on superconducting wires and Josephson junctions has the potential to yield energy-efficient and/or high-speed computing devices across many applications if certain scaling issues can be addressed [1][2]. The switching energy of the Josephson junction, approximately 2e-19 J, is well below that of transistor-based devices, and superconducting wires offer low-dissipation and low-dispersion interconnects, the lack of which constrain VLSI designs using normal metals. The most well-known application for SCE has been general-purpose computing as a replacement for semiconductor-based data centers [3][4], but other applications include neuromorphic computing [5][6], digital receivers with high-speed analog-to-digital converters and digital signal processing [7][8], and ultra-low power readout electronics for cryogenic sensors/systems such as transition edge sensors, microcalorimeters [9][10][11], and quantum computing [12][13][14]. Additionally, space and satellite technology, where low-power and radiation-hardened designs are valued [15][16], is a potential application, especially given advances in cryogenics for satellites [17].

For many of these applications to become feasible, it is necessary to increase both the density and reliability of SCE. Superconducting circuit density is limited by, among other factors, the geometric inductance required to store flux quanta, shunt resistors for Josephson junctions, minimum niobium line widths, and wide low-impedance transmission lines. Component counts for SCE designs are often dominated by ancillary devices such as clock and bias distribution, Josephson Transmission Lines (JTL), splitter trees for fanout, and buffer cells. Superconducting-memory is far less dense than its CMOS counterpart, constraining memory-intensive applications. The reliability of SCE is limited by issues such as flux trapping and process-stabilization. Flux trapping is a superconductivity-specific issue that could be exacerbated at higher densities, and SCE fabrication processes are unable to utilize process-stabilization techniques developed for CMOS due to temperature limitations imposed by Nb/Al-AlOx/Nb junctions and niobium contamination.

The FSDL program goal is to provide the scientific foundation to overcome the challenges mentioned above. Hence, FSDL is soliciting proposals to study the foundational issues on topics such as materials, Josephson junctions, flux-trapping mitigations, and architectures used for SCE and to explore high-risk yet potentially revolutionary paths forward. The goal is not to produce near-term incremental gains but rather to unambiguously identify the underlying limiting factors and determine the fundamental changes required for both an order-of-magnitude, or more, increase in circuit density as well as reliable fabrication and operation. The program encourages research compatible with future scaling towards complex, dense and practical circuits. Here, “complex” means that the circuit reliably performs computations of meaningful scope, volume, and throughput for the intended application, and “practical” refers to the satisfaction of implementation constraints such as limited I/O ports, bi-directional routing, multiple routing layers and ground planes, and distribution of clock and bias.

Such future circuits will have requirements beyond those of simple repetitive diagnostic devices such as shift registers and ring oscillators. The FSDL program anticipates the complexity and density of future circuits and solicits proposals for research that will ultimately result in dense, complex, and reliable superconducting circuits.

A.2 Research Areas

While FSDL is broadly soliciting proposals on foundational aspects of SCE, the following four research areas are of particular interest to this BAA. For context and background, the following sections describe both the state of the practice (SOTP) for each research area and several technical challenges limiting progress towards higher density and reliability. The ordering of these four technology areas is not indicative of the relative priority the FSDL program places on them. Research that cannot be categorized neatly into one research area will be considered, and research addressing technical challenges that are not described below will also be considered if well motivated by the need to increase the density and reliability of SCE.

A.2.1 Novel Materials and Processing Techniques

A.2.1.1 State of the Practice:

SCE fabrication generally involves sputter deposition of niobium thin films, typically around 200 nm thick, followed by patterning with typical line widths down to 200-250 nm. This niobium film thickness exceeds the London penetration depth, and the incomplete penetration means the inductance per length of patterned lines is less susceptible to variations in film thickness and line widths. These niobium layers are stacked with SiOx as the dielectric and generally require deposition temperatures less than 180o C to minimize niobium contamination and to preserve the quality of Nb/Al-AlOx/Nb junctions (discussed in Section A.3.2).

The niobium film is patterned to form inductors, transformers, passive transmission lines, and vias, each with differing constraints on their size and density. Inductors must have a minimum inductance value to store a magnetic flux quantum; this value is fixed by the junction critical current, which itself is often bounded from below by error-rate requirements for each application. This minimum inductance is typically obtained by simply making inductors long rather than utilizing high-kinetic-inductance (KI) techniques. Line spacing is set by device tolerance to parasitic mutual inductance.

Transformers couple only by geometric mutual inductance and must also be of sufficient length to obtain the required coupling. Passive transmission lines (PTLs) must interface with low-impedance SCE and thus have a low characteristic impedance of 20 ohms or less, obtained with relatively wide signals lines in the range of 5-10 um. Vias are typically fabricated with large aspect ratios to minimize voids in the sputtered niobium and are not stackable.

A.2.1.2 Technical Challenges:

Many limitations arise from undesirable material properties of sputtered niobium:

• Sputtered niobium forms columnar grains that can promote the formation of voids and defects and can interfere with damascene processing or fabricating lower-aspect-ratio vias, especially as feature sizes are reduced. Grains may also act as vortex pinning sites.

• Niobium film surfaces can be rough, interfering with fabricating uniform junctions and increasing variance in film thickness.

• Niobium-film stress can be large, can change from tensile to compressive, and can change with subsequent processing steps. Stress has been linked to variation in superconducting properties and must be monitored and controlled at increased layer count to avoid accumulated topography.

• Above 200o C, niobium readily absorbs low-atomic-number materials that can influence its superconducting properties. Such variable superconducting properties may influence flux trapping, as altered Tc due to subsequent processing can influence the Tc-sequencing of the layers.

Reducing the physical size of inductors will likely require moving to the high-kinetic-inductance (KI) regime where the London penetration depth exceeds one or both line dimensions. This could be accomplished by decreasing the thickness and/or line width for niobium below 200 nm or by using a high-KI material whose penetration depth exceeds 200 nm. However, both approaches will introduce challenges around accurate and consistent inductance targeting while maintaining sufficient critical current. At smaller line dimensions, existing variance in film thickness and lithography will have a larger fractional effect, and oxide layers will occupy a larger fraction of the superconductor cross-section and have a larger influence. Use of high-KI materials [18][19] is a well-known technique for reducing inductor size, but such materials have not yet been incorporated in a multi-layer stack-up.

Fabrication variance will again influence inductance targeting but with the additional complication of stoichiometry control for consistent penetration depth and coherence length. The higher Tc of a high- KI material for wiring layer relative to niobium ground planes is a potential disadvantage in terms of flux trapping, and using high-KI materials for ground planes may reduce shielding.

Transformers are used extensively in AC-biased logic, but there is no clear path to reduce their size.

Reducing line widths may allow for closer spacing of the primary and secondary coils but carries the same risks mentioned above. A soft high-permeability magnetic material compatible with thin-film processing has not yet been identified but would open new possibilities. Cryogenic capacitor materials could enable transformers to be replaced by capacitive coupling [20], but these capacitive materials would themselves need to be developed and integrated.

PTLs enable a unique feature of superconductivity: long-distance low-dispersion interconnects.

However, PTLs currently use very wide line widths to achieve low characteristic impedance.

Techniques to lower the inductance per length, or increase the capacitance per length, that are compatible with thin-film SCE fabrication would be needed to increase PTL density.

Improvements to dielectric deposition are known at deposition temperatures above 400o C, but incorporating such techniques is difficult given niobium’s permeability to contaminants at temperatures above 200o C. AC-biased logic can have substantial AC losses of clock power in the dielectric. Variations in dielectric quality across the chip or wafer will impact PTL properties and uniformity.

FSDL encourages proposals focused on developing novel superconducting material, dielectrics and/or processing techniques to meet the above challenges or other relevant challenges in materials and processing.

A.2.1.3 Out-of-Scope Topics in Novel Materials and Processing Techniques

• Materials incompatible with multilayered fabrication;

• High Tc superconducting materials;

• Superconducting materials with Tc significantly lower than 4K.

A.2.2 Josephson Junction Research

A.2.2.1 State of the Practice The Nb/Al-AlOx/Nb trilayer junction is the widely accepted state-of-the-practice junction for digital applications due to its large critical current, fast switching speed, high yield, and high uniformity.

After base niobium electrodes are patterned, a layer of aluminum is deposited and exposed to oxygen to form a very thin oxide layer, on the order of 10 angstroms. The oxidation step is carefully controlled as the critical current density depends exponentially on the oxide thickness. The aluminum layer is also thought to reduce the barrier roughness caused by the underlying niobium. External and relatively large shunt resistors are incorporated to make these junctions non-hysteretic. Once these junctions are fabricated, all subsequent processing steps are limited to temperatures below 180o C to preserve the AlOx barrier. State-of-the-practice multi-layer SCE processes are dominated by Nb/Al- AlOx/Nb junctions despite a large number of publications and proof-of-concept demonstrations of alternative Josephson junction technologies serving a wide variety of functions beyond digital switching.

A.2.2.2 Technical Challenges Reducing the size of the shunt resistor, or eliminating it by developing self-shunted junctions, could improve circuit density by up to an order of magnitude [24]. Self-shunted junctions have been fabricated by thinning the oxide layer. However, this can cause the cross wafer spread to more than double [25]. Possible explanations include variation in the oxide thickness, surface variance due to the rough niobium electrode, and the formation of pinhole defects. Beyond reducing fabrication spread, the impact of internal heat and quasiparticle generation of a self-shunted Nb/Al-AlOx/Nb needs to be explored.

Nb/Al-AlOx/Nb junctions cannot be processed above 180o C due to oxygen migrating from the barrier to the niobium electrodes. This means that improved dielectric processing at 400o C or above is not feasible for SCE fabrication. It also generally constrains junctions to the top of the stack.

Many junction types have been explored [28][29] to overcome these challenges, and many materials have been tried such as Nb/TaN [30], NbN/TaN [31], NbTiN/AlN [32], NbN/MgO, Nb silicide [33], and Mo-Re/𝛼𝛼Si [34]. However, it is challenging to engineer junctions with sufficient critical currents or characteristic voltages for most digital applications. Other challenges include spread and targeting of critical currents at scale, reverse proximity effects, thermal stability, diffusion through interfaces, sensitivity to stoichiometry [27], and the ability to integrate materials into a multi-layer stack [31].

Of potential interest are junctions that can make specific circuits denser by providing, in a smaller area, functionality currently implemented by other devices. Pi junctions have been used in place of inverting transformers or DC bias [35] and could replace the inductance needed to store single flux quanta (SFQ) [23]. Spin-valve junctions can store energy states and act as superconducting memory cells [21] [36] [37]. Three-terminal junctions could serve as circuit control [22], and superconducting ferromagnetic transistors can be used for programmable logic or readout [38]. Despite the range of potential functionality, at-scale utilization of such junctions remains sparse to-date. Known scaling challenges for junctions utilizing relatively thick layers of magnetic materials include fabrication spread, initializing the magnetization state, large control currents needed to switch the magnetic state, and concerns over contaminating sensitive SFQ-based circuits with magnetic materials.

FSDL encourages proposals focused on developing novel Josephson junction technology, retaining the advantages of Nb/Al-AlOx/Nb junctions, but overcoming the above identified challenges and/or introducing new functionality without degradation of other performance parameters.

A.2.2.3 Out-of-Scope Topics in Josephson Junction Research

• Junctions not amenable to multi-layer processing.

• Junctions with inherently large critical-current spreads, above roughly 3%.

• Switching junctions with IcRn products below 0.2 mV.

• Junctions designed for ultra-cold (millikelvin) applications.

• Switching junctions with critical currents below 10 uA without strong additional motivation.

• Alternate logic elements meant to replace the Josephson junction.

A.2.3 Flux Trapping Research

A.2.3.1 State of the Practice Flux trapping is one of the most pernicious failure modes of SCE, as its impact on circuit margins varies with cool downs, test setups, designs, and fabrication runs. In fact, any change in circuit operation or margins between thermal cycles is often attributed to flux trapping, and it is often assumed that the failure mode is vortex pinning outside a moat. To reduce the probability of this occurring, the community uses a combination of magnetic shielding, slow cool downs, optimized moat layout, and circuit design. Identification of pinned vortices can be achieved with a Scanning SQUID Microscope (SSM) in a dedicated machine on an inactive chip. Specialized electrical characterization techniques, such as bit-by-bit analysis of shift registers, are sometimes employed to extract local margin data.

A.2.3.2 Technical Challenges While present-day mitigation schemes may be sufficient for moderately complex circuits to function reliably, they will likely not scale with either circuit size or density. In fact, despite years of work fine tuning the mitigation framework described above, flux trapping continues to be cited as a present-day impediment. Meanwhile, convincing demonstrations of the exact nature of intermittent failure modes of complex circuits fabricated in a multi-layer stack-up and operated in typical magnetic shielding with sufficient statistics are lacking. An SSM can detect vortices pinned outside moats but cannot correlate them to degraded margins, and gathering sufficient statistics is challenging. Electrical characterization, such as bit-by-bit margin analysis, can detect degraded margins in individual cells but cannot directly correlate them to stray flux. Hardware-to-model correlation could be greatly improved. For example, models of fluxon dynamics and formation during the superconducting transition do not currently predict flux pinning sites with high probability, even in simple designs.

Bridging this gap between vortex identification and circuit performance is of interest to the FSDL program.

Additional research is needed to understand the role of other potential failure modes. Flux and persistent-current distributions below the top ground plane are difficult to measure and may interfere with circuit operation. Thermal fluctuations during transition can generate fluxons in inductive loops [39] or vortex/anti-vortex pairs in thin films [40]. However, such phenomena are challenging to identify without in-situ diagnosis and/or advanced magnetic imaging. Furthermore, thermal activations have been studied in the context of thin films or single-degree-of-freedom loops but not in complex circuits with many degrees of freedom nor as a function of circuit density. Other possible failure modes that do not involve flux include cosmic-ray impacts, electromagnetic interference, and unintended shorts or open connections created during cool down due to ice, thermal expansion, or material growth.

Another impediment is the low SSM throughput, which makes high-statistics magnetic-imaging studies time consuming. For example, a 5 x 5 mm2 chip with over 100 flux quanta might take several days to image completely. While an applied field can increase fluxon density for better statistics, such studies do not necessarily correlate to the low-field best practices [42], and it is instead preferred to increase the instrument throughput to study chips in typical shielding (< 100 nT). Increasing imaging speed is also desired to study flux dynamics during the superconducting transition.

FSDL encourages research in scalable solutions to flux trapping, provided the relevant failure modes have been unambiguously identified. Novel approaches may include passive schemes such as critical-temperature gradients, more advanced shielding, and novel ground plane designs as well as techniques for actively removing flux such as thermal gradients or optical control [41]. Detailed characterization of the influence of the solution on flux trapping is required.

A.2.3.3 Out-of-Scope Topics in Flux Trapping Research

• High magnetic field imagery for validation.

• Experiments that cannot demonstrate statistical significance, e.g., because the failure modes are intrinsically intermittent.

• Vortex dynamic studies in materials without direct application to SCE, unless the results can be reasonably extrapolated to relevant stack ups.

A.2.4 Improvements in Logic & Architecture

A.2.4.1 State of the Practice There are three predominant logic families within SCE: Rapid Single Flux Quanta (RSFQ) and its energy-efficient variants, adiabatic Quantum Flux Parametron (AQFP), and Reciprocal Quantum Logic (RQL). RSFQ is a DC-biased logic, and every RSFQ gate must generally be clocked to compute the output and reset the gate. RSFQ has obtained the fastest operating circuits. For both AQFP and RQL, the functions of current bias and clock are mostly combined into one or more AC signals. The largest circuits to-date have been AC-biased. Neither AQFP nor RQL requires an explicit gate reset.

Memory for superconducting digital logic has been successfully implemented with conventional junctions using address/bit lines with both active [49] and passive [50] signaling. Non-Destructive Read Out memory has achieved a density of 0.23 Mb/cm2 with 2.5 routable layers and 5 kA junctions [49]. Passive memories, such as Vortex Transition memory (VT-RAM), achieved a density of 0.88 Mb/cm2 using 60 kA/cm2 self-shunted junctions [50]. VT-RAM has demonstrated a 4-kb memory block dissipating 9.5 mW with an access time of 380 ps that was essentially propagation delay [51].

The densities of these memory types strongly influence available processor architectures.

A.2.4.2 Technical Challenges The scaling issues of DC biasing are well known – parallel biasing is limited to 20,000 – 30,000 Josephson junctions [24] and can degrade bias margins due to fields from the feed current [43]. Serial biasing techniques [44] require interface circuitry with its own biasing, possibly reducing density, while making signal transfer between the serially biased islands difficult [45]. It is not clear that such techniques can be extended to bias over one million junctions per chip. RSFQ gates typically require a clock pulse to output the logic and reset the gate. This clocking requirement effectively creates deep pipelines that are undesirable for processor architecture, burden static timing analysis, and reduce the effective or logical clock rate. Significant effort must be made in VLSI RSFQ designs to ensure the clock pulse co-propagates with the data. The large clock distribution network, in addition to the energy-efficient biasing network, adds significantly to overhead.

AC-biased logic does not require large bias currents but does require extensive power transmission lines and transformers [24]. There is no clear path to reduce transformer size [24], and crosstalk between transformers will worsen at higher densities [46]. High-speed operation of AC-biased circuits may be limited by clock skew [47] and AC losses in the dielectric. To-date, AC-biased circuits have not matched RSFQ-based circuits in clock speed. AC-biased logic families can utilize multiple clock phases to perform more logic per cycle, but this introduces additional timing complications and may not yield a logical clock rate greatly exceeding CMOS designs.

In VLSI designs, a large fraction of the total junction count comes from ancillary components such as splitters, buffers, JTLs, drivers/receivers for PTLs, and logic-to-memory interfaces, all of which consume power, occupy space, introduce delay, and increase the sites for potentially fatal fabrication defects. This overhead is tolerable at lower integration scales but will increasingly limit high-scale integration. JTL signal reach is limited due to inflexible inductor values and consumes power. PTLs enable long-distance transmission but require large driver and receiver circuits, are very wide, and do not address fanout challenges. Fanout is a costly operation for SCE in terms of delay and overhead in extra components that could be optimized [54]. Buffers are required for timing and path balancing and perhaps could be reduced in number with new approaches to clocking.

A long-standing technical challenge in SCE architecture is the fact that, despite impressive metrics for access time and power dissipation, superconducting memory is far less dense than CMOS-based memory. CMOS SRAM memory with a feature size of 250 nm, comparable to SCE feature sizes, achieves roughly 20 Mb/cm2 [52]. At a 22-nm feature size, CMOS memory densities can exceed 1000 Mb/cm2 [53]. Superconducting memory based on magnetic junctions [21] has been attempted but suffers from the issues discussed in Section A.2.3. Combining cryogenic CMOS and SCE technologies could allow one to combine the memory density of CMOS and logical speed of SCE, but signal conversion is a challenge that could offset the power advantage of SCE.

SCE could benefit substantially from architectures that are tailored to the strengths (low loss interconnects, high clock speed) and weaknesses (low memory density, lack of fanout, lack of multiport memory) of SCE. Many superconducting-processor designs are predicated on CMOS-based designs, which evolved over the era of Moore’s Law and capitalized on rapidly decreasing transistor sizes and the concomitant increases in speed, density, and power efficiency. SCE could instead benefit from architectures that emphasize economy of on-chip memory and incorporate off-chip memory, leveraging superconducting interconnects through multi-chip modules or chip stacking.

Innovative approaches to address the lack of multiport register files, which support multiple in-flight instructions and avoid processor stalling [55], are also desired.

A.2.4.3 Out-of-Scope Topics in Improvements in Logic & Architecture

• Designs for single memory cells that do not have promise to scale.

• Previously attempted memory array without a novel approach or an approach that can yield only incremental gains in density.

• Novel logic with no plans for hardware implementation or whose development path will not yield densities and complexities of interest within the program duration.

• Gate designs for incremental progress.

• Superconducting implementation of known hardware not motivated by a target application.

• Variations of component design that promise only marginal increases in density.

A.3 Proposal Categories

The FSDL program will consider two categories of proposals: those for exploratory projects and those for integrated projects. Further details and proposal requirements for each category are described in detail below.

A.3.1 Proposals for Exploratory Projects Proposals for Exploratory Projects are 4-year-long proof-of-concept efforts for novel research to address one or more technical challenges faced by SCE, such as those discussed in Section A.2. The yearly goals of these Exploratory Proposals are in the following list. The yearly breakdown below should be taken as rough guidance; proposals may vary the rate of achievement of goals, provided the final goal is reached by Year 4:

1. Years 0-1: Definitively identify the physical causes of the targeted technical challenges with supporting experimentation, theory, and/or simulation.

2. Years 1-3: Perform convincing “proof-of-concept” demonstrations of the solution(s) to overcome the identified challenges using an appropriate combination of experiments, theory, and/or simulation.

3. Years 3-4: Project whether the technique(s) developed is applicable to large-scale circuits and whether or not a clear pathway to improved density and reliability is possible. This may involve further demonstrations, theory, simulation, and/or working with GFR fabrication partners (see Section A5).

Exploratory Projects are not required to integrate technological advancements into an established state-of-the-art multilayer stack-up, but proposals must discuss how the planned approaches would be compatible with such multilayer stack-ups. The intention is to encourage novel approaches and exploratory research without incurring the cost, complexity, and time required for integration.

Proposals for Exploratory Projects are expected to incorporate the following information:

• Carefully consider the application space of SCE and motivate their work based on one or more of these applications; refer to Section A.4.

• Identify application-specific metrics, including density and reliability, and describe the state of the art for each metric. Proposals will outline yearly measurable milestones based on these metrics, evaluating the progress of the research towards proof-of-concept demonstrations. The capabilities for each target application that may be enabled upon successful achievement of the defined milestones shall be described.

• Demonstration circuits, test articles, and/or numerical simulations of sufficient scale to demonstrate proof-of-concept compatible with the identified target application.

• Experimental approaches, associated theory, and/or simulation work that cleanly isolate known failure modes, such as trapped flux or fabrication variance, from issues that may be introduced by the new technology.

• Identify all necessary skills and experience needed to successfully execute the research project.

Proposals involving multiple investigators shall describe how those skills are distributed across the team and how research tasks will be divided amongst the proposing team. For example, for proposals with hardware demonstrations, describe where the testing will be done, who will do the testing, required test stands and equipment, and configuration management. If funded, throughout the period-of-performance of the project, performers should be prepared to provide sufficient details of their testing to the FSDL program management team to enable an independent team to reproduce their results.

• Identify the technical challenges associated with the proposed approach, especially with respect to density and reliability.

A.3.2 Proposals for Integration Projects Proposals for Integration Projects are expected to describe a 5-year-long research plan to incorporate novel approaches, for which proof of concept has already been demonstrated, with supporting documentation. Proposals for Integration Projects are expected to describe how these novel approaches will be implemented in a new multi-layer process with the goal of demonstrating the utility of the novel approaches in a complex, dense, and practical circuit (see third paragraph of Section A1). Here, “novel approaches” means technologies or techniques to solve one or more of the technical challenges of scaling SCE, such as those listed in Section A.2, and “novel” means the approach is new to multi-layer stack-ups for SCE, even if the approach has been established in other applications. “Proof of concept” means that the novel approach must have some degree of prior demonstration, either from the literature or from previous work from the proposing team. While innovations are encouraged, a balance must be struck between the risks introduced by the novel approaches, their unintended side-effects and the potential advances offered. Furthermore, while the end goal is to demonstrate a sufficiently complex integrated circuit, proposals must nonetheless emphasize the fundamental issues to be uncovered and challenges to be overcome within the technology under scrutiny.

The yearly goals of these Integration Proposals are in the following list. The yearly breakdown below should be taken as rough guidance to proposing teams; proposals may vary the rate of achievement of goals, provided the final goal is reached by Year 5:

1. Years 0-1: Teams must show that the novel approaches that address one or more technical challenges faced by SCE, such as those described in Section A.2. This may involve some early demonstrations involving experiments, theory and/or simulation to validate the selected approaches beyond the proof of concept referenced in the proposal.

2. Years 1-4: Teams must incorporate the novel approaches into a multi-layer stack-up capable of supporting dense and/or more reliable circuits. Any unintended side-effects must be assessed after incorporation into the stack-up and implement mitigation plans should the side-effects compromise circuit yield or functionality.

3. Years 4-5: Teams must implement their new stack-up to fabricate complex, dense, and practical integrated demonstration chips that fully leverage the novel approaches. This demonstration must prove that the targeted technical challenges have been overcome, thus delivering a device of higher density and reliability for the specific application in mind.

Proposals for Integration Projects are expected to incorporate the following information:

• Carefully consider the application space of SCE and describe a program of research aimed at one or more of these applications; refer to Section A.4.

• Identify application-specific metrics, including density and reliability, and describe the state of the art for each metric. Yearly measurable milestones based on these metrics must be described, evaluating the progress toward delivery of the integrated devices that illustrate the advantages of the chosen technology. The capabilities for each target application that may be enabled upon successful achievement of the defined milestones must be described.

• Include an overarching integration plan that assesses the novel approaches individually and outlines decision points for each integration step into the modified multilayer stack-up.

Decision points define individual deadlines for deciding whether or not to incorporate each novel approach in the new stack-up based on progress towards milestones. Proposals are expected to identify contingency plans should the integration of any proposed novel approach prove intractable.

• Identify any new fabrication techniques or supporting technologies required by their stack-up, including new tooling. These may include established techniques and technologies that are new to the proposing team.

• A series of demonstration circuits and/or test articles aimed at showing functionality, advantages, and challenges associated with the novel approaches. Later demonstrations are expected to be aimed at supporting the identified target application.

• Outline experimental plans, associated theory and/or simulation work that cleanly isolates known failure modes, such as trapped flux or fabrication variance, from issues that may be introduced by the novel approaches.

• Identify all necessary skills and experience needed to successfully execute the research project, how those skills are distributed across the team, and how research tasks will be divided amongst the team. For example, proposals are expected to describe where the testing will be done, who will do the testing, required test stands and equipment, and configuration management. If funded, throughout the period-of-performance of the project, performers are expected to be prepared to provide sufficient details of their testing to the FSDL program management team to allow an independent team to reproduce their results.

• Identify the technical challenges associated with the proposed approach, especially with respect to density and/or reliability.

A.4 Target Applications Discussion The FSDL program will consider proposals for foundational research that may have relevance across a wide range of applications. While direct pursuit of applications other than those described herein is out-of-scope for this BAA, proposals shall include a discussion of the range of possible applications the planned research may enable. Emerging applications may be considered alongside more traditional applications such as general-purpose computing. However, proposals with relevance to emerging applications must focus on scaling issues. Applications in superconducting general-purpose computing typically require developing dense superconducting memory. However, significant advances can be made in other applications ahead of or in parallel with advances in superconducting memory; neuromorphic computing and digital signal processing are possible examples of such memory-light applications. Just as CMOS designers are developing specialized hardware accelerators as the limit of Moore’s Law is approached [56], so might SCE find applications for specialized energy-efficient or high-throughput computational devices.

A.5 Government Furnished Resources For Exploratory Projects, the FSDL program intends to provide access to an established multi-layer fabrication process when appropriate. There may also be limited availability to incorporate new technologies, developed within projects funded by this BAA, into this established process.

The FSDL program is considering providing limited SSM services to performers. The availability and capabilities have not yet been determined and may not be sufficient for all proposed technical approaches. It is advised that white papers include a discussion of the impact such a service could have on the proposed research as well as contingency planning should the SSM service not be available.

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