TI 6340_26 - chp8 vol8.pdf

NSN 0056-00-480-0319 TI 6340.26

FINAL '_

INSTRUCTION BOOK

SITE-REPLACEABLE LRU

SCHEMATICSAND DESCRIPTIONS

ARSR-4 SYSTEM

OSCILLATORMODULE

(FROMUNIT3)

r'UADTI:D R II(_l I IklP %.1_| II.|_t V, wVm.V|W|_.* V

CONTRACT DTFA01-88-C-00037

CONTRACTOR

WESTINGHOUSE ELECTRIC CORPORATION

BALTIMORE, MARYLAND

MADE FOR

U.S. DEPARTMENT OF TRANSPORTATION

FEDERALAVIATIONADMINISTRATION _*_,,,

(1MARCH1995) :

I

RECORD OF CHANGES ,,aE=,vs,o. TI 6340.26 J Vol. 8 ] WESTINGHOUS_EWARRANTY OFTHEARSR--4SYSTEMUNDERPERFORMANCESPECIFICATIONSAND DESIGNCRITERIA

CHANGE SUPPLEMENT CHANGE SUPPLEMENTS (a) Definitions:

TO OPTIONAL TO OPTIONAL

8_slc e_s¢ (1) =Correction," asused inthis clause,meansthe elimination of a defect at no additional costto the Government.

(2) "Defect," as used inthis clause,meansany conditionor characteristicinany suppliesorservicesfurnished by the contractor under this contract that isnot in compliancewith the performance requirements of this contract. Routine repairsassociated with maintenance of each systemafter acceptanceisconsideredto beoutsidethe scopeof the warranty provided that the system is meeting the performance requirements under thiscontract.

(3) "Supp_ies_as used inthis ciausa_meansthe end items' inc_udings_ftware furnished bythe contract_r and re_atedservices required under this contract.

i (4) " " "System, as used m thisclause,meansthe ntagrated and operat ona product(s)that ts(are) to be del vered by the contractor under thiscontract. A "system " includesall of itselements orcomponents includingsoftware.

(5) "Acceptance," as usedIn hisclause, meansthe execution of an offlcla document (e.g., FAAForm256) by an author zeal representative of the Government bywhich the Government assumesfor itself,or an agent of another, ownershipof existing and identified supplies,orapprovesspecificservicesrendered, as partialor complete performance of the contract.

The warranty is consideredaccepted for the purposesof payment at the time of final acceptanceof the systemunder warranty.

(b) Contractor'sObligation:

(1) The contTsctor warrants that eath item furnished underthiscontract shallbefree from defectsdiscoveredbyeither the Government or the contractor for a minimum period of 12monthsafter acceptance,even if the field reliability requirements of H.20* are met earlier. (" H.20" refersto the Field ReliabilityVerification clauseof contract DTFA01*88-C- 00037.) However, if the field reliability requirements of H.20are not demonstratedwithin 12months of the acceptance of eachsystem,the warranty shall be extended for that systemuntil these requirements are verified.

(2) In the event that a defect in any warranted item of supplies/systemisthe resultof a deficiency inthe design of such supplies/system,then any resultingmodification of the affected supplies necessaryto correctthe designdeficiency shall also be incorporated into all items of supplypreviouslyaccepted without regard to the above 12month limitation. Such modifications shallbe done at no increasein contract price. Thecontractor'sobligations under this design warranty subparagraph shallapply until 12monthsfollowing acceptanceof the the lastARSR-4systemunder warranty.

(3) If the contractor becomesaware at any time before acceptanceby the Government (whether before or after tender to the Government) that a defect exi___in any suppliesorservices,the contra_or sha]!:

e (i) Promptly correct the defect, or

(ii) Promptly notify the Contracting Officer, inwriting, of the defect, usingthe sameproceduresprescribedin paragraph (b)(4) of this clause°

(4) If the contractor determines that a defect exists inany of the suppliesorservicesafter acceptanceby the Government under thiscontract, the contractor shellsubmitto the Contracting Officer, inwriting, within 30days,a recommendation for correctiveactions, together with supporting information in sufficientdetail for the Contracting Officer to determine what correctiveaction, if any,should be taken. This recommendation shall besubmitted asa no costECP. If the defect isa design defect, the corrective action/modification shallbe effected at all sitesacceptedunderthiscontract.

(5) The contractor shall promptly complywith any timely written direction from the Contracting Officer to correct or partially correcta defect, at no increasein the contract price.

(6) The contractor shallalsoprepare and furnish to the ContractingOfficer data and reportsapplicable to any correction required under this clause(including reviewand updating of all the affected data ca ed for under th scontract) at no increaseinthe contract price.

(7) In the event of timely notice of a decisionnot to correct or onlypartially correcta defect, the contractor shallsubmit a technicaland cost proposal,within 30 daysfrom the time notified, to amend the contract to permit acceptanceof the affected suppliesor servicesin accordancewith the revisedrequirement andan equitable reduction in the contract pdce shall promptly be negotiated by the parties and be reflected ina contract modification.

(8) Anysuppliesor parts thereof corrected or furnished in replacement, and any servicesreperformed, shallalsobe subject to the conditionsof the clauseto the sameextent and for the remaining duration of the warranty applicable to the suppliesor servicesinitially accepted.

(9) The contractor shall not be responsibleunder thisclausefor the correctionof defectsin Government-furnished property, except for defects in installation, unlessthe contractor performs,or isobligated to perform, any modifications or other work on suchproperty. In that event, the contractor shallbe responsiblefor correctionsof defectsthat resultedfrom work

_ performed bythe contractorfor modificationsor other work.

- -- (10) If the Government or contractor returns suppliesfor correctionor replacementunderthis clause,the contractor shall be liable for transportation chargesup to an amount equal to the costof transportation bythe usualcommercial method of shipmentfrom the placeof deliveryspecifiedin the contract(irrespective of the F.O.B,point or the point of acceptance)to the contractor's plant and return to the piece of delivery specifiedin thiscontract. The contractorshallalsobear the riskof lossfor the supplieswhile in transit.

(11) All implied warranties of merchantability and "fitness for a particular purpose" are excludedfrom any obligation underthiscontract.

FAA Form 1320-5 _o_0)USEPREVIOUSEDITION

TI 6340.26

I I INSERT LATEST CHANGED PAGES. DESTROY SUPERSEDED PAGES.

LIST OF EFFECTIVE PAGES I

Dates of issue for original and changed pages are:

Original...0...I March 1995

TOTALNUMBEROFPAGESINTHISPUBLICATIONIS 45 CONSlSTINGOFTHEFOLLOWING:

Page *Change Page *Change Page *Change NO. No. No. No. No, No.

A

B Blank i,,,oo,o.o_o.oo.,.. 0 ii Blank iii- iv 8-I - 8-9 8-10 Blank 8-11 8-12 Blank A-I - A-23 B-I B-2 Blank .......... O B-3 m_ B-4 Blank

* Zero in this column indicates an original page.

Vol. 8

(1 March 1995) A/B

IWlZ_O_JCTIOH

The contents of this book are arranged as follows. Page-size text and tabular material appear first. Illustrations that support the text and tabular material appear next in an 11-inch by 17-inch flat-pak format. Engineering schematic diagrams, also in an 11-inch by 17-inch flat-pak format, appear next in Appendix A. A page-size list of acronyms and abbreviations appears last in Appendix B.

A

(I March 1995) i/ii

T16340.26

TABLE OF CONTENTS

Paragraph Title Page

CHAPTER 8 - OSCILLATOR MODULE

8.1 Introduction ........ 8- I

8.2 Schematic Diagram.q". ....... 8-I

8.3 TechnicalDescription........ 8-I

8.3.I AssemblyOverview. . . 8-1

8.3.I.18.3.1.2 OscillatorFrequency Selectx2sAIIA1thro_h" A19 8-28-2

8.3.1.3 9:1SwitchA20 .... 8-2

8.3.1.4 Voltage Regulators A2 through A10 " . 8-2

8.3.2 Detailed Description ..... 8-3

8.3.2.I PowerDistribution..... 8-3

8.3.2.1.1 +20-Volt DC Distribution" . . . . 8-3

8.3.2.1.2 -15-Volt I)CDistribution .... 8-3

8.3.2.1.3 Voltage Regulators A2 through AIO 8-3

8"3"2"28.3.2.2.1FrequenCYoseillatorSeleCtselection'A1."."."."" 8-48-4

8.3.2.2.2 Co.mmndCheck(BIT) ....... 8-5

8.3.2.3 OscillatorX2s A11through"A19 8-5

8.3.2.3.1 Oscillator ......... 8-5

O 8.3.2.3.38"3-2-3-2 OscillatorBuffer .....Control.... . ."."."."" 8-78-6

8.3.2.4 9:1 Switch A20 ......... 8-8

APPENDIXES

AB ListEngineeringofAcronymsSChpmatiCSandAbbreviations.... . ."."."." . . B-IA-I

(1 March 1995) iii

LIST OF ILLUSTRATIONS

Figure Title Page

8-I Functional Block Diagram 8 9 iv (1 March 1995)

CHAPTER 8

OSCILLATOR MODULE

8.1 INTRODUCTION.- This chapter provides schematic diagr_m_ and a technical description for the ARSR-4 System IF Receiver/Frequency Generator (Unit 3) oscillator module, part numbers 3D59638G01 through 3D59645G01. The part number used depends on the assigned operating frequencies for the particular radar site. The oscillator module is used in one location in unit 3 where it has reference designation A2. For maintenance purposes the oscillator module is classified as a site-replaceable unit repaired at the depot. Refer to chapter I for general information, signal information, conventions, and definitions.

8.2 SCHEMATIC DIAGRAMS.- Schematic diagrams for the oscillator module and its subassemblies are provided in the Engineering Schematics Appendix A. Schematic diagram 3D60078 is an overall schematic diagram for the oscillator module that shows how the subassemblies are connected to each other and to the assembly input/output connectors. The subassembly schpm_tic diagr_m_ provided are:

Subassembly SchematicDiagramNo.

Frequency select AI 3D57035

Voltage regulator A2 - AIO 3D57029

Oscillator X2 A11 - A19 3D57026

9:1 switch A20 3D57032

General reference data for microcircuits shown in the schematic diagr_m_ is provided in the Integrated Circuit Data book, TI 6340.25.

8.3 TECHNICAL DESCRIPTION.- The technical description of the oscillator module begins with an assembly overview that defines the purpose of each subassembly and describes essential subassembly operations and interactions. The overview is followed by a detailed description. In the detailed description, power distribution within the assembly is described first, and then each subassembly is described in depth, with the schematic diagr_m_ serving as reference.

8.3.1 Assembly Overview.- The oscillator module contains nine separate oscillators. The Signal Processor (Unit 4) selects one of the nine oscillators via frequency select At. The selected oscillator has its frequency multiplied to produce the stable local oscillator (STALO) frequency. The range of oscillator frequencies is from 45.5929 to 48.4250 _4z. The output of the oscillator module is twice this frequency range, or 91.1858 to 96.8500 MHz, which corresponds to a STALO frequency range of 1.45897 to 1.54960 GHz. Within the range of oscillator frequencies, there are 20 different frequencies available for selection. Of the nine oscillators in each oscillator module, eight have different frequencies selected from the 20 that are available, and one has the same frequency as one of the other eight oscillators. Each oscillator module is composed of frequency select At, voltage regulators A2 through A%0, oscillator X2s A11 through A19, and 9:1 switch A20. A functional block diagr_am,figure 8-I, shows the major circuit functions and the primary signals associated with them.

VoL 8

(I March 1995) 8-1

8.3.1.1 Frequency Select At.- Frequency select AI interfaces with the Signal Processor (Unit 4) to select the desired oscillator. Twisted-pair differential signals FSASFGFREQSEL(0:3)+/- supply coded eo_m_md signals to the frequency select for decoding to select a particular oscillator. The frequency select monitors the nine oscillator X2s, A11 through A19, and routes fault conditions back to the Signal Processor (Unit 4) via twisted-pair differential signals RO$OSCILFLT(O:8)+/-. Twisted-pair signal RO$OSCDECFLT+/- reports a fault for the frequency select when the oscillator that is commanded on line by the frequency select is not the oscillator that is com_nded on line by the Signal Processor (Unit 4).

8.3.1.2 Oscillator X2s A11 through A19.- Each oscillator X2 contains a BT-cut crystal oscillator and a frequency doubler. [A BT-eut crystal is a piezoelectric plate cut from a quartz crystal at an angle of rotation (about the X-axis) of -49 degrees.] The oscillator has exceptionally low noise. A heater that keeps the crystal at 149 degrees Fahrenheit (65 degrees Celsius) maintains long-term stability. The oscillator on each of the nine oscillator X2s runs continuously. At each oscillator X2 output, a frequency doubler multiplies the oscillator frequency by two. Selection of the particular oscillator needed for a desired STALO is made by the Signal Processor (Unit 4) via frequency select At. On conmmnd from the Signal Processor (Unit 4), the output of the selected oscillator X2 is switched to the output of the oscillator module, and the other eight oscillator X2 outputs are disconnected.

8.3.1.2.1 Both the input and the output of the frequency doubler are switched on or off, depending on whether or not the oscillator is selected for the ST_LO.

Frequency select AI controls the switches via signals OSCICMDF through OSC9CMI)F.

A transistor-transistor logic (TTL) high level turns the output of the oscillator X2 on, and a low level turns the output off. The output of the frequency doubler is connected to 9:1 switch A20.

8.3.1.2.2 The output of the oscillator on oscillator X2 is detected to supply a built-in test (BIT) signal. An oscillator fault causes a loss of its output and, in turn, a loss of detected voltage. The result is a low condition on signals OSCIFDET through OSC9FDET. Signals OSCIFDET through oSCgFDET are connected to the oscillator fault detector on frequency select AI.

8.3.1.3 9:1 Switch A20.- The 9:1 switch connects the output frequency (RO$SGOSC) of the selected oscillator X2 to STALe generator module K3. The 9:1 switch also provides isolation between oscillator X2s filithrough fi19.

8.3.1.4 Voltage Regulators fi2through AIO.- Each of the nine voltage regulators supplies dc operating voltages to one of the nine oscillator X2s, A11 through A19. Each of the nine voltage regulators is mounted in its own enclosure in the oscillator module. Power input to the oscillator module is +20 volts de and -15 volts dc from receiver multivoltege power supply PSI. Two hybrid regulators are mounted in the wall of each regulator enclosure. One hybrid regulator (UI, U3, US, U7, U9, U11, U14, U16, or U18) reduces the +20-volt dc input to +15 volts de; the other hybrid regulator (U2, U4, U6, U8, UI0, U12, U13, U15, or U17) reduces the -15-volt dc input to -11.6 volts de.

Voltage regulators fi2through AIO filter the crystal oscillator dc supply voltages, protect the +15-volt dc hybrid regulators, and regulate the +15 volts dc down to +11.6 volts de. Inputs to each voltage regulator are +20 volts de, +15 volts de, -15 volts de, and -11.6 volts de. Outputs from the voltage regulators to the oscillator X2s are +15 volts de, +11.6 volts de, and -11.6

Vol, 8 8-2 (I March 1995) volts de. A reference voltage is supplied to all -11.6-volt dc hybrid regulators.

8.3.2 Detailed Description.- The following paragraphs describe details of the operation previously s,,mm_rized in the assembly overview. Power distribution within the assembly is described first, and then each of the three subassemblies is described.

8.3.2.1 Power Distribution.- See schematic diagram 3D60078, sheets 5 through

8. Power is supplied externally from receiver multivoltage power supply PSI by +20-volt dcand -15-volt de supplies. Two lines connect each supply to oscillator module input power connector J2 (sheet 5). The +20 volts de is connected to connector J2 pin 12 (sheet 7), J2 pin 13 (sheet 8), J2 pin 14 (sheet 6), and J2 pin 15 (sheet 5). The +20-volt de return is connected to connector J2 pin 2 (sheet 5), J2 pin 3 (sheet 6), J2 pin 5 (sheet 8), and J2 pin 6 (sheet 7). The -15 volts de is connected to connector J2 pins 9 and 10 (sheet 5). The -15-volt de return is connected to connector J2 pins 7 and 8 (sheet 5).

All +20-volt and -15-volt returns are grounded to the oscillator module chassis.

8.3.2.1.1 +20-Volt DC Distribution. See schematic diagram 3D60078, sheets 5 through 9. Nine positive hybrid voltage regulators [UI and U3 (sheet 5), U5 and U7 (sheet 6), U9 and U11 (sheet 7), U14 and U16 (sheet 8), and U18 (sheet 9)] provide +15 volts de from the +20-volt de supply. For voltage regulator A2 (sheet 5), the +20 volts de from connector J2 pin 15 is filtered by feedthru filter FLI and connected to regulator UI pin I (IN) and terminal El on the voltage regulator. Regulator UI pin 3 is grounded. The +15-volt dc output at regulator UI pin 2 (OUT) is connected to terminal E2 on the voltage regulator.

8.3.2.1.2 -15-Volt DC Distribution. See schematic diagram 3D60078, sheets 5 through 9. Nine negative hybrid voltage regulators [U2 and U4 (sheet 5), U6 and U8 (sheet 6), UIO and U12 (sheet 7), U13 and U15 (sheet 8), and U17 (sheet 9)] provide -11.6 volts dc from the -15-volt dc supply. For voltage regulator A2 (sheet 5), the -15 volts de from connector J2 pin 9 is filtered by feedthru filter FL4 and connected to regulator U2 pin 3 (IN) and terminal E4 on the voltage regulator. Regulator U2 pin I (ADJ) is connected by line U2ADJ to the reference voltage supplied at terminal E5 on voltage regulator A2. The -11.6-volt de output from regulator U2 pin 2 (OUT) is connected to terminal E4 on voltage regulator A2.

8.3.2.1.3 Voltage Regulators A2 through AIO. See schematic diagram 3D57029, sheet 2. The voltage regulator has two positive input voltages, +20 volts de to terminal El, and +15 volts de to terminal E2. Diode CRT, connected between terminals El and E2, protects the external regulators supplying the +15 volts de, also connected between terminals El and E2, from failure. Diode CR7 discharges capacitor CI if loss of the input +20 volts de occurs. Capacitor C9 provides stable operation of the regulator. The +15 volts de is routed to terminal E8 and then to the oscillator heater on the oscillator X2 associated with the particular voltage regulator.

8.3.2.1.3.1 Capacitor CI provides stable operation of regulator UI on the voltage regulator. Diodes CRI and CR2 protect regulator UI from loss of +15-volt de--powerby discharging capacitors C5 and C3, respectively. Diode CR3 prevents a negative excursion of the +11.6-volt de output of regulator UI that is connected to terminal E9. Resistors RI and R2 provide the reference voltage

(1 March1995) 8-3 that sets the output of regulator UI to +11.6 volts de. Capacitors C5 and C7 filter the output, and capacitor C3 filters the reference voltage.

8.3.2.1.3.2 The filtered -15-volt dc supply -15VF* is regulated to -11.6 volts de by an external regulator (U2, U4, etc. as shown on schematic diagram 3D60078 sheets 5 through 8) connected to terminals E3 through E5. Apart from the reversals in polarity and reference voltage U*ADJ, this circuit is the same as the positive voltage regulator described in paragraph 8.3.2.1.3.1, and all the components perform equivalent functions. The -11.6-volt dc output voltage is connected to terminal E7. Terminals E6 and EIO are grounded to the voltage regulator.

8.3.2.2 Frequency Selegt AJ.- All connections between connector J1 on frequency select AI and the Signal Processor (Unit 4) are made with twisted-pair lines whinh transmit fault signals and oscillator selection signals.

8.3.2.2.1 Oscillator Selection.- See schematic diagram 3D57035, sheet 2.

Osnillator select differential signals FSASFGFREQSEL(O:3)+/- from the Signal Processor (Unit 4) are input to differential line receiver U12. The selection of each oscillator is made by binary coding the differential voltage levels on signals FSA$FGFREQSEL(0:3)+/-. The coding of the differential signals and the selection of oscillator X2 are as follows:

Selected

FSASFGFREQSEL Q FSASFGFREQSELI FSASFGFREQSEL2 FSASFGFREQSEL_ Oscillator X2

0 0 0 0 None

0 0 0 1 All

0 0 I O A12

0 0 I I A13

0 I 0 0 A14

0 1 0 1 A15

0 1 1 0 A16

0 1 1 1 A17

1 0 0 0 A18

1 O 0 1 A19

8.3.2.2.1.1 The four outputs of differential line receiver U12 are connected to inverter U5 pins 5, 9, 11 and 13. The four outputs from inverter U5 drive binary-ended decimal (bed)-to-decimal decoders U1 and U3. Signal bus CMDCHK(0:9)- from bed-to-decimal decoder UI checks the operation of the selection circuits. Signal bus CMDDEC(0:9)- from bed-to-deci,_l decoder U3 selects the on-line oscillator.

8.3.2.2.1.2 See schematic diagram 3D57035, sheets 2 and 3. Signal bus CMDDEC(0:9)- from bed-to-decimal decoder U3 (sheet 2) is connected to NAND drivers UT-through U11 (sheet 3). Output signals OSCICMD through oSCgCMI)from NAND driver_-U7 through Uli are connected to terminals E11 through E19, respectively, and to +5 volts dc via pull-up resistors R6 through R14, respectively (sheet 3). Depending on the oscillator selected, one of these signalsisa TTLhighand theothereightsignalsareTTL low. Afterpassing (

8-4 (IMarch1995) through line filters, signals OSCICMD through OSC9CMD are sent as signals OSCICMDF through OSC9CMDF to frequency select AI and oscillator X2s Ali through A19, respectively.

8.3.2.2.2 Command Check (BIT).- See schematic diagram 3D57035, sheet 3. The eomm_nd check circuits output a fault signal to the Signal Processor (Unit 4) when the oscillator X2 decoded to be on line by frequency select AI is different than the oscillator X2 com,_uded on line by the Signal Processor (Unit 4).

8.3.2.2.2.I See schematic diagram 3D57035, sheets 2 and 3. Voltages connected to terminals El I through E19 from NAND drivers U7 through UI I are also inputs to buffer/line driver U20 (sheet 3). The outputs from buffer/line driver U20 are connected to 8-bit identity comparator U2. Signal bus CMDCHK(I :8)- from bed-to-decimal decoder UI (sheet 2) is also connected to 8-bit identity comparator U2. In fault-free operation, all bits of signal bus CMDCHK(I:8)- are at the same level as their matching output signal from buffer/line driver U20.

In fault-free conditions, the output of eomparator U2 is high.

8.3.2.2.2.2 See schematic diagram 3D57035, sheet 3. Outputs signals OSC9CMD and OSCOCMD from line driver U11 pins 6 and 8, respectively, are treated separately. Signals OSC9CMD and OSCOCMD are connected to pins 5 and 2, respectively, of exclusive-OR gate U4. Check signals CMDCHKO- and CMDCHK9- are connected to exclusive-OR gate [14pins 4 and 1, respectively. With matching inputs, i.e., fault-free, each output of exclusive-OR gate U4 is high. The two outputs from exclusive-OR gate U4 and the output from 8-bit identity eomparator U2 are connected to NAND gate U6. In fault-free operation, all three inputs to NAND gate U6 are high and output signal CMDERR is low.

8.3.2.3 Oscillator X2s A11 through A19.- There are 20 different oscillator X2s from which the eight different oscillator X2s used in the oscillator module are chosen. All 20 oscillator X2s are similar, the only difference being the frequency of the components used on the particular oscillator. The descriptions in the following paragraphs are applicable for any of the 20 oscillator X2s.

8.3.2.3.1 Oscillator.- See schematic diagram 3D57026, sheet 2. The oscillator has unity gain that is set by adjusting the gain of transistor amplifier QI without varying its operating point. The gain of transistor Q1 is varied by controlling the amount of collector RF voltage fed back to the base. The ratio of the amplitude of the voltage at the collector of transistor QI to that at its base is determined by the ratio of the capacity to ground at the base to the capacity to ground at the collector. The gain is controlled by varying the capacity of the base through the use of a varactor. The varactor-controlled voltage is derived by rectifying the RF voltage at the collector of transistor QI, filtering and amplifying the rectified voltage, and feeding the amplified voltage back to control the varactor bias.

8.3.2.3.1.1 See schematic diagram 3D57026, sheets 2 and 3. Transistor QI provides amplification for the oscillator. A broadband low Q (selectivity) resonant eireuit for the collector of transistor QI is formed by inductors L3, L13 and L19, capacitors C43 and C46, and varactor CR5 (sheet 2). Inversion of the voltage phase at the collector of transistor QI occurs across inductor L13, thus provi_Tng feedback to the base of transistor QI. The network composed of resistor RS, inductor L17, and capacitor C50 grounds the base for dc and suppresses parasitic oscillations. Series mode resonant crystal YI is connected

(1 Mareh 1995) 8-5 between the emitter of transistor QI and the emitter of transistor Q2 (sheet 3), which is low impedance tO ground.

8.3.2.3.1.2See schematicdiagram3D57026,sheet2. CrystalYI is operatedat i its series-resonant frequency, i.e., the frequency where its impedance is an extremely low resistance. Due to its location in the oscillator circuit emitter lead, the oscillator only oscillates if crystal YI is a low resistance. In this manner, crystal YI determines the frequency of oscillation.

8.3.2.3.1.3 The gain of the oscillator is controlled by feedback from operational amplifier UI. Diode CRI rectifies the oscillation sine wave at the collector of transistor QI, thereby providing peak detection of the voltage developed across inductor L3 and charging capacitor C8. This voltage level across capacitor C8 is fed to the inverting input of operational amplifier UI, where it is compared with a +4.5-volt dc reference at the non-inverting input.

The reference voltage (CVADJ) is set by variable resistor R40 at terminal EIO.

The output at operational amplifier UI pin 6 is connected to the cathode of varactor CR5 via a filter composed of resistors R2 and R30, and capacitors C3, C4 and C41. This voltage, supplied to varactor CR5, adjusts automatically until the detected voltage at operational amplifier UI pin 2 is exactly equal to the voltage at operational amplifier UI pin 3. Test point terminal El; for the operational amplifier UI output voltage (OSCTP) is decoupled by resistor R31 and capacitor C42.

8.3.2.3.1.4 The voltage applied to operational amplifier UI pin 3 is derived from +11.6 volts dc by a voltage divider composed of fixed resistors R25, R26 and IL29and variable resistor R40. High stability zoner diode CR6 provides a ÷8.2-volt de reference voltage for this voltage divider. Resistors R28 and R27 form high-impedance current sources for operational amplifier UI. Capacitor C39 d filters noise from the reference signal, and capacitor C40 is the integrator for • operational amplifier UI.

8.3.2.3.1.5 The oscillator is adjusted at the factory. Variable resistor R40 is adjusted to +4.5 volts de at terminal El0, and then variable capacitor C43 is adjusted for maximum positive voltage at terminal El I. This corresponds to the minimum gain condition from transistor QI, indicating that the impedance at the collector of transistor QI is purely resistive and the maintaining oscillator is tuned to the same frequency as the series-resonant frequency of crystal YI.

8.3.2.3.1.6 Operational amplifier UI is supplied with +11.6-volt de power,via deooupling resistor R32 and filter capacitor C35, and with -11.6-volt do power via deeoupling resistor R33 and filter capacitor C36. A sample (OSCTEST) of the RF voltage developed at the collector of transistor QI is available, at a level of greater than +3 dBm, at normally-terminated test connector J1. The collector of positive-negative-positive (PNP) bipolar transistor Q1 is supplied by -11.6 volts do via the decoupling network composed of resistors RI and R9, capacitors CI, C2 and C29, and inductor LI. The emitter of transistor Q1 is supplied with +11.6 volts dc via a decoupling network composed of resistors R5 and R12, capacitors C9, CIO and C30, and inductor L2. Capacitor C7 is a de blocking capacitor, and inductor L20 anti-resonates the self capacity of crystal YI.

8.3.2.3.2 Buffer.- See schematic diagram 3D57026, sheet 3. Transistor Q2, which is operated as a grounded-base amplifier, buffers the oscillator output.

Oscillator output signal OSC is coupled to the emitter of transistor Q2. The output of transistor Q2 is tuned by inductor L18 and variable icollector

8-6 (I March 1995) capacitor C44. Resistor R15 sets the Q of the transistor Q2 collector circuit.

DC conditions are set by the collector and emitter voltages of transistor Q2 and resistors R3, R7 and R13. Decoupling is provided by capacitors C11 through C14, C31 and C32, and inductors L4 and L5. The buffered oscillator signal from transistor Q2is coupled by capacitor C37 to port IN of amplifier ARt.

Amplifier ARt provides a gain of 12.5 dB for the buffered oscillator signal.

The B+ voltage for amplifier ARt is obtained from +11.6 volts dc via the decoupling network composed of capacitors C15, C16 and C34, and inductors L6 and L7. The output (OUT) of amplifier ARt, is attenuated 5 dB by a network composed of resistors R4, R6 and RIO. The output of the attenuation network is coupled to electronic switch U3 (a solid-state relay).

8.3.2.3.3 Oscillator Control.- See schematic diagram 3D57026, sheet 3. The oscillator frequency is input via electronic switch U3 to either doubler U4 or to an internal load. In the off position, electronic switch U3 provides more than 60 dB of isolation to the input of doubler U4. The output of doubler U4 is tuned to twice the oscillator frequency (91.19 to 96.85 MHz) by fixed capacitor C38, variable capacitor C45, and inductor L16. Capacitor C24, connected to output terminal E7 (labeled OSC*OUT), provides a do block. Switching positive intrinsic negative (PIN) diode CR8 further increases the isolation of the output signal at terminal ET. With electronic switch U3 in the on position, the RF signal level at terminal E7 is +5 dBm, corresponding to 0.4 volt rms.

8.3.2.3.3.1 TTL levels generated by frequency select AI turn the oscillator X2 output on or off. A high at terminal E9 turns the oscillator X2 on, and a low turns oscillator X2 off. From terminal E9, signal OSC*CMDF is filtered by capacitors C19 and C20 and inductor L14, and limited to +5.I volts by zener diode CR4. At this point, signal OSC*CMDF splits to drive electronic switch U3 and transistor Q3. Transistors Q3 and Q4 are the switching transistors for PIN diode CR8. The current to drive electronic switch U3 at its control (CTL) terminal is set and filtered by resistor R34 and capacitor C48. The B+ voltage to operate electronic switch U3 at its V+ terminal is obtained from +11.6 volts de via decoupling components composed of capacitors C17, C18 and C28 and inductor LI0. Resistor R19 sets the current for zener diode CR7, which clamps the voltage to +6.2 volts de at the V+ terminal of electronic switch U3.

8.3.2.3.3.2 Drive to inverter transistor Q3 is divided by resistors R20 and R21. Capacitor C49 filters high frequency components to ground during the transition levels of signal OSC*CMDF. A high at the base of transistor Q3 causes a low at the collector of transistor Q3. This low is applied to the base of transistor Q4, thus producing a high at the collector of transistor Q4. This high is applied to the cathode of PIN diode CR8 via decoupling components composed of resistor R35, capacitor C23 and inductor L15, thus biasing PIN diode CR8 off. The anode of PIN diode CR8 is held at +2 volts de. In this condition, current flows from the collector of transistor Q4 through resistor R35, inductor L15, the PIN diodes in 9:1 switch A20, and then to STALO generator module A3, thereby allowing the RF signal to flow. See paragraph 8.3.2.4 for a discussion of 9:1 switch A20.

8.3.2.3.3.3 For a low control voltage applied to terminal E9, opposite conditiona occur throughout. The collector of transistor Q4 is now driven low, causing PIN-diode CR8 to conduct and attenuate any residual amounts of signal leaking through doubler U4 to terminal E7. The B+ voltage to operate transistors Q3 and Q4 is obtained from +11.6 volts de via decoupling capacitor C21 and decoupling inductor L12. Resistor R38 sets the current for zener diode

(1March1995) 8-7 decouples this voltage. Resistors R36 and R38 serve as loads to transistors Q3 and Q4, respectively. Resistors R22 and R24 divide the level applied to transistor Q4. Resistor R35 is a current-limiting resistor.

8.3.2.3.3.4 A BIT signal is developed by rectifying the signal at the input to electronic switch U3. Resistor R17 attenuates this signal to diode CR2, which is a peak detector that charges capacitor C25. Inductor LI I and capacitor C27 filter the voltage developed across capacitor C25. Resistor R23 limits the current of signal OSC*FDET delivered to the load. The BIT voltage developed at terminal E6 is +1.4 to +2.4 volts de.

8.3.2.3.3.5 See schematic diagram 3D57026, sheet 2. Oscillator X2 uses +15 volts de, +11.6 volts de, and -11.6 volts de. The +15 volts dc powers heater U2 and is connected between terminals E5 and E4. Capacitors C33 and C47 and inductors L8 and L9 filter the +15 volts de. Heater U2 maintains crystal YI at a temperature of 149 degrees Fahrenheit (65 degrees Celsius).

8.3.2.4 9:1 Switch A20.- Refer to schematic diagram 3D57032, sheet 2. The outputs from oscillator X2s A11 through A19 are connected to input terminals El through E9 respectively. All voltages are low on these terminals except the one associated with the oscillator }[2 selected for input to STALe generator module

A3. The output of the selected oscillator X2 drives the input terminal to which it is connected on 9:1 switch A20 positive, causing the two diodes in series to conduct. If, for example, terminal El is driven positive, diodes CRI and CRIO

(signal OSCIOUTF) conduct, eonneeting the signal at terminal El to signal

RO$SGOSC at output terminal El0. All other diodes on 9:1 switch A20 are not conducting at this time, thereby rejecting any signal present at their input terminals. Capacitors CI through C9 and inductor LI increase the isolation of each line. Capacitor CI0 is adc blocking capacitor in series with inductor LI.

Conduction through the diodes cannot occur unless output terminal EIO is grounded for de conditions. This connection is made in STALe generator module

A3 through the eoaxial cable from output connector J3 of the oscillator module.

8-8 (1 March 1995)

QUENSELEA OSCLTORX2AIISWTCHINGI

COMMAND I OSCILLATOR l TRANSISTORS

DECODER COMMAND

f FSA$FGFREQSEL(0:3)+/- 8 10 CMODEC(0:9)), INTERFACE 10 OSC(0:9)CMD 1 OSC1CMDF _- ,, r ,- ,- 3D57026

3D57035 3D57035 SH3

SH2,3 SH3

CMDCHK(O:9) SWITCH DOUBLER

COMMAND 9: I _ _ OSClOUT _

SIGNAL PROCESSORTO/FROM ._ CHECK 3D57026 3D57026 3D57026 3D57026

(UNIT4) _ _ RO$OSCDECFLT+/- 2,/ (BIT) 10I/ OSC(0:9)CMD SH2 SH3 SH3 SH3

3D57035

SH 3, 6 OUTPUT

LEVEL

DETECTOR

OSClFDET

OSCILLATOR =C

FAULT

RO$OSCILFLT(0:8)+/- 18/ DETECTOR 3D57026

=( " (BIT) SH 3

OSC2CMDF ). OSCILLATOR X2 A12 OSC2OUT

OSC2FDET

NOTE:

SIGNAL INPUTS TO LRU ARE FROM THE IF OSC3CMDF

RECEIVER/FREQUENCY GENERATOR (UNIT 3) _, OSCILLATOR X2 A13 OSC3OUT

AND SIGNAL OUTPUTS FROM LRU ARE TO OSC3FDET _=

THE IF RECEIVER/FREQUENCY GENERATOR

(UNIT 3), UNLESSOTHERWISE INDICATED. _-SH 2

OSC4CMDF

_, OSCILLATOR X2 A14 OSC4OUT )=,

OSC4FDET

=c

OSC5CMDF

)= OSCILLATOR X2 A15 OSC5OUT _,

OSC5FDET

OSC6CMDF ), OSCILLATOR X2 A16I OSC6OUT

OSC6FDET

•" OSCTCMDF _=,/OSCILLATOR X2 A17 OSC7OUT

OSC7FDET [=E

,.. OSC8CMDF _ l OSCILLATOR X2 A18 OSC8OUT

OSC8FDET [ :_

OSC9CMDF :_ / OSCILLATOR X2 A19 oscgouT

3D57035 OSC9FDET [ )"SH4,5,6

2522H-S2_)O1R

Figure 8-1. Functional Block Diagram (Sheet I of 2)

(I March 1995) 8-9/8-10

FROM RECEIVER + 20V i

MULTIVOLTAGE

POWER

SUPPLY PSI

VOLTAGE _ VOLTAGE _ VOLTAGE

REGULATOR I REGULATOR _ , REGULATOR

REGULATOR A5 REGULATOR A8

A2 "_ U7 +15V4 + 15V4j_ U14 +lSV7 _ + 15V7)UI +lSVl _ + 15V1_ _ 3D5600783D56_78 3D560078

SH5 +11.6V1_ TO SH6 +11.6V4 k TO SH8 +11.6V7 _ TO

OSCILLATOR _ ) {_ OSCILLATOR ), ) {'_ OSCILLATOR

-11.6V1J X2All -11.6V4) X2A14 -11.6V'/J X2AI?

REGOLATOR REGOLATOR --'1REGOLATORSH

U8 -11.6V4 U13 -11.6V7

U2 -11.6V1 ._ 3D57029 i _ 3D57029 -- _ 3D57029 3D56_78 F I 3D560078

3D56_78SH5 SH 2 SH6 SH 2 L sH 2

VOLTAGE _ VOLTAGE _ VOLTAGE

REGOLATOR-- REGULATOR3 IREGULATOR,EOOLATOR3

REGULATOR A3 REGULATOR A6 | U16 A9

U3 +15V2 _ +ISV2_,'_ U9 +15VS _ +ISVS_, +ISV8 +ISVSj,,3DS60078 3D56_78 - I 3DS60078

SHS +11.6V2 k TO SH7 +11.6VS _ TO L SIlo +11.6y8 , TO

OSCILLATOR _ _ OSCILLATOR _ _ _ OSCILLATOR

-ll.6_J X2AI2 -11.6VS) X2A15 -ll.6_J X2A18

REGULATOR REOOLATOR -------'. EGULATOR

U15 -11.6V8

U4 U10 -11.6V5 _ )3D57029 -- 3D57029 -- 3D57029

3D56_78 3D56_783DS60078 SH2 SH2 SH25H5 SH7 SH8

VOLTAGE ) VOLTAGE ]P VOLTAGE

REGULATOR / [ 3DS60078 REGULATOR _ , 3D560078 REGULATOR

REGULATOR A7 REGULATOR AIO

REGULATORu5 +15V3 _ A4 +15V3_'_ _ Ull +lSV6 _ +15V6_ U18 +lSV9 _ +15vgj= 3DS60078 r

SH6 +11.6V3 \ TO SH7 +11.6V6 _ TO SH9 +11.6y9 _ TO

}_ {_ OSCILLATOR ) _- (_ OSCILLATOR ) _ _ OSCILLATOR

) -,,.6_.,,jX_A,3 r _j X_A,O -1,.6_..,jX2A,9REGULATOR , REGULATOR REGULATOR

I U17 -11.6V9 U6 -11.6V3 _ 3D57029 _ U12 -11.6V6 _ 3D57029 _ _ 3D57029

3D56_78 SH 2 3DS6_78 SH 2 3DS_078 SH 2SH6 SH7 SH9

9:1 SWITCH _0

_ REGULATOR 1

OSCIOUTF ._ 9:1 DIODE U19 +5V)_ TO FREQUENCY

SWITCH 3DS60078 SELECTA1

OSC2OUTF SH9

OSC3OUTF _OSC40UTF

OSCSOUTF _1 RO$SGOSC TO STALO GENERATOR

SH 1 _ )' MODULEA3OSC6OUTF

OSC7OUTF _OSC8OUTF

OSC9OUTF __ 3DS7032SH2

i

2S22H-S2_)02B

Figure 8-I. Functional Block Diagram (Sheet 2 of 2)

(I March 1995) 8-11/8-12

CHAPTER 8 - APPENDIX A

ENGINEERING SCHEMATICS

This appendix contains an overall schematic diagram for the oscillator module and schematic diagrams for its subassemblies. The diagrams appear in the order listed as follows:

Assembly/Subassembly Schematic No. of Sheets Page Number

Oscillator Module 3D60078 9 A-2 Frequency Select AI 3D57035 6 A-11 Voltage Regulator A2 - AIO 3D57029 2 A-17 Oscillator X2 A11 - A19 3D57026 3 A-19 9:1 Switch A20 3D57032 2 A-22

Vol. 8

App. A

(1 March 1995) A-1

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