STATEMENT OF WORK P17068 - Naval Research Lab - HSP (003).pdf
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- Solicitation number
- N0017326Q5528
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This is a Statement of Work (SOW) for consulting services to be provided by The MathWorks, Inc. to the Naval Research Laboratory (NRL) under contract P17068.
The NRL requires consulting services to support evaluation and integration of AMD Versal AI Core platforms (VCK190 evaluation kit and Alpha-Data Versal platform board VA601) with ADC/DAC FMC cards using JESD204C interfaces. The contractor shall develop and support a prototyping workflow enabling NRL's algorithm developers to prototype algorithms directly on space application hardware. The SOW encompasses four primary tasks totaling 410 estimated person-hours: (1) Create a Linux image and default reference design for the VA601 board with board bring-up using MathWorks meta layer (60 hours); (2) Support VA601 for prototyping workflow with HDL Coder IP Core Generation, including authoring reference designs, creating HDL plugin files, and developing ADC/DAC software for register initialization (150 hours); (3) Test reference designs through LED blinking, streaming data transfers, and full data flow testing from host PC through RF channels (50 hours); and (4) Support VA601 for HDL Coder and Model Composer for AI Engine, including authoring reference designs with AI Engine interfaces and testing generated bitstreams (150 hours). All services will be performed at the contractor's premises. The period of performance and specific execution dates will be determined upon receipt of a signed Agreement and purchase order. Acceptance criteria require all items and services to be received and in full working order. The NRL points of contact are Eric Justh (Technical) and Victoria Howard (Business) at 4555 Overlook Ave SW, Washington, DC 20375-0001.
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STATEMENT OF WORK
TITLE: P17068 – US Naval Research Laboratory HSP
I. Background Information The Naval Research Laboratory (NRL) requires consulting services to support an AMD Versal AI Core, VCK190 evaluation kit and the Alpha-Data Versal platform board (VA601). This work is focused on the integration of their ADC/DAC FMC cards (through JESD204C) and requires a custom reference design. The goal is to enable NRL's algorithm developers to prototype their algorithms directly on the hardware being used in their space application.
II. Scope This Statement of Work covers the consulting services to be provided by The MathWorks, Inc. to the Naval Research Laboratory to develop and support a prototyping workflow for the VCK190 and VA601 platforms.
III. Objectives The primary objectives of this project are:
• Create a Linux image and default reference design for the VCK190 and or VA601 boards.
• Develop and support a prototyping workflow using HDL Coder IP Core Generation.
• Create and test reference designs for the VA601 platform, including interfaces for AXI4-Stream and AI Engine.
• Enable the use of ADC/DAC (passthrough) with custom reference design plugin files.
IV. Services to be performed or specification of items to be procure.
The contractor shall independently perform all work and furnish all labor, materials, supplies, equipment, and services (except as otherwise specified in the contract) to perform the following services:
Specific Requirements – The contractor shall perform the following tasks:
• Task 1: Create Linux Image (Estimated 60 hours)
• Author a default reference design for the VA601 board and provide handoff files for a Linux build.
• Perform board bring-up with a default bitstream using the MathWorks meta layer.
• Task 2: Support VA601 for prototyping workflow with HDL Coder IP Core Generation (Estimated 150 hours)
• Author reference designs for a "Default system" and a "Default system with AXI4-Stream interface".
• Create HDL board/reference design plugin files.
• Create custom reference design plugin files for the use of the ADC/DAC (passthrough), based on the Xilinx reference design provided by NRL.
• Develop software for register initialization on the ADC/DAC configuration registers.
• Task 3: Test the reference designs (Estimated 50 hours)
• Test the default reference design by blinking an LED.
• Test the streaming reference by sending data from the host PC and streaming it back.
• Test the full data flow by streaming data from the host PC to the RF channels via DAC, to the receive ADC channel, and sending it back to the host PC.
• Task 4: Support VA601 Platform for prototyping workflow with HDL Coder + Model Composer for AIE (Estimated
150 hours)
• Author reference designs for a "Default system with AXI4-Stream interface w/AI Engine" and create HDL board/reference design plugin files.
• Author reference designs for "System Design Interface to ADC/DAC w/AI Engine" and create HDL board/reference design plugin files.
• Test the generated bitstreams on the board for AI Engine Custom Reference Designs.
V. Period of Performance The specific dates of execution will be arranged with mutual agreement upon receipt of a signed copy of this Agreement and a purchase order for the amount specified. The total estimated effort is 410 person-hours.
VI. Deliverables All services will be performed at the contractor's premises unless otherwise stated. The point of contact for the Naval Research Laboratory is:
• ADDRESS: 4555 Overlook Ave SW, Washington, District of Columbia, 20375-0001, United States
• POC NAME: Eric Justh (Technical), Victoria Howard (Business)
VII. Inspection and Acceptance Criteria The items/services listed in the scope of this document must be received and in full working order to be accepted as final by NRL.
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