Specifications.pdf

Requirements / Specification Document

TITLE: All-Glass Microwave Microfluidic Wafers

Requesting Laboratory / Division / Group:

Communications Technology Laboratory Radio Frequency Technology Division Guided Wave Electromagnetics Group, MS672.01

General Statement of Need:

The National Institute of Standards and Technology (NIST), CTL/RFT, in Boulder, CO has a project funded by the NIST-on-a-Chip Initiative to build on-chip microwave microfluidic devices to measure intermolecular interactions, electrochemical interfaces and biomolecules. There is an urgent need for new strategies to measure dielectric spectra for small batches of high-value pharmaceuticals, specialty chemicals, and catalysts, because the cost to develop a large-scale separation is too high. At the cutting edge of small-batch separations research, chemists control intermolecular interactions to improve the separation efficiency, yield, and purity of the target molecule.

To this end, we require all-glass microwave microfluidic devices to provide enhanced chemical resistance for electrical measurements in a range of frequencies and pressures.

The information from these measurements will be utilized to develop constitutive equations and models of the fluid dynamic response and the intermolecular interactions in solution.

Item Specifications and Quantities:

Item 1: Encapsulated All-Glass Microwave Microfluidic Wafers (8-inch wafers) Quantity: 4 EACH Specifications: 1.1 High purity fused silica for substrate and microfluidic roof wafers.

1.2 One platinum resistor deposition layer (25 nm) on substrate wafer.

1.3 One platinum conductor deposition layer (600 nm) on top of the resistor layer.

1.4 Platinum layers shall be adhered with non-magnetic adhesion layers.

1.5 Metallization layer tolerances of 0.5 microns.

1.6 One patterned silicon dioxide layer (1-5 microns thick) on top of platinum electrode layer, polished with chemical-mechanical polishing to required smoothness of RMS less than or equal to 1 nm.

1.7 Silicon dioxide layer shall be adhered to the platinum

electrode layer with silicon nitride.

1.8 All patterns will be provided by NIST as .gds files.

1.9 Hermetically bonded glass channels to substrate wafer, 100-micron depth channels.

1.10 Channels shall have straight sidewalls achieved through, for example, laser cutting.

1.11 Platinum electrodes must be directly exposed to the channel.

1.12 Platinum electrode ends (at least 500 microns width) must be fully exposed for probe station measurements.

1.13 Any etching for exposure of platinum electrodes must not exceed an over-etch of 50 nm below the substrate surface.

1.14 Temperature treatments of wafers in process should not

exceed 300 degrees Celsius.

1.15 Channel to substrate misalignment tolerance of 10 microns.

1.16 Devices should withstand 100 psi applied fluid pressure.

1.17 Vias to the fluid channels should come through the top wafer

(the wafer with channel etched out).

1.18 Wafers should be fully diced into individual chips.

Item 2: Fused Silica Wafers with Calibration Artifacts (8-inch wafers) Quantity: 1 EACH Specifications: 2.1 High purity fused silica for substrate wafer.

2.2 One platinum resistor deposition layer (25 nm) on substrate wafer.

2.3 One platinum conductor deposition layer (600 nm) on top of the resistor layer.

2.4 Platinum layers shall be adhered with non-magnetic adhesion layers.

2.5 Metallization layer tolerances of 0.5 microns.

2.6 One patterned silicon dioxide layer (1-5 microns thick) on top of platinum electrode layer, polished with chemical-mechanical polishing to required smoothness of RMS less than or equal to 1 nm.

2.7 Silicon dioxide layer shall be adhered to the platinum

electrode layer with silicon nitride.

2.8 All patterns will be provided by NIST as .gds files.

2.9 Platinum electrode ends (at least 500 microns width) must be fully exposed for probe station measurements.

2.9 Any etching for exposure of platinum electrodes must not

exceed an over-etch of 50 nm below the substrate surface.

2.10 Wafer should be fully diced into individual chips.

Procurement Support Information and Ancillary Services:

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Section Requirements/Specifications

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