SOW.pdf

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Attached to
Multi-Project Wafer (MPW) run. Federal contract opportunity
Solicitation number
80NSSC231307
Issued by
National Aeronautics and Space Administration Shared Services Center

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STATEMENT OF WORK

1. Objective/Requirements Fabrication of silicon chips with custom NASA design in TSI Semiconductor

Complementary Metal-Oxide-Semiconductor (CMOS) processes.

2. Characteristics, Scope, and Specs

The contractor shall perform the following duties:

Fabricate and deliver specific integrated circuits (ASICs) containing a NASA GSFC design in the Tower Semiconductor CA18 180nm CMOS process.

Tower Semiconductor CA18 180nm is used to fabricate custom integrated circuits, specifically designed for this CMOS process. These integrated circuits are in support of R&D activities related to science instruments and spacecraft electronics.

3. Place of Performance Tower Semiconductor

4. Period of Performance

1 year period of performance (12 months)

File details come from the government source that posted it. Updated .