Single Source Justification (Simplified Acquisition) - AFRL/IZH High-Performance Computer Center Design Services

This is a Single Source Justification document for a simplified acquisition submitted by the Department of the Air Force for engineering design services. The Air Force Research Laboratory (AFRL), located at Wright-Patterson Air Force Base (WPAFB) in Ohio, seeks to contract with ERG, a mechanical engineering consulting and design firm, to provide engineering services for a Level 2 design charette for a proposed High-Performance Computing (HPC) center. The required services include developing mechanical and electrical systems requirements and infrastructure specifications for a future building that will house data equipment and supporting spaces. The contractor must travel to WPAFB for on-site design charette meetings, where mechanical and electrical engineers will attend sessions to make informed design decisions, evaluate trade-offs, and review charette documentation. Additional engineers will provide periodic assistance. The contracting activity is AFRL/PKI BLDG 15 WPAFB, OH 45433, and the project is identified as AFRL/IZH High-Performance Computer Center Design Services.

The justification for single-source solicitation centers on ERG's specialized expertise in providing engineering requirements for high-performance computing centers that meet Government standards and regulations. ERG has previously completed the Level 1 proposal for the current facility effort and possesses critical technical knowledge necessary to create accurate and technically complete Level 2 design charette documentation, including the critical DD 1391 form. The contracting officer, Joshua Sawdey (DO-03), determined on December 31, 2025, that only a single source is reasonably available per FAR 13.106-1(b)(1). To prevent future single-source awards, AFRL plans to conduct frequent market scanning, engage with industry through numerous agreements, and continuously evaluate emerging services and technologies to expand competition for future HPC design requirements.