SATPC0042900 Tab 04 4 SOW.pdf

STATEMENT OF WORK

1. Objective/Requirements

NASA requires a complete set of Engineering Test Unit (ETU) electronic cards, Backplane, Chassis and Intellectual Property for Main Electronics Box (MEB) testing and evaluation for ultimate use in space over a 5 year mission. The design shall be capable of processing TensorFlow Artificial Intelligence (AI), support 1.5 TB of on-board non-volatile memory storage, be capable of communicating via the necessary

Spacecraft interfaces defined below, possess the ability to drive Thermal Electric

Coolers (TEC’s), calibration sources and optical switches, provide thermal control via operational heaters, decontamination heaters & thermal sensors, and simultaneously drive/control/read two detectors at a frame rate up to 50Mbps each. The design must meet the power and mass specifications and be within the schedule defined below.

2. Characteristics, Scope, and Specs

The contractor shall deliver an entire set of ETU electronic cards, including Backplane, chassis and IP to GSFC by 3/1/2027 capable of the following;

• An architecture capable of on-the-edge AI that supports TensorFlow and where the algorithm can be reprogrammed from the ground

• Include processor and FPGA (Field Programmable Gate Array) space for Spacecraft interfacing and specific instrument functionality as defined below

• Separate RS422 interfaces between the Spacecraft for Command, Telemetry, PPS

(Pulse Per Second) and Science data

• Provide a LVPS (Low Voltage Power Supply) capable of up to 50W of total power consumption that is MIL-STD-461 compliant with filtering and inrush mitigations

• Provide an overall design that is compliance to MIL-STD-461 EMI/EMC

(Electro-Magnetic Interference/Compliance) RE (Radiated Emissions), RS (Radiated Susceptibility), CE (Conducted Emissions), and CS (Conducted Susceptibility)

• Provide stable power, and LVDS (Low Voltage Differential Signaling) interfaces for commanding, engineering telemetry and science data between two Teledyne SIDECAR (System for Image Digitization Enhancement Control And Retrieval) ASIC’s (Application Specific Integrated Circuits) and two Detectors, including capability of reading out full frames simultaneously at up to 50Mbps

• Provide 2-10V variable voltage control, up to 7.5W each for 2 TEC’s capable of maintaining a stable (+/-500mK) thermal environment via closed loop temperature feedback

• Provide three independent variable voltage (7-12V), constant current (0.2-1.2A) sources

• Provide PWM (Pulse Width Modulation) control of 5-8 heaters (12V, 125mA max each) capable of independent 1-100% duty cycle control

• Provide capability to read 16 PRT (Platinum Resistance Thermometer) thermal sensors within -50C to +50C range

• Provide control of up to three 12V/<80mA optical switches

• Provide a JTAG interface to access FPGA programming

• Provide a test-only ethernet port for test interrogation and fastest processor, AI and FPGA programmability

• Provide at least 1.5 TB of non-volatile memory storage capability

• Provide memory scrubbing

• Design to include all space qualified connectors for every interface

• Provide a minimum of the following electrical analyses; WCCA (Worst Case Circuit Analysis), PSA (Parts Stress Analysis), SI (Signal Integrity) and PI (Power

Integrity)

• Provide mechanical/structural analyses to support nominal Falcon Heavy LV

(Launch Vehicle) Vibration, Acoustics and up to 1910 G’s Shock

• Provide MIUL (Material Identification and Usage List)

• Provide thermal analyses with ability to support 12 cycles of TVAC (Thermal Vacuum) testing between -50C to +50C

• Compliant to 30krad TID (Total Ionizing Dose) and 75MeV cm2/mg LET (Linear

Energy Transfer)

• Overall mass less than 3kg

• Provide verification of card level and box level functional testing

• Provide hardware support

3. Place of Performance

NASA GSFC in Greenbelt, MD

4. Period of Performance

Hardware needs to be available for qual integration and testing starting March 1st 2027, the latest.