PDG_SSRD_V15 (AP WIP).docx

DOCX document 3 MB Posted Apr 22, 2026

Attached to: F16_HRPDG_AP
Solicitation number: F16_HRPDG_AP
Issued by: Department of the Air Force Materiel Command Lifecycle Management Center Hill Air Force Base

About this file

Written by GovTribe AI · Apr 22, 2026

This is a Subsystem Requirements Document (SSRD) for the F-16 High Resolution Programmable Display Generator Upgrade (HRPDG), established as of March 24, 2026, and distributed under DISTRIBUTION STATEMENT D to DoD and DoD contractors only. The document contains controlled unclassified information (CUI) with export restrictions under the Arms Export Control Act and requires dissemination in accordance with DoD Directive 5230.25.

The SSRD outlines technical specifications and performance requirements for the HRPDG upgrade system, including video processing capabilities, data storage, cryptographic services, memory error detection, and display output standards. Key technical parameters include video latency requirements (maximum 100 milliseconds), processing throughput specifications (measured in DMIPS), mass storage capacity (240 gigabytes), and startup time requirements (10 seconds plus 1 second for measurement uncertainty). The document specifies support for H.264 video compression standards, SHA-256 and SHA-512 memory error detection, and various video signal interfaces including RS-170 resolution standards, DVI output at 60Hz, and XGA 1024x768 resolution for CDU pixel displays. The requirements document has undergone 12 revisions since its initial release on October 5, 2015, with the most recent revision (Revision 12) dated August 2, 2021, incorporating clarifications on video signal specifications, processing throughput measurements, startup timing, and power interruption procedures. The document references the MLV CONOPS (Concept of Operations) as Appendix B and includes detailed signal timing diagrams and interface specifications in its appendices.

View the file

Other files

File	Type	Posted
PDGU_CDRL_B001Redacted.pdf	PDF	Apr 22, 2026
HRPDG AP SOO.pdf	PDF	Apr 22, 2026
PDGU_CDRLS_A001_through_A03F_Redacted.pdf	PDF	Apr 22, 2026

On GovTribe

Work with this file

Download the original file
Contacts named in this file
Similar government files
Ask GovTribe AI about this file

Try for free Login

Text version

The file's text, extracted by GovTribe without its formatting.

SUBSYSTEM REQUIREMENTS DOCUMENT (SSRD)

FOR THE

F-16 HIGH RESOLUTION PROGRAMMABLE DISPLAY GENERATOR UPGRADE (HRPDG)

24 March 2026

DISTRIBUTION STATEMENT D - Distribution authorized to the DoD and DoD contractors only; critical technology; 18 July 2017 Other requests for this document shall be referred to AFLCMC/WWM, 6137 Wardleigh Rd Bldg 1515, Hill AFB, UT 84056

WARNING - This document contains technical data whose export is restricted by the Arms Export Control Act (Title 22, U.S.C. Sec 2751, et seq.) or the Export Administration Act of 1979, as amended, Title 50, U.S.C., App. 2401 et seq. Violations of these export laws are subject to severe criminal penalties. Disseminate in accordance with provisions of DoD Directive 5230.25.

CUI

Revision History

Revision

Description

Date

Initial Release

5 October 2015

Various fixes including:

· Pre SRR Identified Issues

· Problematic requirements identified at SRR

· Removal of Objective requirements, and revision of requirements to include values from contractor proposal.

· Addition of ICD Appendix

· Issues identified in CECs:

o	7512.001
o	7512.002
o	7512.003
o	7512.003A o	7512.004
o	7512.009
o	7512.015
o	7512.019
o	7512.020
o	7512.028
o	7512.031
o	7512.037
	20 April 2018

Added Cryptographic Services Section, Corrected RS-170 resolution issue, Defined remaining configuration discretes.

Changes are outlined in the following CECs:

7512.045

7512.050

18 December 2018

Modified SSD Transfer speed into separate read and write requirements to match actual performance vice theoretical maximum 4Gbit/sec read, 2.4 Gbit/sec write.

Modified CMFD DVI output from 30Hz to 60Hz in ICD. Changes outlined in PCOL 19-04-02 Mass Storage Capacity changed to 240 Gbytes from 256 Gbytes to account for future potential for bad sectors.

29 Apr 19

3.2.1.1 B-frame compression excluded from H.264 Standard 3.2.1.6.1.5 Turn off Random Number Generation when not in use. 3.2.1.8.3.1 Memory Error Detection added SHA-256 and SHA-512. Removed Deleted Pages from ICD.

Fixed Page Numbers in ICD.

07 April 2020

3.2.1.6.1.2 Removed requirement for normal elliptic curve point multiply.

16 April 2020

3.2.1.6.1.2 Updated wording for clarity, “timing equalized and version”

29 May 2020

3.2.1.8.3 Removed Wear Leveling Requirement for Gov’t Writable EEPROM/Flash; Updated Section 3.2.1.9.1 and added referenced MLV CONOPS V8 as Appendix B

1 July 2020

Added Appendix C

3.1.3.1 Added and Appendix C.

3.1.3.2.4 Added and Appendix C

3.1.3.4 Added and Appendix C

3.1.3.4.2.1 Added and Appendix C

3.2.1.2.2.2 Added and Appendix C

Replaced table of Contents with Automatic one. Fixed broken links Updated Page Numbering Created Links for all tables and figures Fixed TOC and automatic numbering in Appendix B MLV conops.

Added to 3.3.6.7 “Where entrapment of fluids can occur and cause deterioration of equipment or cause equipment malfunction,”

11 Jan 2021

Removed Note 5: This signal is not used by the Block 30 ACMFD from MFDSPWRON signal.

Added Signals CMFD1RST, CMFD2RST, CMFD3RST and CMFD4SRT to Appendix C.

Removed AGM-65 A and B types.

Added Signal is Monochrome to note 1 for VS Video A

Removed 22X specification from CMFDXXXX signal timing diagram. Specification was redundant.

02 March 2021

Updated Radar Signal VIDCOMP in Appendix A to support for APG-83 radar and clarify specification. Updated to Vertical Period with tolerance instead of Frame Rate. Removed Northrup Grumman info only pages.

Updated VS Video A, VS Video B, VS Video C, VS Video E and Color Video In to specify Vertical Period and Horizontal Period with tolerance instead of Frame Rate. Color Video In uses note 5 from 16PP967. All others use General Purpose 525-Line Video from 16PP967. HARM has a tolerance of 1%.

02 Aug 2021

3.2.1.7.1 Change processing throughput requirement from MIPS to DMIPS

3.2.1.1 Video Latency to max of 100 mS

3.2.1.4.2 Startup time to pass control to application software from 5 sec to 10 sec + 1 sec for measurement uncertainty. Removed SBIT from this requirement.

3.2.1.4.4.1 SBIT complete time from start of SBIT rather than power application. The OFP is expected to call SBIT.

3.2.1.4.4.4 Dynamic Link: Removed requirement to be completed within 5 second of power application.

3.1.3.2.1.2 1553 No response timeout wording updated.

PDGCDUDVI1, PDGCDUDVI2: Updated to add XGA 1024 x 768.Added CDU pixel display notes Added Pair Shields and Overall Shield pins.

Appendix B: Updated to Rev 11 of MLV CONOPS

3.1.5.1.3 Added requirement to continue normal operations for power interruptions <= 50mSec

Updated Ref Black tolerance on Block 30 to +/-40mV to match Block 40.

18 Nov 2021

3.1.3.1.1.2 Changed the maximum power draw at 30VDC to 65 watts (was 68 watts)

4.6.1.4.1.1 Temperature-Altitude Tests

Added note 6 Note 6: Deviation from specified performance during test condition must be recoverable to normal operation after a warm start.

Added

3.2.1.5.2 The HRPDG shall [-5] provide independent switching capability, turn output signals on and off, for all DVI video outputs via software control during runtime.

07 September 2022

Added Section 3.2.1.12

Updated Section 3.2.1.6.1, Section 3.1.3.2.2 , Section 3.1.3.1.1.2, Section 3.1.3.4.2.0, Section 3.1.4.3, Section 3.2.1.2, Section 3.2.1.3, Section 3.2.1.7.1, and Section 3.3.13.5.1

Adjusted Value in 3.2.1.9.1

Adjusted Table 4

Deleted 3.2.1.4.4.1

11 September 2023

Deleted 3.2.1.4.4.1

3.2.1.4.3 Removed the Removed Section

Deleted Section 3.2.1.4.3 From Verification Cross Reference Matrix

3.1.3.4.1.2 Removed the Removed Section

Section 3.2.1.6.1 Cryptographic Services.

Fixed alignment on Figure 1.

Added Appendix D

Changed MTBF to minimum 500 hours at 95% confidence

Updated Table of Contents 24 March 2026

Table OF COnTENTS

1	SCOPE	1
1.1	Definition of Terms	1
2	APPLICABLE DOCUMENTS	1
2.1	Government Documents	1
2.2	Non-Government Documents	3
3	Requirements	5
3.1	Item Definition	5
3.1.1	Item Diagram	5
3.1.2	Major Components	5
3.1.3	Interface Requirements	7
3.1.3.1	Electrical	7
3.1.3.1.1	Electrical Power Interfaces	8
3.1.3.1.1.1	Input	8
3.1.3.1.1.2	Output	8
3.1.3.2	Serial Communications Interfaces	8
3.1.3.2.1	MIL-STD-1553B Serial Bus	8
3.1.3.2.1.1	Inter-message gap	9
3.1.3.2.1.2	No Response Time-Out	9
3.1.3.2.2	High Speed Network Interface	9
3.1.3.2.3	RS-422 Interface	9
3.1.3.2.4	Universal Asynchronous Receiver Transmitter Interface	9
3.1.3.3	Discrete Interfaces	9
3.1.3.3.1	Discrete Inputs	9
3.1.3.3.1.1	High-Level Discretes	9
3.1.3.3.1.2	Low Level Complementary Discretes	10
3.1.3.3.1.3	Open/Ground Discretes	10
3.1.3.3.2	Discrete Outputs	10
3.1.3.3.2.1	Low Level Complementary Discretes	10
3.1.3.4	Video Interfaces	10
3.1.3.4.1	Video Inputs	10
3.1.3.4.1.1	RS-170 & A	10
3.1.3.4.2	Video Outputs	10
3.1.3.4.2.1	RS-170 RGB	10
3.1.3.4.2.2	NTSC RS-170/170A	11
3.1.3.4.2.3	DVI	11
3.1.4	Mechanical Interfaces	11
3.1.4.1	Mounting Tray	12
3.1.4.2	Support Interface Access	12
3.1.4.3	Growth Provisions	12
3.1.5	Electrical Power Characteristics	12
3.1.5.1	Power System	12
3.1.5.1.1	Internal Power Supply	12
3.1.5.1.1.1	Block 40/50 Display Support	13
3.1.5.1.1.1.1	+30 VDC Display Power	13
3.1.5.1.1.1.2	+28VDC Display Heater Power	13
3.1.5.1.1.2	Block 30 Display Support	13
3.1.5.1.2	Steady State and Transient Operation	13
3.1.5.1.2.1	Normal Power Transients	13
3.1.5.1.2.2	Abnormal Transients	13
3.1.5.1.3	Power Interruptions	13
3.2	Subsystem Performance Requirements	14
3.2.1	Functional Performance	14
3.2.1.1	System Video Latency	14
3.2.1.1.1	Viper MLV	14
3.2.1.2	System Processes	14
3.2.1.2.1	General Processing Function	15
3.2.1.2.2	System I/O Communications Processes	15
3.2.1.2.2.1	1553 Modes	15
3.2.1.2.2.2	CMFD UART Communication Processes	15
3.2.1.2.2.2.1	CMFD Switch/Control Response	15
3.2.1.2.2.3	Ethernet Protocols	15
3.2.1.3	Display Function Processing	15
3.2.1.3.1	Graphics Support	16
3.2.1.3.2	Display Processing Functions	16
3.2.1.3.3	Image Canvas/Display Formats	16
3.2.1.3.4	Display Resolution	16
3.2.1.4	Start-Up	16
3.2.1.4.1	HRPDG On/Off Discrete	16
3.2.1.4.2	Cold Start	17
3.2.1.4.3	Self-Test/Built-In-Test	17
3.2.1.4.3.1	Start-Up/Power-On-Bit	17
3.2.1.4.3.2	Periodic BIT	17
3.2.1.4.3.3	Initiated BIT	17
3.2.1.4.3.4	Dynamic Link	17
3.2.1.5	Display Driver Capabilities	18
3.2.1.5.1	Display Channels	18
3.2.1.5.2	Video Switching	18
3.2.1.5.3	Video Decompression	18
3.2.1.5.4	Symbology and Video	19
3.2.1.5.4.1	External Video Noise Rejection	19
3.2.1.5.5	CMFD Configuration Discretes	19
3.2.1.5.6	Moving Map	21
3.2.1.6	Cyber Security Requirements	22
3.2.1.6.1	Cryptographic Services	22
3.2.1.6.1.1	Cryptographic Files	22
3.2.1.6.1.2	Elliptic Curve Cryptography	22
3.2.1.6.1.3	Cryptographic Authentication	23
3.2.1.6.1.4	Symmetric Key Block Ciphers	23
3.2.1.6.1.5	Random Number Generation	23
3.2.1.6.1.6	Run-Time Integrity Checking	23
3.2.1.6.1.7	Advanced Protocol Support	23
3.2.1.7	Processing Functionality	23
3.2.1.7.1	Throughput	24
3.2.1.7.1.1	General Purpose Processor	24
3.2.1.7.1.2	Display Processor	24
3.2.1.8	Memory	24
3.2.1.8.1	Memory Retention Functional Requirements	24
3.2.1.8.2	Memory Zeroize	24
3.2.1.8.3	Memory Size and Type	25
3.2.1.8.3.1	Memory Error Detection	25
3.2.1.8.4	Mass Storage	25
3.2.1.8.4.1	Mass Storage Capacity	25
3.2.1.9	Supportability and Safety Performance	25
3.2.1.9.1	Reliability, Maintainability and Human Factors (MTBF MTBR)	25
3.2.1.10	Maintainability	28
3.2.1.10.1	On-Aircraft Maintenance Time	28
3.2.1.10.2	Mean-Time-to-Repair	28
3.2.1.10.3	On-Aircraft Maintenance Personnel	28
3.2.1.10.4	Troubleshooting	28
3.2.1.10.5	Tools	28
3.2.1.10.6	Alignments and Calibration	28
3.2.1.10.7	Equipment Handling	28
3.2.1.10.8	Reversibility Restrictions	29
3.2.1.10.9	Captive Hardware	29
3.2.1.11	Fault Detection/Isolation	29
3.2.1.11.1	False Alarms	29
3.3	Design and Construction	29
3.3.1	Weight	30
3.3.2	Human Factors	30
3.3.2.1	Handles	30
3.3.3	System Safety	30
3.3.3.1	Nuclear Safety and Certification	30
3.3.4	Thermal Design	30
3.3.4.1	Cooling	30
3.3.4.2	Cooling Air Conditions and Flow Rate	30
3.3.4.3	Supply Air Temperature	30
3.3.4.3.1	Cooling Air Temperature Variation	31
3.3.4.3.2	Start-Up temperature Variation	31
3.3.4.3.3	Water Content	31
3.3.4.3.4	Sand and Dust Content	31
3.3.4.3.5	Resistance to Overcooling	31
3.3.4.3.6	Cooling Air Pressure Loss	32
3.3.5	Electromagnetic Environmental Effects (E3)	32
3.3.5.1	Electromagnetic Interference	32
3.3.5.2	Radiated and Conducted Electromagnetic Environment	32
3.3.5.2.1	Conducted Susceptibility (CS101)	32
3.3.5.2.2	Conducted Emissions (CE102)	32
3.3.5.2.3	Conducted Susceptibility (CS114)	33
3.3.5.2.4	Conducted Susceptibility (CS115)	33
3.3.5.2.5	Conducted Susceptibility (CS116)	33
3.3.5.2.6	Radiated Emissions (RE102)	33
3.3.5.2.7	Radiated Susceptibility (RS103)	33
3.3.5.3	Grounding	33
3.3.5.4	Electrical Bonding Requirements	33
3.3.5.5	Shielding	33
3.3.5.6	Electrostatic Discharge (ESD) Protection	34
3.3.6	Environmental Requirements	34
3.3.6.1	Temperature and Altitude Environments	34
3.3.6.2	Surrounding Air Pressure	36
3.3.6.3	Sand and Dust	36
3.3.6.4	Salt Fog and Spray	36
3.3.6.5	Fungus Resistance	36
3.3.6.6	Explosive Atmosphere	36
3.3.6.7	Humidity, Moisture and Rain	36
3.3.6.8	Vibration Environment	37
3.3.6.9	Mechanical Shock	38
3.3.6.10	Design Loads	40
3.3.6.10.1	Limit Load Factors	40
3.3.6.10.2	Ultimate Load Factors	40
3.3.6.10.3	Fluids	40
3.3.7	Materials, Processes and Parts	41
3.3.7.1	Parts	41
3.3.7.1.1	External Connectors	41
3.3.7.2	Hazardous Materials	41
3.3.7.3	Finish and Colors	41
3.3.8	Interchangeability	41
3.3.9	Product Marking	41
3.3.10	Transportability	42
3.3.11	Service Life	42
3.3.12	Storage	42
3.3.13	Display Processing Software	42
3.3.13.1	Real Time Operating System	42
3.3.13.2	Board Support Package	42
3.3.13.3	Software Development Environment	42
3.3.13.4	Software Development	42
3.3.13.4.1	Software Rehost Effort	43
3.3.13.4.1.1	Code Reuse	43
3.3.13.4.2	Software Development Support	43
4	Quality Assurance Provisions	43
4.1	Verification	43
4.1.1	Methods of Verification	43
4.1.1.1	Test	43
4.1.1.2	Demonstration	43
4.1.1.3	Inspection	44
4.1.1.4	Analysis	44
4.1.1.5	Similarity	44
4.2	Responsibility for Tests	44
4.3	Failure Reporting	44
4.4	Verification Cross Reference Matrix	44
4.5	Test Conditions	51
4.5.1	Ambient Test Conditions	51
4.5.2	Test Tolerances	51
4.5.3	Accuracy of Test Equipment	52
4.6	Types of Verification	52
4.6.1	Test articles	52
4.6.1.1	Acceptance Test	52
4.6.1.1.1	Product Examination	52
4.6.1.1.2	Functional and Qualification Tests	52
4.6.1.1.3	Rejection and retest	52
4.6.1.2	Qualification test	53
4.6.1.2.1	Qualification Certification	53
4.6.1.3	Electrical Power Transient Tests	53
4.6.1.3.1	Normal Electric System Operation	53
4.6.1.3.2	Bus Switching Transients	53
4.6.1.3.3	Abnormal Electric System Operation	54
4.6.1.3.4	Steady State Electric System Operation	55
4.6.1.4	LRU Environmental Tests	55
4.6.1.4.1	Temperature, altitude and cooling air tests	55
4.6.1.4.1.1	Temperature-Altitude Tests	55
4.6.1.5	Inoperative Storage and Warm-Up Tests	57
4.6.1.6	Sand and Dust	59
4.6.1.7	Salt Fog and Spray	59
4.6.1.8	Fungus	59
4.6.1.9	Explosive Atmosphere	59
4.6.1.10	Humidity, Moisture and Rain	59
4.6.1.10.1	Vibration tests	59
4.6.1.10.1.1	Random vibration level test	60
4.6.1.10.2	Gunfire vibration test	60
4.6.1.10.3	Mechanical and Bench Shock tests	60
4.6.1.10.4	Design Loads test	60
4.6.1.10.5	Post Qualification Acceptance Test	60
4.6.1.10.6	Safety of Flight Tests	60
Appendix A.	INTERFACE CONTROL DOCUMENT (ICD) FOR THE F-16 HIGH RESOLUTION PROGRAMMABLE DISPLAY GENERATOR UPGRADE (HRPDG)	62
Appendix B.	CONOPS Document for MLV interface to F-16 HIGH RESOLUTION PROGRAMMABLE DISPLAY GENERATOR (HRPDG)	191

1	SCOPE	1
1.1	Definition of Terms	1
2	APPLICABLE DOCUMENTS	1
2.1	Government Documents	1
2.2	Non-Government Documents	3
3	Requirements	5
3.1	Item Definition	5
3.1.1	Item Diagram	5
3.1.2	Major Components	5
3.1.3	Interface Requirements	7
3.1.4	Mechanical Interfaces	11
3.1.5	Electrical Power Characteristics	12
3.2	Subsystem Performance Requirements	14
3.2.1	Functional Performance	14
3.3	Design and Construction	29
3.3.1	Weight	30
3.3.2	Human Factors	30
3.3.3	System Safety	30
3.3.4	Thermal Design	30
3.3.5	Electromagnetic Environmental Effects (E3)	32
3.3.6	Environmental Requirements	34
3.3.7	Materials, Processes and Parts	41
3.3.8	Interchangeability	41
3.3.9	Product Marking	41
3.3.10	Transportability	42
3.3.11	Service Life	42
3.3.12	Storage	42
3.3.13	Display Processing Software	42
4	Quality Assurance Provisions	43
4.1	Verification	43
4.1.1	Methods of Verification	43
4.2	Responsibility for Tests	44
4.3	Failure Reporting	44
4.4	Verification Cross Reference Matrix	44
4.5	Test Conditions	51
4.5.1	Ambient Test Conditions	51
4.5.2	Test Tolerances	51
4.5.3	Accuracy of Test Equipment	52
4.6	Types of Verification	52
4.6.1	Test articles	52
Appendix A.	INTERFACE CONTROL DOCUMENT (ICD) FOR THE F-16 HIGH RESOLUTION PROGRAMMABLE DISPLAY GENERATOR UPGRADE (HRPDG)	62
Appendix B.	CONOPS Document for MLV interface to F-16 HIGH RESOLUTION PROGRAMMABLE DISPLAY GENERATOR (HRPDG)	191
1	Scope	197
2	Applicable Documents	197
2.1	Government Documents	197
2.1.1	Customer	197
2.1.2	Military	197
2.2	Non-Government Documents	197
2.2.1	General Dynamics	197
2.2.2	Other Publications	197
3	Overview	197
4	Concept of Operations	197
5	Security	198
6	Interface Hardware	198
7	File Transfer Protocol	199
8	OFP and Map loading	199
9	Pilot / Maintainer Interaction with MLV	200
10	Mission Planning Map Creation	200
11	OFP disk creation	201
Appendix C.	INTERFACE CONTROL DOCUMENT (ICD) FOR THE BLOCK 30 ACMFD	203
Appendix D.	Subsystem Requirements Document (SSRD) for F-16 High Resolution Programable Display Generator Advanced Processing (HRPDG+)	227
1	Scope	228
1.1	Definition of Terms	228
2	Applicable Documents	228
2.1	Government Documents	228
3	Requirements	228
3.1	Item Definition	228
3.2	Advanced Processing Functions	228
3.2.1	Advanced Processor Start-up	228
3.2.2	Advanced Processor Built-in-test	229
3.2.3	Advanced Processor Dynamic Link	229
3.2.4	Advanced Processor Cyber and Cryptographic	229
3.2.5	Advanced Processor System I/O Communications	229
3.2.6	Advanced Processor Throughput	229
3.2.7	Advanced Processor Memory	230
3.2.8	Advanced Processor Memory Zeroize	230
3.2.9	Advanced Processor Reset/Shutdown	230
3.2.10	Advanced Processing Software	230
3.3	Thermal Design	231
3.3.1	Cooling	231
3.4	Electromagnetic Environmental Effects (E3)	233
3.4.1	Electromagnetic Interference	233
3.5	Environmental Requirements	235
3.5.1	Temperature and Altitude Environments	235
3.5.2	Surrounding Air Pressure	236
3.5.3	Sand and Dust	237
3.5.4	Salt Fog and Spray	237
3.5.5	Fungus Resistance	237
3.5.6	Explosive Atmosphere	237
3.5.7	Humidity, Moisture and Rain	237
3.5.8	Vibration Environment	238
3.5.9	Mechanical Shock	239
3.5.10	Design Loads	241
3.5.11	Fluids	241
4	Quality Assurance Provisions	242
4.1	Verification	242
4.1.1	Methods of Verification	242
4.2	Responsibility for Tests	243
4.3	Failure Reporting	243
4.4	HRPDG+ Verification Cross Reference Matrix	243
4.5	Test Conditions	246
4.5.1	Ambient Test Conditions	246
4.5.2	Test Tolerances	246
4.5.3	Accuracy of Test Equipment	246
4.6	Types of Verification	247
4.6.1	Test articles	247

LIST OF FIGURES

Figure 1: HRPDG System Interfaces	6
Figure 2: HPRDG Cooling Air Flow Rate	31
Figure 3: F-16 Airborne Electronic Ventilation Bay Equipment Temp vs Alt	35
Figure 4: Non-Gun-firing Vibration Test Levels (Random Vibration)	37
Figure 5: Gunfire Vibration Test Levels	38
Figure 6: Shock Test Requirements	39
Figure 7: MLV Process Diagram	198
Figure 8: HRPDG Boot up Behavior	200
Figure 9: HPRDG Cooling Air Flow Rate	232
Figure 10: F-16 Airborne Electronic Ventilation Bay Equipment Temp vs Alt	236
Figure 11: Non-Gun-firing Vibration Test Levels (Random Vibration)	239
Figure 12: Gunfire Vibration Test Levels	239
Figure 13: Shock Test Requirements	240

LIST OF TABLES

Table 1: HRPDG Electrical Interfaces	7
Table 2 Block 30 CMFD Power Requirements	8
Table 3: Table 3: MFD Configuration Bits	20
Table 4: HRPDG Quantitative Supportability Performance Requirements	28
Table 5: Maximum Air Pressure Loss	32
Table 6: Verification Cross Reference Matrix (VCRM)	45
Table 7: Temperature-Altitude Test Conditions	57
Table 8: Maximum Air Pressure Loss	233
Table 9: Temperature-Altitude Test Conditions	251

SCOPE

This specification establishes the performance and test requirements for the F-16 High Resolution Programmable Display Generator (HRPDG) subsystem.

Definition of Terms Shall – identifies a mandatory and contractual requirement. Requirements identified by “shall” require metrics to quantify compliance and require a formal verification process.

APPLICABLE DOCUMENTS

Government Documents The following documents of the exact issue shown form a part of this specification to the extent specified herein. In the event of conflict between the documents referenced herein and the contents of this specification, the contents of this specification shall be considered as superseding requirements.

Military

MIL-E-5400T 16 Nov 1979

Electronic Equipment, Airborne, General Specification for

MIL-A-8243D 26 Oct 1985

Anti-icing and De-icing – Defrosting Fluid

MIL-STD-108E

Notice 1 19 Sep 1985 Definitions of and Basic Requirements for Enclosures for Electric and Electronic Equipment

MIL-STD-210C 9 Jan 1987
Climatic	Information	to	Determine	Design	and	Test Requirements for Military Systems and Equipment

MIL-STD-461F 10 Dec 2007

Requirements for the Control of Electromagnetic Interference Characteristics of Subsystems and Equipment

MIL-STD-704A 9 Aug 1966

Electric Power, Aircraft Characteristics, and Utilization of

MIL-STD-810G

w/Change 1 15 April 2014 Environmental Engineering Considerations and Laboratory Tests

Military

MIL-STD-882E 11 May 2012

Department of Defense Standard Practice, System Safety

MIL-STD-1472G 11 Jan 2012

DoD Design Criteria Standard - Human Engineering

MIL-STD-1553B

Notice 2 8 Sept 1986 Aircraft Internal Time Division Command/Response Multiplex Data Bus

MIL-HDBK-454B 15 Apr 2007

DoD Handbook - General Guidelines for Electronic Equipment

MIL-STD-130N 16 Nov 2012

DoD Standard Practice, Identification Marking of U.S. Military Property

MIL-STD-1285D

w/Change 1 10 Nov 2010 DoD Standard Practice, Marking of Electrical and Electronic Parts

AMS-STD-595A

February 2017 Colors Used in Government Procurement

Other Publications

IEEE 802.3

28 Dec 2012 IEEE Standard for Ethernet

CNSSI 1253

27 March 2014 Security Categorization and Control Selection for National Security Systems

MISB RP 0804.3

Sept 2010 Real-Time Protocol (RTP) for Full Motion Video

RFC 3550

July 2003 RTP: A Transport Protocol for Real-Time Applications

RFC 3551

July 2003 RTP Profile for Audio and Video Conferences with Minimal Control

RFC 3984

February 2005 RTP Payload Format for H.264 Video

RFC 2326

April 1998 Real Time Streaming Protocol (RTSP)

Other Publications

RFC 2327

April 1998 SDP: Session Description Protocol

RS-170 Nov 1957
Electrical	Performance	Standards-Monochrome	Television Studio Facilities

AFMAN 91-118

4 Aug 2010 with Change 1 21 June 2011 Nuclear Surety Safety Design and Evaluation Criteria for Nuclear Weapon Systems

AFMAN 91-119

5 June 2012 with Change 1 23 April 2013 Nuclear Surety Safety Design and Evaluation Criteria for Nuclear Weapon Systems Software

Non-Government Documents The following documents of the exact issue shown form a part of this specification to the extent specified herein. In the event of conflict between the documents referenced herein and the contents of this specification, the contents of this specification shall be considered as superseding requirements.

SPECIFICATIONS

Lockheed Martin

16PP4166A

Current revision Signal Interface Control Document for the F-16 Avionic System M6.5

16PP967D

1 August 1995 F-16 Multiplex Bus and Standard Signal Interface Requirements

16ZE964C

05 May 2002 Prime Item Development Specification for the Color Programmable Display Generator (CPDG)

16ZE123C

22 Aug 1985 Prime Item Development Specification for the Multifunction Display Set on the F-16 Aircraft

16ZE962A 26 June 2000

Prime Item Performance Specification for the Common Color Multifunction Display

16VE964003C

11 September 2003 PDG Chassis

16VE123004F

1 September 1995

PDG Tray

16PS011E

13 December 1994

Environmental Criteria for the F-16

C21061

Specification Control Drawing: CONNECTOR, OCTAX,

SPECIFICATIONS

Lockheed Martin

Current Revision

RECEPTICAL, DUEL SHELL SIZE 11

C21071 Current Revision Specification Control Drawing: CONNECTOR, OCTAX,RECEPTACLE, SHELL SIZE 25

C21077 Current Revision Specification Control Drawing: CONNECTOR, OCTAX, RECEPTACLE, SHELL SIZE 19

Requirements Section 3 contains the performance, software, mechanical and environmental requirements for the F- 16 High Resolution Programmable Display Generator Upgrade (HRPDG) subsystem.

Item Definition The primary head down display system of the F-16 is comprised of a HRPDG and multiple Color Multifunction Displays (CMFDs). The primary head-down display system is the man-machine interface to the pilot for situational awareness, control and activation of aircraft weapons and sensors. The HRPDG provides air vehicle general processing and display graphics processing capabilities for the CMFDs. The HRPDG generates, scales, organizes and positions both symbology and/or sensor video in accordance with the mode selected by the pilot. These modes can be selected though interactive software controlled buttons/switches located on each of the CMFD bezels and other aircraft controls.

The HRPDG is envisioned to be compatible with the existing F-16 Block 40/52 Common CMFDs (CCMFD) and Central Display Units (CDU) as well as the F-16 Block 30 Color Multifunction Displays (CMFDs). Throughout this document the term CMFD will be used to when referencing the CCMFDs, CDUs or CMFDs.

On the Mil-STD-1553 network the HRPDG is primarily role is a remote terminal (RT) and its secondary role is as a backup-bus controller (BBC) in the event the bus controller (BC) fails.

Item Diagram A functional block diagram illustrating the primary interfaces between the HRPDG, the aircraft and other avionics subsystems is presented in Figure 1.

Major Components The HRPDG consists of the following Line Replaceable Units (LRUs):

A. Programmable Display Generator

Figure 1: HRPDG System Interfaces

Interface Requirements Electrical The HRPDG subsystem shall -1 provide the electrical interfaces described within this specification, as shown in Table 1 and as defined in the Interface Control Document 16PP4166A, Appendix A and Appendix C.

Table 1: HRPDG Electrical Interfaces Aircraft Power

Signal Description

Signal Quantity

Inputs

28 VDC

115 VAC, 400Hz, 3 Phase

AC Neutral

AC Safety Ground

Outputs

28 VDC

30 VDC

Data Interfaces

MIL-STD-1553

Gigabit Ethernet

RS-422

UART

Mass Storage

Discrete Interfaces

Inputs

High-Level

Low-Level Complementary

Open/Ground

Outputs

Low-Level Complementary

Special Low-Level Complementary

Video Interfaces

Inputs

RS-170A (color & mono)

Outputs

RS-170 RGB/A (color)

NTSC RS-170A (color)

NTSC RS -170 (mono)

DVI

Electrical Power Interfaces The HRPDG will interface to the aircraft’s primary and secondary power sources. The primary power source is the aircraft’s 3 phase 115 VAC 400 Hz power bus. The secondary power source is the aircraft’s +28 VDC power bus. The HRPDG will provide a low voltage power supply which will generate the required internal electrical voltages. This low voltage power supply will also supply the Block 40/50 CMFD +30 VDC CMFD display power and optionally any voltages required to operate the Block 30 CMFDs.

Input The HRPDG’s primary power input shall [-1] be 3 phase 115 VAC 400 Hz MIL-STD-704 aircraft power. The HRPDG’s secondary power input shall [-2] be +28 VDC aircraft power.

Output The HRPDG shall [-1] provide a +28 VDC pass through capability to a maximum of four (4) CMFDs to operate the display heaters per 16ZE964 and 16ZE962.

Note: The maximum heater power draw at 28VDC per CMFD is 138 Watts per 16ZE962.

The HRPDG shall [-2] provide +30 VDC to a maximum of four (4) CMFDs for display operation per 16ZE964 and 16ZE962.

Note: The maximum power draw at 30 VDC is modified from 16ZE964 to 65 Watts.

The HRPDG shall [-3] provide the capability to supply the voltages and power levels identified in Table 2 below to each Block 30 CMFD

Table 2 Block 30 CMFD Power Requirements Block 30 CMFD Power Requirements

Function

Supply Voltage

Power

Max Bright w/o Heaters

115 VAC

55 W

Max Bright with Heaters

115 VAC

180 W

Serial Communications Interfaces Serial communication between the HRPDG and other F-16 avionics subsystems will be accomplished using a combination of MIL-STD-1553 and 1553B (includes backwards compatibility with the base MIL-STD-1553), High Speed Network, and RS-422 communications.

MIL-STD-1553B Serial Bus The HRPDG shall [-1] provide 5 dual-redundant mux bus interfaces.

Each mux bus interface shall [-2] be capable as acting as a RT and BBC, as defined in section 3.2.1.2.2.1 1553 Modes

Each mux bus interface shall -3 conform to the requirements of MIL-STD-1553B as modified by 16PP967 section 4.1.4.1.

The MIL-STD-1553 mux bus interfaces shall [-4] comply with the requirements defined in 16PP967 and Appendix A.

Inter-message gap When in BBC mode, the HRPDG programmable inter-message gap range shall [-1] be between 4 microseconds to 35 microseconds in 1 microsecond increments.

Note: The Inter-message Gap time is set at compile time and is varies on a message by message basis.

No Response Time-Out When in BBC mode, the HRPDG shall [-1] provide the capability to configure the transmitting Remote Terminal No Response Time-Out value for each MUX bus to be a minimum of 14 or 30 microseconds. (1553B/1553).

High Speed Network Interface

The HRPDG shall [-2] provide four (4) interfaces compliant to IEEE 802.3-2002 10/100/1000 Base T Ethernet.

RS-422 Interface The HRPDG Shall [-1] provide two (2) RS-422 compliant interfaces

Universal Asynchronous Receiver Transmitter Interface The HRPDG shall [-1] provide one (1) UART interface for communications from each CMFD as defined in Appendix A and Appendix C.

Discrete Interfaces Discrete Inputs High-Level Discretes The HRPDG shall [-1] provide a minimum of four (4) High Level Single-Ended discretes compliant to 16PP967 & Appendix A.

The HRPDG shall [-2] provide a minimum of four (4) High Level Single-Ended discretes complaint to Appendix A discretes titled “Special High-Level Discrete”.

Low Level Complementary Discretes The HRPDG shall [-1] provide a minimum of seven (7) low level complementary discretes compliant to 16PP967 & Appendix A.

Open/Ground Discretes The HRPDG shall [-1] provide a minimum of thirteen (13) open/ground single-ended discretes compliant to 16PP967 & Appendix A.

Discrete Outputs

Low Level Complementary Discretes The HRPDG shall [-1] provide a minimum of One (1) low level complementary discretes compliant to 16PP967 and Appendix A.

The HRPDG shall [-2] provide a minimum of Four (4) special low level complementary discretes compliant to Appendix A for MFD Reset.

Video Interfaces The HRPDG shall [-1] provide all the necessary synchronization and control signals required to support each video input and output type defined within this section, per 16ZE964, 16PP967,Appendix A and Appendix C.

Video Inputs

RS-170 & A

The HRPDG shall [-3] provide six (6) color video inputs compliant to RS-170A as modified by 16PP967.

Each of the HRPDG RS-170A video input channels shall [-4] be user configurable to support RS- 170A color and RS-170 monochrome video modified by 16PP967 and Appendix A.

Note:

The RS-170 and 170A inputs modifications may include but not limited to load impedance, bandwidth, sync and timing, reference 16PP967 and Appendix A for details.

Video Outputs

RS-170 RGB

The HRPDG shall [-1] provide four (4) independent RGB video output drivers compliant to RS-170, as modified by Appendix A, Appendix C and 16PP967.

Sync information shall [-2] be carried on the green channel signal.

The RS-170 RGB video outputs shall [-3] support video synchronization, and other controls required by the displays as defined in Appendix A and Appendix C.

In the absence of a video input or sync the HRPDG shall [-4] automatically generate a video signal containing the HRPDG internally generated symbology.

Each of the RS-170 RGB video outputs shall [-5] provide the ability to be independently commanded to display color or monochrome imagery on the respective green video channel.

The monochrome imagery shall [-6] be a combination of the following RGB signals 30% red, 59% green, and 11% blue.

NTSC RS-170/170A

The HRPDG shall [-1] provide three (3) color NTSC RS-170A composite video outputs as modified by Appendix A and 16PP967.

Each of the NTSC RS-170A composite video channels shall [-2] provide the capability to independently mirror two (2) of the four (4) RS-170 RGB outputs and one (1) of the two (2) DVI video outputs.

The HRPDG video mirroring function shall [-3] be user selectable, via software, to determine which video channels to mirror.

Note:

The RS-170, 170A, and RS-170 RGB output modifications may include but not limited to load impedance, bandwidth, sync and timing, reference 16PP967 and Appendix A for details.

DVI

The HRPDG shall [-2] provide six (6) DVI outputs compliant to DVI-D standard. The HRPDG must provide the ability to switch each D

Mechanical Interfaces The HRPDG chassis (including provisions for mounting, cooling and electrical wiring) maximum mechanical envelope shall [-1] be 6.30 in. (W) x 7.66 in. (H) x 17.67 in. (D) reference specification control drawing 16VE964003.

Mounting Tray The HRPDG chassis shall [-1] conform to the existing F-16 PDG mounting tray’s mechanical and structural requirements (including provisions for mounting, cooling and electrical wiring) as defined in 16VE123004.

Support Interface Access Any Vendor or Depot level support interfaces shall [-1] only be accessible with the HRPDG chassis access cover removed.

The HRPDG production configuration shall [-2] ensure JTAG compliant interface(s) are disabled at the factory prior to delivery.

Growth Provisions The HRPDG chassis and backplane shall [-1] provide Four (4) growth slots with electrical connections and mechanical interfaces to allow the addition of both processing and mass storage module(s) without modification to the internal HRPDG chassis, backplane, and power supply.

The growth slots shall [-2] only be accessible by removing the HRPDG cover.

The mass storage module shall [-3] provide a minimum read transfer rate of 4 Gbit/sec and a write transfer rate of 2.4 Gbit/sec.

Electrical Power Characteristics The HRPDG shall [-1] meet all specified requirements of MIL-STD-704 for the types of power specified within this specification.

The HRPDG shall -2 meet all specified requirements of MIL-STD-704 for the 3-phase, 115 VAC, 400 Hz power and the 28 VDC discretes specified herein.

The HRPDG shall -3 provide specified performance when supplied with electrical power with the characteristics and within the limits defined in MIL-STD-704, category B, except as specified herein.

Power System The HRPDG will derive all HRPDG internal voltages from the aircraft’s 3 phase 115 VAC 400 Hz power bus. In addition, the HRPDG will contain a low voltage power supply capable of providing 30 VDC to each of the 4 CMFDs for display operation and provide a +28 VDC pass through capability to operate CMFD display heater.

Internal Power Supply The HRPDG internal power supply shall -1 provide all the required voltages necessary to operate the HRPDG and up to four (4) CMFDs as defined herein and in 16ZE123 and 16ZE962.

The HRPDG internal power supply shall [-2] provide a maximum of 385 watts for the internal electronics of the HRPDG; this excludes any power required to drive the CMFDs.

Block 40/50 Display Support +30 VDC Display Power The HRPDG internal power supply shall [-1] provide +30 VDC to a maximum of four (4)CMFDs.

The HRPDG +30 VDC output shall [-2] be capable of supplying a maximum of 65 watts to each CMFD.

+28VDC Display Heater Power The HRPDG +28 VDC output shall [-1] be capable of passing through a maximum of 140 watts to each CMFD display heater

Block 30 Display Support The HRPDG internal power supply shall [-1] provide a pass through capability to provide 115 VAC required for operation of four (4) Block 30 CMFDs, per Table 2.

Steady State and Transient Operation Normal Power Transients The subsystem shall -1 provide specified performance when the prime power inputs and discretes originating from an aircraft power bus are within the normal electrical system operation limits specified by MIL-STD-704.

Abnormal Transients When input power and discretes originating from any aircraft power bus are exposed to the abnormal transients limits specified in MIL-STD-704 the subsystem shall [-1] automatically recover and provide full performance, as specified herein, without recycling the input power or re-initialization once the abnormal condition has been removed.

The subsystem shall [-2] remain safe during and after exposure to the abnormal transients limits specified in MIL-STD-704.

Power Interruptions The equipment shall -1 not be damaged by any combination of normal or abnormal power interruptions of any duration, or by any combination of interruptions of one or more phases of the AC voltage.

When power returns within the normal requirements of MIL-STD-704, the equipment shall -2 automatically resume normal operation in an orderly manner within the start-up time requirements of Section 3.2.1.4.

In the event of a power interruption of up to 50 mSec, the equipment shall [-3] continue normal operation without restarting. Power to the CMFDs may [4] be switched off during the power interrupt condition.

Subsystem Performance Requirements Functional Performance The HRPDG shall [-1] support the CMFD video driver requirements defined within this specification and described in 16ZE123 and 16ZE964.

System Video Latency

The HRPDG analog and digital video latency shall [-2] be less than 100 milliseconds under the worst case system load condition.

The worst case system load conditions are defined to occur when the HRPDG networks (1553 and Ethernet), analog, digital and analog video interfaces, and decompression and video processing engines are operating at maximum capacity.

Digital video latency is defined as the time between the arrival of the last pixel of a H.264/AVC compressed video packet (non-interlaced 768 x 1024 image at a frame rate of 60 Hz) is received at the HRPDG Ethernet interface until the first pixel of the video stream is processed and available for presentation at the desired HRPDG video output. Processed in the above statement includes all temporal and spatial functions and operations the system is required to perform to process the incoming video packet including but not limited to buffering, decompression, video conversion (RGB,RS170, DVI or STANG 3350), rotation, cropping, and overlaying of symbology or imagery.

Viper MLV The HRPDG shall [-1] provide the capability to interface to the Viper MLV support equipment via High Speed Network interfaces.

All HRPDG OFPs shall [-2] be loadable by the Viper MLV through the high speed network.

The HRPDG shall [-3] support the capability to load all software images via the High Speed Network interfaces.

The HRPDG shall [-4] support the capability to load firmware images by the Viper MLV via the High Speed Network interfaces.

System Processes The HRPDG shall [-1] support a General Processing Function (GPF) and Display Processing Function (DPF).

General Processing Function The HRPDG General Processing Function (GPF) shall [-1] include instructions, memory, interface and other necessary features to enable accomplishment of the following:

1.1.1.1.1.1. Symbol table build-up and sorting,

1.1.1.1.1.2. Logic associated with switch interpretation,

1.1.1.1.1.3. Interface data and control command to the Display Processor Function,

1.1.1.1.1.4. Interface with the multiplex data bus,

1.1.1.1.1.5. Interface with symbol intensity, display contrast, and display brightness,

1.1.1.1.1.6. General avionics processing.

System I/O Communications Processes

1553 Modes The HRPDG shall [-1] provide the capability to allow application software to determine the MIL-STD- 1553 interface operational mode, BBC, or RT, as defined in Appendix A and 16PP967.

CMFD UART Communication Processes The HRPDG shall [-1] use the UART interface/channel for CMFD command, control and status as described in Appendix A and Appendix C.

The HRPDG shall [-2] be capable of independently communicating to each of the four (4) CMFDs over a dedicated UART interface.

CMFD Switch/Control Response The HRPDG shall [-1] receive information from CMFD peripheral switches/controls located on the bezel of each CMFD via the serial UART interface.

The HRPDG will be capable of responding as necessary to any switch/control action from any display. This switch/control information shall [-2] be available to the HRPDG system function process.

In addition, the switch/control information shall [-3] identify which switch/control has been depressed on each of the displays.

The time to refresh each display’s switch information state shall [-4] be less than 100 msec.

Ethernet Protocols The HRPDG Ethernet interfaces shall [-1] support the following: Transmission Control Protocol/Internet Protocol (TCP/IP) and User datagram Protocol (UDP) protocols, Real-Time Protocol (RTP) MISB RP 0804.3 and RFCs 3550,3551, and 3984, Real Time Steaming Protocol (RTSP – RFC 2326), Internet Protocol V4 (IPV4) Session Description Protocol (SDP – RFC2327)..

Display Function Processing

The HRPDG display function processing will be provided by the HRPDG supplier.

Graphics Support The HRPDG Graphics Processor shall [-1] be compatible with OpenGL ES SC 1.0 standard. The OpenGL graphics library shall [-2] support the development of 2D graphics elements.

The OpenGL graphics library shall [-3] support the development of 3D graphics elements.

Display Processing Functions The display processing function shall [-1] accomplish the following allocated tasks:

a) Symbol generation

b) Symbol rotation

c) Symbol positioning

d) Format storage, integration, and data consistency

e) Decoding and processing of symbol control data received from system function

f) Hardware interaction/control processing

Image Canvas/Display Formats The display processing function shall [-1] provide one (1) scalable symbology, character and video image canvas.

The image canvas shall [-2] provide the capability to generate and render the following display image formats:

a) 4 - 482 x 482 and 2 - 768 x 1024

b) 4 - 768 x 768 and 2 - 768 x 1024

Display Resolution The HRPDG shall [-1] provide the capability to independently support the following display resolutions: a) 4 - 482 x 482 via RS-170

b) 2 - 768 X 1024 via DVI-D

c) 4 - 768 x 768 via DVI-D

Start-Up

Note:

There is a 1 pixel wide border as part of the 482x482 format. This leaves only 480x480 pixels for display.

HRPDG On/Off Discrete

The HRPDG shall [-1] provide the capability to be remotely powered On/Off via an external discrete as defined in Appendix A.

Cold Start The HRPDG shall [-1] perform and complete a self-test of the general processing hardware and pass control to application software boot code within 10 seconds of power being supplied to the unit. Note: An allowance of 1 sec is allowed for measurement uncertainty if timing with a manual method (stopwatch).

The HRPDG shall [-4] be fully operational and provide full performance as defined within this specification within 30 seconds of the application of power.

In the event a power interruption is greater than 50 msec the HRPDG shall [-5] undergo a cold start (re-initialization) and be operational within 30 seconds.

Self-Test/Built-In-Test The HRPDG shall [-1] provide a Self-Test/Built-In-Test (ST/BIT) capability as defined below:

Start-Up/Power-On-Bit The HRPDG shall [-1] provide a subsystem level start-up self-test (SBIT) capability which verifies the functionality of the HRPDG hardware. SBIT shall complete within 5 seconds of initiation.

Periodic BIT The HRPDG shall [-1] provide a subsystem level continuous self-test capability which verifies the functionality of the HRPDG hardware during operation.

PBIT shall [-2] be executed as a background task and complete within 20 seconds of initiation.

Initiated BIT The HRPDG shall [-1] provide a subsystem level user initiated self-test capability which verifies the functionality of the HRPDG hardware.

The HRPDG IBIT shall [-2] consist of only non-destructive tests.

The HRPDG shall [-4] provide the functionality (hardware, firmware, and/or software) to allow the OFP to perform the following IBIT tests:

· MFDS bezel button depression tests

· MFDS contrast, brightness, gain and symbol tests

· MFDS color pallet tests

· MFDS pixel tests

Upon receipt of an IBIT request the HRPDG shall [-5] initiate IBIT tests within 2 seconds.

Dynamic Link The HRPDG shall [-1] support a dynamic link capability.

The HRPDG dynamic link process shall [-2] be available for Buyer applications (i.e. OFP) at the completion of subsystem-level SBIT.

Upon successful completion of the dynamic link process the HRPDG shall [-3] assert a Supplier defined flag to notify readiness to receive any Buyer developed applications.

The HRPDG shall [-4] execute Buyer applications (i.e. OFP) only in volatile RAM.

Display Driver Capabilities

Display Channels Each channel shall [-1] include video synchronization, and other necessary control signals required by the display.

Video Switching The HRPDG shall [-1] provide a video switching capability, capable of routing a minimum of seven (7) independent video inputs (internally or externally generated) to a minimum of six (6) independent video outputs simultaneously.

The video switch shall [-2] provide the capability to determine the switch’s input and output routing via software control.

A multi-channel video processing capability shall [-3] allow independent (unsynchronized) video signals to be presented (along with their appropriate symbology and/or imagery overlay) on each of the display channels simultaneously.

The HRPDG shall [-4] be capable of selectively routing any video input to any video output for presentation on a single, or any combination of display channels.

The HRPDG shall [-5] provide independent switching capability, turn output signals on and off, for all DVI video outputs via software control during runtime.

Video Decompression

The HRPDG shall [-1] provide the capability to decompress a one (1) MPEG-2 compressed video stream received via RTP.

The HRPDG shall [-2] provide the capability to decompress one (1) MPEG-4/H.264/AVC video stream received via RTP.

The MPEG-4/H.264/AVC decoder/algorithm shall [-3 ] support decoding tools conforming to the H.264 High Profile, without B-Frame support, and Level 4.1 video streams.

The HRPDG shall [-4] provide the capability to simultaneously decode/decompress two (2) compressed video streams received via RTP. The compressed video streams shall [-5] consist of one (1) MPEG -2 and one (1) MPEG-4/H.264/AVC video streams.

The HRPDG shall [-6] provide the capability to simultaneously decode/decompress two (2) MPEG- 4/H.264/AVC video streams received via RTP.

Symbology and Video The HRPDG shall [-1] be capable of generating symbols while simultaneously processing video for display.

The HRPDG shall [-2] provide the capability to overlay internally or externally generated symbology and imagery on up to six (6) independent active video stream(s) or image(s).

Symbology and/or imagery shall [-3] be overlaid on any user defined video stream.

A video signal which contains symbology and/or imagery generated within the HRPDG shall [-4] be provided in the absence of any external video input or syncs.

External Video Noise Rejection The common-mode noise signal inputs with up to 3 volts peak-to-peak (Vpp) amplitude occurring at both terminals of the HRPDG video input connectors and having equal amplitude and phase at both terminals shall [-1] be attenuated as follows:

Frequency	Attenuation
0 to 10,000 Hz	50 dB minimum
above 10,000 Hz	Maximum consistent with other
	requirements of this specification

No damage to the HRPDG shall [-2] occur due to the presence of spurious video, white “hot spots” of 6 volts amplitude of less than five (5) microseconds duration.

The HRPDG shall [-3] present a normal video image in the presence of “hot spots” as defined above.

CMFD Configuration Discretes The HRPDG’s Configuration bits defined in Appendix A shall [-1] conform to the following table:

Table 3: Table 3: MFD Configuration Bits

Input

Ground Logic

Open Logic

CONF 0

Front CDU Present

No Front CDU

CONF 1

Aft MFDs Present

No Aft MFDs

CONF 2

Aft CDU Present

No Aft CDU

CONF 3

Block 30 Aircraft

Not Block 30 Aircraft

CONF 4

Block 40 Aircraft

Not Block 40 Aircraft

CONF 5

High Resolution MFD

Standard Resolution MFD

Moving Map

The HRPDG shall [-1] support a color moving map display.

The moving map shall [-2] be displayed below any existing symbology.

The moving map shall [-3] be available for display on any video channel identified within this specification.

The moving map shall [-4] provide centering options on own ship position, on steer-point, or on cursor location, or depressed mode.

As a minimum the moving map shall [-5] be capable of loading and displaying the following map types:

a. 1:5M

GNC (Global Navigation Chart)

b. 1:2M

JNC (Jet Navigation Chart)

c. 1:1M

ONC (Operation Navigation Chart)

d. 1:500K

TPC (Tactical Pilotage Chart)

e. 1:500K

LFC (Low Flying Chart)

f.	1:250K
TFC (Transit Flying Chart)

g. 1:250K

JOG (Joint Operations Graphic - Air)

h. 1:100K

TLM (Topographic Line Map)

i.	1:50K
TLM (Topographic Line Map)

j.	Level 1
DTED (Digital Terrain Elevation Data)

k. 10m

CIB (Controlled Image Base) (Satellite images)

l.	5m
CIB (Controlled Image Base) (Satellite images)

m. 1m

CIB (Controlled Image Base) (Satellite images)

The moving map function shall [-6] support the following features:

a) Display Modes

a. 2D and 3D Views

b) Map Underlay using

a. Compressed Arc Digitized Raster Graphics

b. Enhanced Compressed Raster Graphics

c. [Removed]

d. GeoTIFF

e. Digital Terrain

c) Map Overlays

a. Slope Shading

b. Contour Lines

c. Elevation Bands

d. Height Above Terrain

d) Object Visibility

e) Ownship Visibility

f) GeoChips Cyber Security Requirements The HRPDG shall [-1] be compliant to following CNSSI 1253 impact definitions:

Confidentiality: Low Integrity: Moderate Availability: Moderate

The HRPDG shall [-2] comply with Cyber Security requirements as required for the impact definitions defined above.

The HRPDG mass storage device shall [-5] support Advanced Encryption Standard (AES)-256 (minimum) encryption.

Cryptographic Services HRPDG Cryptographic Services shall [-1] provide the user access to the hardware accelerated security features identified within this section.

The HRPDG Cryptographic Services shall [-2] provide the capability for the user to import and export user encrypted files.

Cryptographic Files The HRPDG shall [-1] provide the capability for the user to create and store encrypted files in SSD.

The HRPDG shall [-2] provide the user the capability to apply a digital signature (identified below) to encrypted files.

Elliptic Curve Cryptography The HRPDG shall [-1] support all defined elliptic curve functions with the following elliptic curves:

Curve Name

Description

secp224r1

NIST/SECG curve over a 224 bit prime field

secp384r1

NIST/SECG curve over a 384 bit prime field

secp521r1

NIST/SECG curve over a 521 bit prime field

prime192v1

NIST/X9.62/SECG curve over a 192 bit prime field

prime256v1

X9.62/SECG curve over a 256 bit prime field

sect163k1

NIST/SECG/WTLS curve over a 163 bit binary field

sect233k1

NIST/SECG/WTLS curve over a 233 bit binary field

sect283k1

NIST/SECG curve over a 283 bit binary field

sect409r1

NIST/SECG curve over a 409 bit binary field

sect571r1

NIST/SECG curve over a 571 bit binary field

HRPDG shall [-2] support the ability to sign and verify files via Elliptic Curve Digital Signature Algorithm (ECDSA).

The HRPDG shall [-3] support key agreement via Elliptic Curve Diffie-Hellman (ECDH) The HRPDG shall [-4] support key generation via ECDSA and ECDH.

The HPPDG shall [-5] support timing-equalized versions of ECDSA sign and key generation.

The HRPDG shall [-6] support the following Elliptic curve functions point add, point double, point multiply, timing equalized version of point multiplication, prime file and binary polynomial field functions.

Cryptographic Authentication The HRPDG shall [-1] support SHA-256, SHA-384 and SHA-512 hashing algorithms.

The HRPDG shall [-2] support hashed based message authentication code (HMAC) for SHA-256, SHA 384 and SHA-512 hash algorithms.

Symmetric Key Block Ciphers The HRPDG shall [-1] support AES…

This is the start of the file's text. The full file is on GovTribe.

File details come from the government source that posted it. Updated Apr 22, 2026.