NIST CHIPS MFGUSA NOFO.pdf

NOTICE OF FUNDING OPPORTUNITY (NOFO)

CHIPS Manufacturing USA Institute Competition

Executive Summary

Federal Agency Name: National Institute of Standards and Technology (NIST), United States Department of Commerce

Funding Opportunity Announcement Title: FY2024 CHIPS Manufacturing USA Institute Competition

Funding Opportunity Announcement Type: Initial

Funding Opportunity Announcement Number: 2024-NIST-CHIPS-MFGUSA-01

Assistance Listing Number(s): 11.042 – CHIPS R&D

Funding Opportunity Description: This NOFO seeks proposals from eligible applicants for activities to establish and operate a CHIPS Manufacturing USA Institute focused on digital twins with integrated physical assets and computational capabilities (digital assets) to tackle important semiconductor-industry manufacturing challenges. The CHIPS Manufacturing USA Institute will join an existing network of seventeen Institutes designed to increase U.S. manufacturing competitiveness and promote a robust R&D infrastructure. The Institute will manage a portfolio of Institute-led projects and competitively funded Member-led projects, including Education and Workforce Development (EWD) activities, basic and applied research, and technology demonstrations.

Dates: Relevant dates in the application process are listed in Table 1 and described in the text that follows.

The Department of Commerce may amend this NOFO at any time. It may also close the NOFO with at least 60 days’ notice. Changes will be communicated via https://www.grants.gov and https://www.chips.gov.

Table 1. Chips Digital Twin Manufacturing USA Institute NOFO Key Dates

Webinar Information Session May 8, 2024 Proposers Day May 16, 2024 Concept Paper Due June 20, 2024 Invited Full Applications Due September 9, 2024 https://www.grants.gov/ https://www.chips.gov/

Webinar Information Session: The National Institute of Standards and Technology (NIST) CHIPS Research and Development Office (CHIPS R&D) will host an informational webinar on May 8, 2024, to provide general information regarding this NOFO, offer general guidance on preparing applications, and answer questions. Proprietary technical discussions about specific project ideas will not be permitted during the webinar, and CHIPS R&D staff will not critique or provide feedback on specific project ideas while they are being developed by an applicant, brought forth during the webinar, or at any time before the deadline for all applications. However, questions about the NOFO, eligibility requirements, evaluation and award criteria, selection process, and the general characteristics of a competitive application will be addressed at the webinar and by e-mail to askchips@chips.gov with “2024-NIST-CHIPS-MFGUSA-01 Questions” in the subject line. There is no cost to attend the webinar, but participants must register in advance. Participation in the webinar is not required and will not be considered in the review and selection process.

Proposers Day and Teaming Meetings: In addition to the informational webinar described above, CHIPS R&D plans to host a Proposers Day on May 16, 2024 to promote awareness of this NOFO and provide a forum for organizations to identify prospective partners. Information about the event can be found on the CHIPS for America events website.

Public Website, and Frequently Asked Questions (FAQs): CHIPS R&D has a public website with a “Frequently Asked Questions” page and other information pertaining to this NOFO.

Concept Papers: The submission of a concept paper is required. Concept papers will only be accepted through Grants.gov. The deadline for receipt of concept papers is 11:59 p.m. Eastern Time, June 20, 2024. Concept papers received after this deadline will not be reviewed or considered. Please note that an active SAM.gov registration is required to submit application materials through Grants.gov.

Full Applications: Full applications will be accepted only from those applicants invited after concept paper evaluation. Full applications must be received at Grants.gov no later than 11:59 p.m. Eastern Time, September 9, 2024. Applications received after this deadline will not be reviewed or considered.

Anticipated Amounts: NIST anticipates awarding up to approximately $285M in Federal funding for a single Institute award, with a performance period of up to five years.

Funding Instrument: Awards in this program will be made as other transaction agreements for the selected project, as provided in 15 U.S.C. § 4659(a)(1). See Section 2 of this document for additional information regarding the type of award agreement.

Eligibility: Eligible applicants for the Institute award are non-profit organizations; accredited institutions of higher education; State, local, and Tribal governments; and for-profit organizations that are domestic entities. A domestic entity is one incorporated within the United States (including U.S. territories) with its principal place of business in the United States (including U.S. territories). Eligible applicants may only submit one concept paper for the Institute award under this NOFO. See Section 3 regarding eligibility requirements. Eligible entities may participate in multiple concept papers and applications as a subrecipient. Applicants and recipients are required to have an active registration in SAM.gov and are encouraged to begin the process of registering as early as possible.

mailto:askchips@chips.gov https://www.nist.gov/chips/chips-america-webinars https://www.nist.gov/chips/chips-RD-funding-opportunities

Cost Share Requirements: Non-Federal cost share is required for an award issued pursuant to this NOFO. Specifically, this program requires cost share in an amount equal to at least the total amount of Federal funding over the lifetime of the award (i.e., 50% or more of the total funding for the Institute must come from non-Federal sources). Cost share is that portion of the project costs not borne by the Federal government. See Sections 1.2, 1.8, and 3.2 of this document for definitions, additional information, and expectations regarding cost share requirements and optional co-investment.

Agency Points of Contact (POC): Section 7 identifies Agency Points of Contact. Applicants must submit all questions in writing to the appropriate agency point of contact with “2024-NIST-CHIPS- MFGUSA-01” in the subject line. All inquiries regarding this NOFO must be submitted to the email addresses in that section.

Table of Contents

1 PROGRAM DESCRIPTION

1.1 CHIPS Manufacturing USA Institute Overview

1.1.1 CHIPS R&D Mission and Goals

1.1.2 The Manufacturing USA Network

1.1.3 CHIPS Manufacturing USA Institute Description

1.2 Definitions

1.3 Funding Opportunity Detailed Description

1.3.1 Institute Activities

1.3.2 Institute-level Targets

1.3.3 Operational Areas

1.3.4 Phases and Milestones

1.4 Milestones and Deliverables

1.4.1 Operational Area 1 (OA1): Institute Operations

1.4.2 Operational Area 2 (OA2): Shared Physical and Computational Capabilities

1.4.3 Operational Area 3 (OA3): Industry-led Solutions

1.4.4 Operational Area 4 (OA4): Education and Workforce Development

1.5 Manufacturing Readiness Levels

1.6 General Roles of The Institute Award Recipient and NIST

1.6.1 Substantial Involvement

1.6.2 Responsibilities of Recipient

1.6.3 Involvement of NIST and CHIPS R&D

1.6.4 Joint Activities Between Recipient and NIST and CHIPS R&D

1.6.5 Coordination with other Federal R&D Programs

1.7 Broader Impacts

1.7.1 Commitments to Future Investment

1.7.2 Creating Inclusive Opportunities

1.7.3 Environmental Responsibility

1.7.4 Community Impact and Support

1.8 Optional Co-Investments

1.9 Government-Furnished Property (GFP) and Government Furnished Information (GFI)

2 FEDERAL AWARD INFORMATION

2.1 Funding Instrument and payments

2.2 Funding Availability under this announcement

2.2.1 Eligible Uses of Funds

2.2.2 Construction

2.3 Multi-Year Funding Policy

2.4 Possibility of Award Renewal

2.5 Indirect (F&A) Costs

2.6 Public Access to CHIPS R&D Research

2.7 Fundamental Research

2.7.1 Fundamental Research Declaration

2.7.2 On-Campus Research

2.7.3 Pre-Publication Reviews

2.8 Research Security

2.8.1 Research Security Definitions

2.8.2 Authorities

2.8.3 Requirement to Establish a Research Security Program

2.8.4 Covered Individuals

2.8.5 Foreign Entities of Concern

2.8.6 Research Security Review and Risk Determination

2.8.7 Non-Discrimination

2.8.8 Potential for Mitigation

2.8.9 Requirement for Recipients to Update Research Security-Related Information

2.9 Intellectual Property (IP) and Domestic Production

2.9.1 Domestic Production

2.9.2 Domestic Control

2.9.3 Requirements at the Institute Level

2.9.4 Project Level Requirements: Commercial Viability and Domestic Production Plans

3 ELIGIBILITY INFORMATION

3.1 Eligible Applicants

3.1.1 Institute Teams

3.1.2 Existing Manufacturing USA Institutes

3.1.3 Federally Funded Research and Development Centers

3.1.4 Federal Entities

3.1.5 Individuals and Unincorporated Sole Proprietors

3.1.6 Foreign Entities and Foreign Research Activities

3.2 Cost Share Requirements

3.3 Allowable Costs

4 APPLICATION AND SUBMISSION INFORMATION

4.1 Overview

4.2 Address to Request Applications Package

4.3 Page Count Guidance

4.4 Submission Format

4.4.1 Amendments

4.4.2 Proprietary and Sensitive Business Information

4.5 Concept Paper Instructions

4.5.1 Required Forms and Documents

4.6 Full Application Instructions

4.6.1 Required Forms and Documents

4.6.2 Unique Entity Identifier and System for Award Management (SAM)

4.7 Submission Dates and Times

4.7.1 Concept Papers

4.7.2 Full Application

4.8 Intergovernmental Review

4.9 Funding Restrictions

5 APPLICATION REVIEW INFORMATION

5.1 Concept Paper Evaluation Criteria

5.1.1 Relevance to economic and national security

5.1.2 Project Management, Resources, and Budget

5.1.3 Overall Scientific and Technical Merit

5.1.4 Transition and Impact Strategy

5.1.5 Education and Workforce Development

5.2 Concept Paper Selection Factors

5.3 Full Application Evaluation Criteria

5.3.1 Relevance to economic and national security

5.3.2 Project Management, Resources, and Budget

5.3.3 Overall Scientific and Technical Merit

5.3.4 Transition and Impact Strategy

5.3.5 Education and Workforce Development

5.4 Selection Factors

5.5 Review and Selection Process

5.5.1 Initial Review of Applications

5.5.2 Review of Concept Papers

5.5.3 Review of Full Applications

5.6 Additional Information

5.6.1 Safety

5.6.2 Changes in Applicant and Reteaming

5.6.3 Notification to Unsuccessful Applicants

5.6.4 Retention of Unsuccessful Applications

6 Federal Award Administration Information

6.1 Federal Award Notices

6.2 Administrative and National Policy Requirements

6.2.1 Terms and Conditions

6.2.2 Funding Availability and Limitation of Liability

6.2.3 Collaborations with CHIPS R&D and Other Federal Agencies

6.2.4 Post-Award Involvement of Foreign Entities

6.2.5 Use of Federal Government-Owned Intellectual Property

6.2.6 Export Controls

6.3 Reporting

6.3.1 Reporting Requirements

6.3.2 Audit Requirements

6.3.3 Federal Funding and Accountability Transparency Act of 2006

7 AGENCY CONTACTS

8 OTHER INFORMATION

8.1 Personal and Business Information

8.2 Public Website

Full Announcement Text

1 PROGRAM DESCRIPTION

The statutory authority for the CHIPS1 Manufacturing USA Institute is 15 U.S.C. § 4656(f). This competition seeks to establish one (1) Manufacturing USA Institute (the Institute) focused on the development, validation, and use of digital twins for semiconductor manufacturing, advanced packaging, assembly, and test processes. This CHIPS Manufacturing USA Institute will be established and operated consistent with the requirements of 15 U.S.C. § 278s(e), as amended.

1.1 CHIPS MANUFACTURING USA INSTITUTE OVERVIEW

The CHIPS and Science Act of 2022 appropriated $50 billion to the U.S. Department of Commerce’s (the Department) CHIPS for America program to strengthen semiconductor manufacturing in the United States. This amount includes $39 billion for the Department to onshore semiconductor manufacturing through an incentives program and $11 billion to advance U.S. leadership in semiconductor research and development (R&D). These R&D advances will be realized through four programs: the CHIPS National Semiconductor Technology Center (NSTC), the CHIPS National Advanced Packaging Manufacturing Program (NAPMP), the CHIPS Metrology Program, and the CHIPS Manufacturing USA Program. These investments, across both the R&D and incentives programs, seek to strengthen U.S. competitiveness, support domestic production and innovation, create good jobs across the country—with working conditions consistent with the Good Jobs Principles published by the Department and the U.S.

Department of Labor—and advance U.S. economic and national security.

1.1.1 CHIPS R&D Mission and Goals

Within the CHIPS for America program, the mission of the National Institute of Standards and Technology (NIST) CHIPS Research and Development Office (CHIPS R&D) is to accelerate the development and commercial deployment of foundational semiconductor technologies by establishing, connecting, and providing access to domestic research efforts, tools, resources, workers, and facilities.

CHIPS R&D aims to achieve the following goals by 2030:

• U.S. Technology Leadership: The United States establishes the capacity to invent, develop, prototype, manufacture, and deploy the foundational semiconductor technologies of the future.

• Accelerated Ideas to Market: The best ideas achieve commercial scale as quickly and cost effectively as possible.

• Robust Semiconductor Workforce: Inventors, designers, researchers, developers, engineers, technicians, and staff meet evolving domestic government and commercial sector needs.

1 DOC CHIPS activities were authorized by Title XCIX—Creating Helpful Incentives to Produce Semiconductors for America of the William M. (Mac) Thornberry National Defense Authorization Act for Fiscal Year 2021 (Pub. L. 116-283, often referred to as the CHIPS Act), codified at 15 U.S.C. 4651 et seq., as amended.

https://www.dol.gov/general/good-jobs/principles

1.1.2 The Manufacturing USA Network

The CHIPS Manufacturing USA Institute will join an existing network of seventeen Institutes designed to increase U.S. manufacturing competitiveness and promote a robust R&D infrastructure. Institutes are public-private partnerships that convene members2 in industry; academia (e.g., research universities, community colleges, and career and technical education schools); non-profit groups; Federal laboratories;

and State, local, and Tribal governments to focus on priorities that

(1) address challenges in advanced manufacturing;

(2) assist manufacturers in retaining or expanding domestic industrial production;

(3) reduce the cost, time, or risk of commercializing new technologies; and

(4) develop and implement improvements in education and workforce development.

NIST further expects that Institutes will work to improve the competitiveness of U.S. manufacturing, help fill the gap between basic research and commercialization, accelerate non-Federal investment in advanced domestic manufacturing production capacity, and enable the commercial application of new technologies.

Within NIST’s Office of Advanced Manufacturing (OAM), the Advanced Manufacturing National Program Office is tasked with coordinating the activities of the Manufacturing USA network. The Institute will be required to engage with the network, as described in Section 1.6.2. More information about Manufacturing USA, including published reports documenting program design and performance, can be found online at https://manufacturingusa.com.

1.1.3 CHIPS Manufacturing USA Institute Description

Semiconductors are arguably the smallest, most complex products ever made in one of the world’s most sophisticated manufacturing environments. Although U.S. innovation created the sector, domestic manufacturing currently accounts for about 12% of global production, compared to 37% approximately thirty years ago.3 To improve its manufacturing competitiveness, the United States must address key challenges, such as the time and cost of chip development and manufacturing processes, as well as talent shortages.

1.1.3.1 Background on Digital Twins

Digital twins offer a critical tool for the United States to achieve technology leadership and accelerate ideas to market across the semiconductor sector. As recently defined by the National Academies of Sciences, Engineering, and Medicine:

2 The business model for institutes relies on a group of persons and/or organizations coming together for a common purpose. This model generally results in a membership structure and an associated agreement that formalizes the relationship between a stakeholder organization and the institute entity itself.

Stakeholder organizations that establish this type of relationship with an institute are generally referred to as members.

3 See https://www.whitehouse.gov/briefing-room/statements-releases/2022/01/21/fact-sheet-biden-harris-administration-bringing-semiconductor-manufacturing-back-to-america-2/.

https://manufacturingusa.com/ https://www.whitehouse.gov/briefing-room/statements-releases/2022/01/21/fact-sheet-biden-harris-administration-bringing-semiconductor-manufacturing-back-to-america-2/ https://www.whitehouse.gov/briefing-room/statements-releases/2022/01/21/fact-sheet-biden-harris-administration-bringing-semiconductor-manufacturing-back-to-america-2/

A digital twin is a set of virtual information constructs that mimics the structure, context, and behavior of a natural, engineered, or social system (or system-of-systems), is dynamically updated with data from its physical twin, has a predictive capability, and informs decisions that realize value.

The bidirectional interaction between the virtual and the physical is central to the digital twin.4

Digital twin technologies can significantly impact both current and future semiconductor manufacturing, advanced packaging, assembly, and test processes. Leading companies have therefore developed and deployed proprietary digital twins and resources to optimize key process steps and increase throughput.

However, despite substantial investments in proprietary semiconductor digital twin technologies, multiple challenges hinder the development of breakthrough innovations using digital twins, including:

• Fragmentation, where companies each develop separate digital twins, limiting process optimization to a single tool or suite of tools rather than across the full manufacturing flow.

• Lack of transparency and trust, where companies are unwilling to share critical assets (e.g., models, data, and best practices related to their digital twins) outside of their supply chain.

• High barriers to entry, where high equipment and facilities costs, along with the difficulty of testing and validating digital twins in a full process flow, limit small business participation.

1.1.3.2 CHIPS Manufacturing USA Institute Vision, Mission, and Objectives

By convening the manufacturing ecosystem to solve shared technology challenges, a new Manufacturing USA Institute aims to unlock the full potential of digital twins for the semiconductor industry and benefit manufacturers of all sizes. The CHIPS Manufacturing USA Program therefore seeks to establish an Institute with the following vision and mission:

Vision: The CHIPS Manufacturing USA Institute will enable seamless integration of digital twin models into the U.S. semiconductor manufacturing, advanced packaging, assembly, and test industry, enabling the rapid development and adoption of innovations and enhancing domestic competitiveness for decades.

Mission: The CHIPS Manufacturing USA Institute will foster a collaborative environment within the domestic semiconductor industry, enabled by shared facilities; support industry-led solutions through funded research projects; accelerate technology towards commercialization through significant co-investment; and enable digital-twin workforce training.

To facilitate the creation of the CHIPS Manufacturing USA Institute, this NOFO seeks proposals from eligible applicants for activities to establish and operate the Institute, consistent with the mission and vision, to achieve the following specific objectives:

(1) Convene stakeholders across the semiconductor manufacturing, advanced packaging, assembly, and test industry to address shared challenges relevant to digital twins, in a collaborative environment.

4 National Academies of Sciences, Engineering, and Medicine. 2023. Foundational Research Gaps and Future Directions for Digital Twins. Washington, DC: The National Academies Press. See https://doi.org/10.17226/26894 https://doi.org/10.17226/26894

(2) Improve the state of the art in manufacturing-relevant digital twins, for both unit-level digital twins and the combination of multiple digital twins.

(3) Significantly reduce U.S. chip development and manufacturing costs by improving capacity planning, production optimization, facility upgrades, and real-time process adjustments using digital twins.

(4) Improve development cycle times of semiconductor manufacturing, advanced packaging, assembly, and test and accelerate the development and adoption of relevant innovative technologies, including breakthrough tools, materials, and manufacturing processes.

(5) Advance digital twin-enabled curricula, best practices, and hands-on opportunities for training the next generation of the domestic semiconductor workforce.

(6) Create a digital twin marketplace for industry to access digital models and manufacturing process flows and to de-risk digital twin development and implementation.

1.2 DEFINITIONS

This section provides definitions for purposes of this NOFO.

(1) Advanced packaging – A subset of packaging technologies that uses novel techniques and materials to increase the performance, power, modularity, and/or durability of an integrated circuit. Advanced packaging technologies include flip-chip, 2D, 2.5D, and 3D integration, fan-out and fan-in, and embedded die/system-in-package (SiP).

(2) Applied Research – “Original investigation undertaken in order to acquire new knowledge.

Applied research is, however, directed primarily towards a specific practical aim or objective.”5

(3) API –A set of interfaces for the Digital Twin Backbone that allow human developers to access the data of a digital twin. The API may also allow different digital twins to communicate, exchanging data and functionalities seamlessly.

(4) Basic Research – “Experimental or theoretical work undertaken primarily to acquire new knowledge of the underlying foundations of phenomena and observable facts. Basic research may include activities with broad or general applications in mind, such as the study of how plant genomes change, but should exclude research directed towards a specific application or requirement, such as the optimization of the genome of a specific crop species.” 6

(5) Co-investment – Commitments made by Institute members to advance potential innovations from projects to higher Manufacturing Readiness Levels (MRLs). Examples of co-investment may include those commitments required to enable the scale-up, commercialization, and transition to domestic production of Institute-funded innovations. Co-investment is described further in Section 1.8. MRLs are described further in Section 1.5.

(6) Cost Share – The portion of the costs of a Federally assisted project or program not borne by the Federal Government. The required cost share must, at a minimum, be equal to the total amount of Federal funding provided through the lifetime of an award (i.e., 50% or more of the total funding for the Institute must come from non-Federal sources). Examples of cost share are to be reported in the Research and Related Budget. Cost share is described further in Section 3.2.

(7) Design Technology Co-Optimization – The concurrent development of design and manufacturing processes to optimize chip performance, power efficiency, area utilization, and manufacturability.

5 Office of Management and Budget Circular A-11 (2023).

6 Id.

(8) Digital Twin – A set of virtual information constructs that mimics the structure, context, and behavior of a natural, engineered, or social system (or system-of-systems), is dynamically updated with data from its physical twin, has a predictive capability, and informs decisions that realize value.7

(9) Digital Twin Backbone – Interconnected digital twins as well as the standards, software, connection pathways, and protocols for data and IP protection required to provide a 2-way or networked path of exchange of information between them. The Digital Twin Backbone provides a means to form an end-to-end aggregated Digital Twin model of a process or system.

(10) Full Flow – The entire sequence of steps required for semiconductor manufacturing, from initial wafer preparation to final packaging, assembly, and test, or a subset of such steps as defined by the proposed Institute scope.

(11) Governing Council – The advisory body, consisting of representation from Institute membership, the Federal government, and others, that provides strategic advice to the CHIPS Manufacturing USA Institute, technical oversight of the Institute, and performance oversight of the Institute director and staff.

(12) Institute award – The award, granted under this NOFO, for the establishment and operation of the CHIPS Manufacturing USA Institute.

(13) Institute team – Together with the applicant, any proposed subrecipients, contractors, and/or unfunded collaborators listed on the application, which may include potential Institute members.

(14) Institute-led projects – Research, development, demonstration, or education and workforce development activities carried out by Institute staff. Institute-led projects can also support the shared capabilities, as outlined in Section 1.4.2, independent of Member-led projects. Institute-led projects must support Institute goals.

(15) Institute-level targets – Specific, measurable, achievable, relevant, and time-bound (SMART) technical or non-technical metrics proposed by the applicant, consistent with the mission and relevant objectives in Section 1.1.3.2, for the Institute to achieve by the end of the period of performance. Institute-level technical targets should seek to aggressively advance the current state of the art in digital twins or in semiconductor manufacturing.

(16) Institute staff – Individuals who may be direct Institute employees, contractors, or contracted staff at member organizations. The composition is proposed by the applicant to maximize the impact of the program.

(17) Interoperability – The capability of two or more networks, systems, devices, applications, or components to work together, and to exchange and readily use information — securely, effectively, and with little or no inconvenience to the user.8

(18) Member-led projects – Research, development, demonstration, or education and workforce development activities carried out by Institute members, funded via competitive Project Calls.

(19) Milestones – Actions or events marking a significant change or stage in developments in a project.

(20) Phase-Specific Project Plan – Description of the scope of technical work to be performed for a particular stage of the period of performance, what is expected to be accomplished, including SMART project-specific targets, milestones, deliverables, and budgets for Institute-led and Member-led projects.

7 See https://nap.nationalacademies.org/catalog/26894/foundational-research-gaps-and-future-directions-for-digital-twins.

8 See NIST Special Publication 1108r4. “NIST Framework and Roadmap for Smart Grid Interoperability Standards, Release 4.0” February 2021. https://doi.org/10.6028/NIST.SP.1108r4 https://nap.nationalacademies.org/catalog/26894/foundational-research-gaps-and-future-directions-for-digital-twins https://nap.nationalacademies.org/catalog/26894/foundational-research-gaps-and-future-directions-for-digital-twins https://doi.org/10.6028/NIST.SP.1108r4

(21) Phase-specific targets –Technical and non-technical targets, derived from applicant-specified milestones, to inform go/revise/no-go points for the transition from one phase to the next.

(22) Project award – An award, granted by the Institute, for the conduct of a Member-led or Institute-led project.

(23) Project Call – The mechanism by which the Institute will solicit proposals for competitively awarded projects.

(24) Semiconductor – An integrated electronic device or system, most commonly manufactured using materials such as, but not limited to, silicon, silicon carbide, or III-V compounds, and processes such as, but not limited to, lithography, deposition, and etching. Such devices and systems include but are not limited to analog and digital electronics, power electronics, and photonics, for memory, processing, sensing, actuation, and communications applications.

(25) Semiconductor manufacturing – All activities encompassed by the semiconductor fabrication, advanced packaging, assembly, and test processes.

(26) Shared capabilities model – A federated model where the Institute and members contribute funds and resources for facilities, physical equipment, computation and data resources, and technical staff.

(27) Short Loop – A simplified or truncated version of the typical semiconductor manufacturing flow, typically involving fewer steps and less complexity. Short-loop processing is commonly used in research, prototyping, or when simpler devices don't require the full-scale semiconductor manufacturing process.

(28) SMART – Specific, measurable, achievable, relevant, and time-bound (SMART). Acronym to describe goals, targets, or objectives.

(29) System Technology Co-Optimization – The process of developing semiconductor technologies in tandem with system-level requirements to optimize performance, power efficiency, integration, reliability, cost, and manufacturing processes.

(30) Technology Demonstrations – Industry-led solutions may include technology demonstrations that validate the digital twin for manufacturing solutions. Project funding for the technology demonstration must be limited to the physical substantiation of the technology and focused on the digital twin for manufacturing outcomes.

(31) Test Vehicle – An article designed for physical validation of digital twins. It will contain structures, circuits or integrated circuits that can be measured and/or tested. The test vehicle will be defined for a process module or short loop and have a plan for characterization and data generation.

1.3 FUNDING OPPORTUNITY DETAILED DESCRIPTION

1.3.1 Institute Activities

Applicants to this NOFO must propose to establish a CHIPS Manufacturing USA Institute with integrated physical assets and computational capabilities (digital assets) to tackle important semiconductor-industry manufacturing challenges. The Institute will manage a portfolio of Institute-led projects and competitively funded Member-led projects, including Education and Workforce Development (EWD) activities.

Projects also may include basic and applied research and technology demonstrations.9

9 For more information on Manufacturing USA Institute activities, see 15 U.S.C. § 278s, as amended.

CHIPS R&D encourages collaborative proposals under this NOFO, as significant partnership will likely be required to meet the CHIPS Manufacturing USA Program objectives. Consistent with the statute, effective Institutes will likely include the active participation of expert representatives from for-profit and non-profit organizations (including industry-led consortia); covered entities; research universities;

community colleges; career and technical education (CTE) schools; Federal laboratories; and State, local, and Tribal governments. As defined in 42 U.S.C. 18971(b), covered entities include Historically Black College or Universities (HBCUs), Tribal Colleges or Universities, Minority Serving Institutions, a minority business enterprise (as defined in 15 C.F.R. § 1400.2), or a rural-serving institution of higher education (as defined in 20 U.S.C. § 1161q). Further, CHIPS R&D encourages outreach and engagement with government agencies, labor organizations, public workforce systems,10 community-based organizations, and small and medium-sized manufacturing enterprises,11 including women-owned, minority-owned, and veteran-owned manufacturing enterprises.

1.3.2 Institute-level Targets

Consistent with the mission and objectives under Section 1.1.3.2, applicants must propose specific Institute-level technical targets, representing significant improvements over the current state of the art for semiconductor-industry digital twins and real-world semiconductor manufacturing. For example, SMART Institute-level technical targets and milestones could, but are not required to, include—

(1) A substantial decrease in the time required to develop a specific new capability (e.g., a material, process, or tool) for semiconductor manufacturing, within two years of award;

(2) A specific increase in the accuracy of a short loop of digital twins, leveraging artificial intelligence, within two years of award;

(3) Establishing a production-representative digital twin of an end-to-end flow between semiconductor fabrication and advanced packaging, consisting of multiple interoperable digital twins validated with a pre-determined test vehicle, within five years of award; or

(4) Demonstrate the applicability of one digital twin to another end-to-end flow, leveraging standards, within five years of award.

Applications should also propose Institute-level non-technical targets, representing significant advances in the operation of the Institute, addressing issues such as technology transition and financial sustainability. For example, SMART Institute-level non-technical targets and milestones could, but are not required to, include—

(1) Achieving cost share and co-investment commitments of more than three times the level of Federal investment, within two years of award; or

(2) Enabling the hiring or reskilling of a specific number of semiconductor industry workers, via EWD projects focused on credentialing, within five years of award.

1.3.3 Operational Areas

Consistent with the mission and objectives specified in Section 1.1.3.2, responsive applications to this NOFO must address each Operational Area (OA) described in Section 1.4. Briefly, the OAs are:

10 The public workforce system is comprised of state and local workforce boards, American Job Centers, Registered Apprenticeship Programs, Eligible Training Providers, and other Federal, state, and local government-funded or overseen programs that provide training and other workforce services.

11 See https://www.nist.gov/mep.

https://www.careeronestop.org/LocalHelp/WorkforceDevelopment/find-workforce-development-boards.aspx https://www.careeronestop.org/LocalHelp/AmericanJobCenters/american-job-centers.aspx https://www.apprenticeship.gov/employers/registered-apprenticeship-program https://www.trainingproviderresults.gov/#!/about https://www.nist.gov/mep

(1) OA1: Institute Operations. Establishing an Institute management and governance strategy, to include plans for outreach to a broad group of potential members.

(2) OA2: Shared Physical and Computational Capabilities. Operating or providing member access to physical and virtual facilities, as appropriate.

(3) OA3: Industry-led Solutions. Developing and supporting an Institute-funded portfolio of projects, to either improve the capabilities of digital twins or to impact real-world operations.

(4) OA4: Education and Workforce Development. Developing and supporting projects to either train the workforce to use digital twins or to leverage digital twin technology to deliver EWD services to diverse audiences of trainees.

1.3.4 Phases and Milestones

Consistent with the mission and objectives specified in Section 1.1.3.2, responsive applications to this NOFO must propose 4 phases of work, with each phase ranging in length from 3 months to 18 months.

The total period of performance may not exceed five years.

Responsive applications must further define, within each phase, milestones marking measurable progress towards the Institute-level technical targets and other CHIPS Manufacturing USA objectives. If an application stands a reasonable chance of being funded, CHIPS R&D may negotiate with the applicant (1) to refine the proposed milestones and (2) to define phase-specific targets derived from the proposed milestones. These phase-specific targets will inform go/revise/no-go decision points for the transition from one phase to the next.

Upon approval and selection of an application, CHIPS R&D intends to award funding for Phase 1 activities across all operational areas; additional phases will be funded incrementally. CHIPS R&D retains sole discretion to determine whether a recipient has met the requirements for each Institute-level target, phase-specific target, and deliverable.

1.4 MILESTONES AND DELIVERABLES

1.4.1 Operational Area 1 (OA1): Institute Operations

The CHIPS Manufacturing USA Institute must lead a national effort to research, develop, test, and demonstrate industry-relevant, high-impact technologies relevant to the development or application of semiconductor industry digital twins. The Institute must therefore enable research collaboration among multiple parties while protecting intellectual property (IP) and advancing the vision, mission, and objectives specified in Section 1.1.3.2.

To demonstrate capabilities relevant to OA1, full applications must include an Institute Management and Governance Strategy, Institute Investment Strategy, and draft Institute Transition and Sustainability Plan.

1.4.1.1 Activities

CHIPS R&D expects activities under OA1 to include (1) attracting and serving a membership of diverse stakeholders from industry, academia, non-governmental organizations, national labs, and other groups;

(2) creating and implementing clear governance and operating structures and strategies for member participation, to include policies to protect member IP and Federally funded research products; (3) creating and maintaining the Institute Investment Strategy for technical roadmaps that identify the technical and non-technical challenges across OA2, OA3, and OA4; and (4) developing and executing a financial management strategy that enables the long-term sustainability of the Institute, including after the expiration of CHIPS R&D funding.

Membership. The Institute must build, provide value to, and facilitate engagement and collaboration among a diverse membership, consistent with meeting the Institute-level targets and ensuring representation from across the relevant portions of the semiconductor manufacturing industry.

Effective Institutes will likely include the members as referenced in Section 1.3.1.

Governance. CHIPS R&D expects that the key Institute leadership, including the executive director, will be 100% dedicated to the Institute.12 The Institute must establish governance structures such as a Board of Directors, Governing Council, and advisory committees, to provide strategic direction and ensure alignment with Institute-level targets. The Institute must establish policies, consistent with governing areas such as research security, IP rights, and enterprise risk management. These structures and policies should facilitate stakeholder engagement, uphold transparency, protect research security and IP, and enable prudent and effective management of Institute resources.

Financial Management. The Institute must develop annual budgets aligned with Institute-level targets. Financial stewardship includes budget monitoring, compliance with Federal award agreement terms, transparent reporting to stakeholders, and planning for long-term sustainability once Federal support ends.

1.4.1.2 Milestones and Deliverables by Phase

Applicants must propose SMART Institute-level targets related to, at a minimum, each of the activities listed in Section 1.4.1.1. Applications must further identify SMART milestones describing measurable steps toward achieving the proposed Institute-level targets.

OA 1 Phase 1 milestones must include, at a minimum—

(1) Hiring the full Institute leadership team;

(2) Hiring or contracting other key personnel critical to OA1 operations;

(3) Finalizing the Institute Management and Governance Strategy, including a membership agreement, Intellectual Property Rights Management Plan, and Research Security Plan;

(4) Convening the Institute membership to refine the Institute Investment Strategy;

12 Meaning that the Institute provides their full-time employment, and their appointment is not split between the Institute and other functions.

(5) Within six months of award, work towards coordination agreements with other relevant external CHIPS R&D-funded programs and entities (see Section 1.6.5), including but not necessarily limited to the CHIPS NSTC;

(6) Enrolling a diverse set of members, as required to accomplish the Institute-level targets; and

(7) Securing required cost share and any additional in-kind co-investment from Institute members or other sources.

OA 1 Phase 1, Phase 2, Phase 3, and Phase 4 deliverables must include, at a minimum—

(1) Updates to the Intellectual Property Rights Management Plan, as described in Section 4.6.1.6 and pursuant to 15 U.S.C. §4656(g) and Section 2.9;

(2) New or updated Phase-specific Project Plans, as described in Section 4.6.1.6;

(3) Reports of any significant incidents impacting research security or enterprise risk; and

(4) Additional updates to the Institute Management and Governance Strategy or Institute Investment

Strategy, in the event of significant changes.

Additional deliverables may include updates to the Institute Transition and Sustainability Plan and the Market Transformation Plan, as described in Section 4.6.1.6, and information required to evaluate the potential renewal of the Institute’s award, consistent with Section 2.4. The updated Institute Transition and Sustainability Plan, as practicable, should address plans to ensure Institute-owned IP compliance with Section 2.9.

1.4.2 Operational Area 2 (OA2): Shared Physical and Computational Capabilities

Digital twins offer a transformative tool to accelerate the pace of technological innovation. However, high barriers to entry, such as the costs of equipment and protections on proprietary IP, limit critical participation from academia and small businesses. Consistent with the mission, vision, and objectives under Section 1.1.3.2, the CHIPS Manufacturing USA Institute must enable innovation by providing a wide range of stakeholders with access, at low cost and with reasonable IP protections, to the equipment, facilities, licenses, staff, and digital infrastructure required for digital twin testing and validation. OA2 therefore seeks to establish a network of facilities, equipment, and tools that meet the broad requirements of Institute members. To accomplish this goal, the applicant and its partners may contribute funds and resources for physical facilities and equipment, computation and data resources, and technical staff towards a shared capabilities model that best meets members’ needs.

To demonstrate capabilities relevant to OA2, applications must include, within the Institute Investment Strategy, a Shared Capabilities Infrastructure Plan to include applicant-proposed milestones and deliverables, as appropriate.

1.4.2.1 Activities

Under OA2, activities must include (1) acquiring access to physical assets, at not less than two physical locations within the United States in order to establish a network, representing key processes within the semiconductor manufacturing, advanced packaging, assembly, and test industry; (2) establishing a computational capability to provide access to and improve an interconnected network of digital twins representing tools and other necessary physical assets; (3) providing access to the human expertise required for the Institute and its members to innovate using the physical assets and Digital Twin

Backbone; and (4) establishing a digital marketplace to provide members with access to digital twins and related IP. Each of these activities must align with achieving the Institute-level technical targets.

Physical Assets. To ensure the applicability of the Institute to current and future domestic semiconductor manufacturing, applicants must propose to provide Institute members with access to industry-relevant physical assets (e.g., commercially relevant semiconductor manufacturing tools).

This access must be sufficient to enable the development and testing of digital twin models, which will likely require member access to staff trained on the use of the relevant physical asset. CHIPS R&D expects a significant portion of the physical assets and staff, or access to such assets and staff, will be provided to the Institute as part of the required cost share and/or the optional co-investment.

Computational Capability. To ensure that Institute activities are not limited to advancing only small subsets of digital twins, applicants must propose to establish a computational capability to build, improve, and provide Institute members with access to an interconnected network of digital twins.

The resulting interconnected network (or “Digital Twin Backbone”) must include not only multiple digital twins but also the computational and information technology (IT) infrastructure connecting them. The interconnected network must further include any sensors or additional infrastructure allowing for communication between physical assets and their respective digital twins. Applicants should also demonstrate how Institute governance and policies—such as data sharing standards and IP protection requirements—enable interoperability between digital twins, leading to data and model standards, data protection, and accuracy standards. CHIPS R&D expects a significant portion of the computational capability as well as the digital twins, or access to such digital twins, will be provided to the Institute as part of the required cost share and/or optional co-investment.

Institute Expertise. To ensure that Institute activities are not limited to advancing the digital twin capabilities of any single member or group of members, applicants must propose to provide Institute members with access to independent technical staff responsible for supporting, maintaining, and improving the Digital Twin Backbone, including computational engineers. Independent technical staff may also include individuals with direct access to and expertise relevant to the physical assets.

Institute staff—who may be direct Institute employees, contractors, or contracted staff at member organizations—may support Member-led projects and conduct Institute-led projects, among other activities, at the discretion of the Institute.

Digital Marketplace. To facilitate Institute member access to digital twins and the licenses required to conduct R&D activities, applicants should propose to establish a Digital Marketplace as a resource to provide members access to Institute and member IP and other products (e.g., software licenses, other research-use licenses, Federally funded and donated IP). The marketplace may provide, based on agreed-upon terms and conditions and with appropriate IP protections, access to items available to all members as a benefit of membership. The marketplace may also provide, with appropriate IP protections, access to items available from members or other sources at a cost. CHIPS R&D invites alternative proposals as to the structure of the Digital Marketplace.

1.4.2.2 Milestones and Deliverables

Applicants must propose SMART Institute-level targets related to, at a minimum, each of the required activities listed in Section 1.4.2.1. Applicants should further identify SMART milestones describing measurable steps toward achieving the proposed Institute-level targets.

Deliverables for each phase must include, at a minimum, within the Institute Investment Strategy, providing an updated Shared Capabilities Infrastructure Plan, as described in Section 4.6.1.6.

OA2 Phase 1 milestones must include, at a minimum—

(1) Acquiring consistent access to physical assets based on member needs, at not less than two domestic locations;

(2) Establishing the computational capability and providing member access to a functional Digital Twin Backbone, with connectivity between multiple digital twins (for example data and model standards, data protection, and accuracy); and

(3) Hiring or contracting Institute expertise to support the physical assets, computational capability, Institute-led projects, and Member-led projects.

OA2 Phase 2, Phase 3, and Phase 4 milestones must include, at a minimum—

(1) Demonstrating use of the physical assets, computational capability, and functional Digital Twin Backbone to conduct projects in service to the Institute-level technical targets;

(2) Within two years of award, executing a significant demonstration of the Digital Twin Backbone, across multiple industry-relevant digital twins in a short loop (e.g., a short loop modeling front-end-of-line fabrication, advanced packaging, or assembly into printed circuit boards) and in service to the Institute-level technical targets;

(3) Increases in the quantity and quality of the physical assets;

(4) Improvements in the performance of the Digital Twin Backbone (e.g., digital twin operability and the accuracy of the digital process flow);

(5) A reduction in the time required to introduce new digital twin tools into the Digital Twin

Backbone; and

(6) Additional demonstrations of the Digital Twin Backbone, sufficient to indicate the full technical scope of the Institute.

1.4.3 Operational Area 3 (OA3): Industry-led Solutions

To accomplish the mission, vision, and objectives specified in Section 1.1.3.2, the CHIPS Manufacturing USA Institute must provide “industry-led solutions” via research, development, and demonstration projects that both develop improved digital twins and translate digital twin innovations into the real world.