NB688000-21-01460 SPECS.pdf

SPECIFICATIONS

ARTIQ KINTEX/ZYNQ DRTIO SUPPORT

NIST / Ion Storage Group (ISG) requires software and gateware to be developed to enable full DRTIO (distributed real-time input/output) functionality, including DRTIO mastering and DRTIO satellite operation for KC705 and ZC706 evaluation boards running NIST ARTIQ gateware. ISG performs a variety of quantum computing, quantum simulation, and optical clock experiments using trapped ions. These experiments are very complex and require advanced real-time classical control.

The ARTIQ experimental control system, developed specifically for the Ion Storage Group, is used to operate our experiments. For the next generation of quantum information and clock experiments, ISG requires the ability to integrate our existing ARTIQ control hardware, based on the Xilinx KC705 and ZC706 evaluation boards, with other ARTIQ control hardware in the Sinara ecosystem based on the Kasli FPGA card, along with related hardware modules controlled by Kasli. The existing ARTIQ standard for such integration, known as DRTIO, is not currently compatible with the KC705 or ZC706 boards or with Kintex or Zynq FPGAs. The ARTIQ Kintex/Zynq DRTIO support requires software and gateware to enable full DRTIO support on KC705 and ZC706 as following:

Item 1 – GTX transceiver setup for DRTIO and multi-channel support with phase alignment. This item enables porting of the DRTIO physical layer to the physical KC705 and ZC706 boards with Kintex-7 FPGA fabric. This does not include WRPLL support.

Item 2 – Update of KC705 DRTIO target definitions to support the latest ARTIQ and transceiver changes.

This must cover both the QC2 and CLOCK variants to support the use of the corresponding NIST FMC backplanes. Both QC2 and CLOCK variants must be usable as either a DRTIO master or as a DRTIO satellite.

Item 3 – DRTIO master support in ARTIQ-Zynq runtime for the ZC706. This includes target definitions for QC2 and CLOCK variants to support the use of the corresponding NIST FMC backplanes.

Item 4 – Port of the DRTIO satellite manager to Zynq for the ZC706. This includes target definitions for QC2 and CLOCK variants to support the use of the corresponding NIST FMC backplanes.

Terminology note – ARTIQ-related acronyms are defined in the online ARTIQ documentation accessible at https://m-labs.hk/artiq/manual-master/

The contracted software and gateware must enable the correct functioning of both KC705 and ZC706 boards as ARTIQ core devices, running the latest stable release of ARTIQ at the time of contract completion and invoicing, with the required DRTIO functionality. These boards must be able to act as DRTIO master when configured appropriately and must also be able to act instead as DRTIO satellite when configured appropriately. This functionality must be realized for both the NIST QC2 gateware and the NIST CLOCK gateware for all combinations of KC705/ZC706 and DRTIO master/DRTIO satellite.

The contracted software and gateware must be delivered electronically in several ways. The source code must be posted in appropriate public Github repositories such as M-LABS/ ARTIQ and related repositories. Compiled bitstreams for all contracted hardware combinations described above must be accessible for install via conda in the standard manner for ARTIQ bitstreams.

https://m-labs.hk/artiq/manual-master/

SHIPPING AND DELIVERY

Maximum of 4 months after receipt of order (ARO).

ELECTRONIC MEDIA

Software to be open source and accessible on Github and as part of ARTIQ Conda packages.

WARRANTY

Base Manufacturer Warranty is acceptable.

INSPECTION AND ACCEPTANCE

Operation and testing of updated ARTIQ software with contracted DRTIO functionality to be carried out by NIST personnel on NIST hardware to verify satisfactory performance.

The Government acceptance is expected up to 3 WEEKS. NIST personnel is subject to COVID-19 guidance and restrictions as applicable.