STATEMENT OF WORK (SOW) - ETTUS.pdf

STATEMENT OF WORK

High-performance, multi-channel software-defined radio (SDR)

Background:

Sponsor / Customer: NAVSEA, PMS 408 Expeditionary Missions

End User: Navy (CIED/CUAS), Air Force, FMS – Australia, New Zealand

Requirement: The Software Support Activity (SSA) provides a full software sustainment capability for the JCREW I1B1 System of Systems. The goal is to support / lead system integration and technical insertion efforts as directed by the I1B1 APM/PM. The SSA will implement the system software and firmware (SW/FW) supportability and sustainment requirements identified in the Capabilities

Production Document (CPD) and the Life Cycle Sustainment Plan (LCSP).

Project Completion: The JCREW I1B1 is a DoD Program of Record (POR) - ACAT II program with major milestones through its life cycle where SSA has a direct involvement.

NEXTGEN SDR/SC Technical Insertion/Enabling Functions FY24-27

Operational Program (OP) 8.1.X Release FY24-27

NSWC IHD:

RDT&E VSYSCOM Lab 209, E34, NSWC IHD, serves PMS408 - Joint Counter Radio-Controlled Improvised

Explosive Device Electronic Warfare (JCREW) as the Software Support Activity (SSA) for JCREW I1B1

Family of Scanner/Jammers. The nature of the software/firmware makes it imperative that the SSA must "mirror" the software development environment of the prime vendor, Northrup Grumman for sustainment (main deliverable software/firmware), transformational (NEXTGEN SDR, SC, CDU), and support of the JCREW Organic Depot at NSWC CN.

The JCREW family of systems in deployed to the US NAVY, US AIRFORCE, OGA, and FMS customers.

The JCREW SSA must handle SW from other USG stakeholders, JHU/APL, and Industry.

This document is prepared in accordance with the direction of the Joint Counter Radio Controlled

Improvised Explosive Device Electronic Warfare (JCREW) program Statement of Work (SOW).

Identification:

This Computer Software Product (CSP) describes how to build each of the JCREW software and Very

High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) components and the

Digital Versatile Discs (DVDs) that contain all the source code, test and peer review artifacts for the

CSCIs.

System Overview:

JCREW System of Systems (SoS), shown in shown below, implements a network-ready system architecture that is to be integrated into a variety of host platforms (dismounted, mounted and fixed site/semi-permanent). JCREW Devices share a common modular hardware and software design for a cost effective solution using electronic warfare (EW) methods and techniques that meets the war fighter’s need for an agile and adaptive active defense system to suppress ever changing Radio

Controlled Improvised Explosive Devices (CIEDs) AND (CUAS) threats.

High-performance, multi-channel software-defined radio (SDR)is needed in support of NEXTGEN

SDR/SC, CDU 2.0, FOA, DRAKE, QUATTRO/MIB technical instructions -- high priority Counter UAS projects. As threats evolve, the SSA must have the proper lab and field equipment to support Testing and Development of the JCREW SW.

Need:

JCREW SSA requires (2) High-performance, multi-channel software-defined radio (SDR)

Features

High channel density

Reliable and fault-tolerant deployment

Stand-alone (embedded) or host-based (network streaming) operation

Fully integrated and assembled (the USRP X410 does not support swappable daughtercards)

1 MHz to 7.2 GHz frequency range (tunable up to 8GHz)

Up to 400 MHz of instantaneous bandwidth per channel

4 RX, 4 TX in half-wide RU form factor

Xilinx Zynq-Ultrascale+ ZU28DR RFSoC

12 bit ADC, 14 bit DAC

IQ Sample Clock rates up to 500 MS/s

Onboard SD-FEC, DDC, DUC

Quad-core ARM Cortex-A53 up to 1.2 GHz CPU

Dual-core ARM Cortex-A5 MPCore up to 500 MHz

Two QSFP28 ports (10 Gigabit Ethernet, 100 Gigabit Ethernet, Aurora)

Two iPass+™ zHD® Interfaces (PCIe Gen3 x 8)

RJ45 (1 GbE) [1]

10 MHz Clock reference

PPS time reference

Trig In/Out Interface

Built-in GPSDO

Two FPGA Programmable GPIO Interfaces (HDMI)

1 Type C USB host port

1 Type C USB port (serial console, JTAG)

Watchdog timer

OpenEmbedded Linux

RF Network on Chip (RFNoC™) FPGA development framework

Xilinx Vivado® 2019.1 Design Suite