OPTIMA_Proposers_Day_Package.pdf

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Optimum Processing Technology Inside Memory Arrays (OPTIMA) Jason Woo, MTO

March 1, 2023

A scalable, high-performance, compute-in-memory array processor for leap-ahead energy efficiency

Briefing prepare for OPTIMA program Proposers Day

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OPTIMA program goal H1

1.E-01 1.E+00 1.E+01 1.E+02

8-bi t T

OP

S/ W

8-bit TOPS/mm2

4/5/7nm 12/14/16nm 22/28nm 55/65nm

En er gy E ff ic ie nc y (T

O

PS

/W

Area Efficiency (TOPS/mm2)

10.1 10 100

OPTIMA

Peripheral circuits power limit

M em or y de vi ce s fo ot pr in t l im it

Tensor product unit (TPU) Graphic processing unit (GPU)

The state-of-of 8-bit, >1TOPS compute-in-memory (CIM) Accelerator data source: N. R. Shanbhag, et al., OJ-SSCS 2022 TPU, GPU accelerator data source: N. Jouppi, et al., ISCA 2021

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Data transfer and throughput limits power efficiency

H0

S. Chikkagoudar,et al., BMC 2011

PE: Process element LC: Local cache memory

TOPS = tera operations per second

General Purpose CPU Tensor product unit (TPU) Graphic processing unit (GPU)

Memory

Control Unit

Arithmetic and Logic Unit

Register Data movement latency limits TOPS

Digital compute energy limits

TOPS/W

Data movement energy limits TOPS/W MemoryData Process/

Control/IO

Memory Buffer

Matrix Multiply Unit

Accumulators

Norman Jouppi, et al., ISCA 2021

LC

PE

LC

PE

LC

PE

LC

PE

LC

PE

LC

PE

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Compute-in-memory (CIM) accelerator architecture H0

Multiply Compute Element

(MCE)

Multiply Accumulate Macro

(MAM)

Compute-in-memory Accelerator

(CIMA)

• Performs a multiply operation within the memory cell

• Performs analog summation (“accumulate”)

• Highly parallel processing

• Process large matrix-vector-multiplication-intensive workloads

Accumulation Signal Processing

A x B

B

A

Ad dr es s ci rc ui t

Logic & I/O

MAM

MAM

MAM

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Recent DARPA/MTO funded compute-in-memory research 2013 2018 2023

2018 (UIUC)

• 65 nm technology

• Compute memory with on-die learning

• 16X energy reduction per classification vs. near-memory computation

2018 (Stanford/Berkeley/MIT)

• Monolithic 3D integration with carbon nanotube FETs

(CNFET) and Resistive RAM (RRAM)

• 98% accuracy demonstrated 2022 (UCLA)

• 14nm technology

• Stochastic computing-in-memory

2022 (MIT/SkyWater)

• 130nm SkyWater

• Monolithic 3D Technology

2017 (University of Michigan)

• 40nm technology

• Heterogeneously integrated memristor chip with CMOS-based processor

Semiconductor Technology Advanced Research Network (STARnet)

Unconventional Processing of Signals for Intelligent Data Exploitation (UPSIDE)

Joint University Microelectronics Program (JUMP)

Foundations Required for Novel Compute (FRANC)

Three Dimensional Monolithic System-on-a-Chip (3DSoC)

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Current compute in memory limits H0

SOA MAMs has limited performance of ~20 TOPS/W and ~5 TOPS/mm2

Avishek Biswas, et al., ISSCC 2018

Poor MCE density

• 8-transistor Static Random Access

Memory (SRAM) has large footprint

• Binary-only operation

• Requires 6x6 SRAM cells (288 transistors) for 6-bit accuracy computation

Poor power efficiency

• Requires many analog-to-digital converters (ADCs)

• High power

• Large footprint

• Power-consuming digital signal processing circuits

SRAM-based Multiply Accumulate Macro (MAM)

Accumulation

Signal Processing

MCE

Array

A=0.067mm2

MCE = Multiply Compute Element

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OPTIMA objectives H1

1.E-01 1.E+00 1.E+01 1.E+02

8-bi t T

OP

S/ W

8-bit TOPS/mm2

4/5/7nm 12/14/16nm 22/28nm 55/65nm

En er gy E ff ic ie nc y (T

O

PS

/W

Area Efficiency (TOPS/mm2)

10.1 10 100

Specific program goals:

CIM Accelerator (CIMA)

• ≥ 100 TOPS throughput

• ≥ 300 TOPS/W efficiency (15X)

Multiply Compute Element (MCE)

• One-transistor (1T) footprint

• ≤ 0.5 fJ/bit execution energy

• ≤ 1 ns execution speed

• ≥ 1012 read endurance cycles

Multiply Accumulate Macro (MAM)

• 256x256 MCEs

• 8-bit accuracy

• 300 TOPS/W (15X)

• ≥ 20 TOPS/mm2 (4X)

OPTIMA will develop a fast, compact, power-efficient, and scalable compute-in-memory accelerator

MCE

MAM

Accumulation Signal Processing

CIMA

Ad dr es s ci rc ui t

Logic & I/O

MAM

MAM

MAM

OPTIMA

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Technical Challenge 1:

Achieving a small, power-efficient MCE

MCE large footprint and intrinsic binary operation limits computation density and energy efficiency

SOA = State-of-the-Art SRAM = Static Random Access Memory MCE = Multiply Compute Element MAM = Multiply Accumulate Macro

A. Jaiswal, et al., IEEE TVLSI, 2019

SOA MCE

• 8-transistor SRAM cell

• Large circuit footprint (0.14 µm2)

• Binary only memory

• Large access energy (40 pJ/operation)

• Long execution time (> 18 ns)

Poor MAM computation area efficiency (< 5 TOPS/mm2)

H2

750 nm

1 Transistor

MCE

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Technical Challenge 2:

Achieving a small, scalable, and power-efficient MAM architecture

Large footprint and energy intensive signal processing circuitries limits MAM computation density and power efficiency

ADC = analog-to-digital converter DAC = digital-to-analog converter CIM = Compute In Memory MAM = Multiply Accumulate Macro

• Area and energy inefficient signal processing circuits

• Needed large number of power intensive ADCs and DACs for digital-signal-processing-based CIM architectures

• Limitation in compute and area efficiencies

• 80% of the MAM power dissipation

• Up to 50% of the MAM area

• Limiting MAM performance to ~ 20 TOPS/W

Accumulation Signal Processing

H2MAM

Accumulation Signal Processing

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Possible approaches (All approaches based on VLSI technology meeting the BAA metrics will be considered)

Ferroelectric Field Effect Transistor (FEFET)

VLSI compatible single transistor MCEs and power efficient high performance MAMs

S.S. Cheema et al., Nature 2022

H3

• 1T footprint MCE utilizing novel VLSI compatible transistor with built-in memory function

Switching polarization

• Eliminate/reduce number of data converters

• Low power small footprint signal processing circuits

SRAM Stochastic Number generator low energy Boolean OR Compute Cells

6-bit

No ADC

Low power Small area

Stochastic compute signal processing

Jiyue Yang et al., ASSCC 2022

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Phase 1 (18 mo.)

Low-energy MCE

Phase 2 (18 mo.)

Compact MCE and MAM

Phase 3 (18 mo.)

Scalable MAM arrays

• Non-volatile MCE feasibility demo

• MAM architecture exploration

• Compact MCE realization

• High-density MAM integration

• High-performance MCE optimization

• Scalable MAMs for high-performance CIM

IV&V

• MCE performance validation • MAM evaluation • Mission-relevant workloads testing

Program structure and schedule H5

Program Kickoff

Oct ’23

BAA

Mar ‘23

All proposer teams need to address both TC1 and TC2 :

• Demonstrate a single transistor footprint MCE with ≤ 0.5 fJ/bit execution energy, ≤ 1 ns execution speed

• Demonstrate a compact MAM with at least 256x256 MCEs, and with 20 TOPS/mm2 and 300 TOPS/W

• Demonstrate an MAM-based CIM accelerator with 100 TOPS and 300 TOPS/W

CY 2023 CY 2026CY 2024 CY 2025 CY 2027

FY 2026FY 2023 FY 2024 FY 2025 FY 2027 FY 2028

CY 2028

MCE = Multiply Compute Element MAM = Multiply Accumulate Macro CIM = Compute In Memory

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OPTIMA metrics

TC

Metrics(1) SOA Phase 1 (18mo)

Low-energy MCE Phase 2 (18mo)

Compact MCE and MAM Phase 3 (18mo)

Scalable MAM arrays

TC1

Switching Energy (fJ/bit) > 10 ≤ 1 ≤ 0.5 ≤ 0.5 Read Speed (ns) ≤ 1 ≤ 5 ≤ 1 ≤ 1 Read Endurance (Cycles) N/A (volatile) 1010 1011 1012

MCE Cell Size (F2)(2) > 16 ≤ 6 ≤ 3 ≤ 3

TC2

MAM array Size (number of MCEs) Limited to <10 rows ≥ 256x256 (simulated) ≥ 256x256 (measured) ≥ 256x256 (measured) MAM Density (TOPS/mm2) ~5 ≥ 20 (simulated) ≥ 20 (measured) ≥ 20 (measured) MAM Peak Compute Efficiency

(TOPS/W)(3)(4)

~ 20 ≥ 100 (simulated) ≥ 100 (measured) ≥ 300 (simulated)

≥ 300 (measured)

CIMA Compute Throughput (TOPS)(3)(5) CIM Architecture Study 100 (simulated) 100 (measured)

(1) Measuring TOPS/W in the MAM for 8-bit integer multiply–accumulate (MAC) operation with full 8-bit arithmetic accuracy.

(2) “F” is defined as the contacted gate pitch.

(3) Computing density, computing efficiency, and compute throughput all are benchmarked against proposer proposed data set and algorithm meeting requirement (1).

(4) Power calculation includes all necessary periphery, control, and/or ADC circuitry of the MAM or CIMA test chips.

(5) Large data set 8-bit input benchmark including the inferencing accuracy target defined by proposer.

MCE = Multiply Compute Element fJ/bit = femtojoules of energy per bit ns = nanoseconds of speed MAM = Multiply Accumulate Macro TOPS = tera operations per second (compute throughput) TOPS/W = tera operations per second per watt (compute efficiency)

H5

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www.darpa.mil

Optimum Processing Technology Inside Memory Arrays (OPTIMA)

HR001123S0026

Proposers Day March 1, 2023

Brian D. Nuckols Contracting Officer

DARPA Contracts Management Office

Distribution Statement A. Approved for Public Release; Distribution Unlimited.

Proposers Day Disclaimer

A copious amount of information is made available to potential proposers to clarify program goals/objectives and proposal preparation instructions.

However:

• Only the information/instructions in the BAA counts

• Proposals will only be evaluated in accordance with the instructions provided in the BAA

• Any response provided by the Government in the FAQ that’s different than what is provided in the BAA will be made formal by an amendment to the BAA

• Such responses will make note of an impending BAA amendment

Only a duly authorized Contracting Officer may obligate the Government

BAA Overview

Described in Federal Acquisition Regulation Part 35:

– For the acquisition of basic and applied research

– FAR 35.016 (a): Shall only be used when “meaningful proposals with varying technical/scientific approaches can be reasonably anticipated.”

– BAAs allow for a variety of technical solutions

– The BAA defines the problem set, the proposer defines the solution (and SOW)

DARPA Scientific Review Process

– Proposals are evaluated on individual merit and relevance as it relates to the stated research goals/objectives rather than against one another

– Selections will be made to proposers whose proposals are determined to be most advantageous to the Government, all factors considered, including potential contributions to research program and availability of funding

Government may select for negotiation all, some, one, or none of the proposals received Government may accept proposals in their entirety or select only portions thereof Government may elect to establish portions of proposal as options

BAA Overview, Cont’d

Multiple Awards Anticipated (~$78M total)

Multiple award instrument types:

– Procurement contract

– Other Transaction

Phase 1 (Base Period)

– Realize a low-energy single-transistor footprint MCE with ≤ 1 fJ/bit, ≤ 5 ns read speed, ≤ 6

F2 nominal footprint and ≥ read endurance

– 18 months

Phase 2 (Option Period)

– Further improve the MCEs to achieve ≤ 0.5 fJ/bit, ≤ 1 ns read speed, ≤ 3 F2 nominal footprint and ≥ read endurance, and experimentally demonstrate a compact MAM with at least 256x256 MCEs with 100 TOPS/W energy efficiency and 20 TOPS/mm2 area efficiency

– 18 months Phase 3 (Option Period)

– Further improve and optimize the MCEs and MAMs to realize experimentally a CIMA with 100 TOPS throughput and 300 TOPS/W energy efficiency

– 18 months

BAA Process/Timeline

1. BAA published: February 21, 2023

2. Proposers Day: March 1, 2023

3. Abstracts Due: March 21, 2023

4. Government Abstract Responses: ~ early April 2023

5. FAQ Submission Deadline: April 21, 2023

6. Proposals Due: May 17, 2023

7. Proposals are checked for BAA compliance

Non-conforming proposals are not reviewed (and cannot be selected)

8. Government conducts Scientific Review Process

Clarification requests may be sent to various proposers

8. Government sends out notification letters: ~ June/July 2023

9. Contracts negotiated & awarded (performance start): ~ October 2023

(can assume 1 Oct 2023 for Pricing)

See BAA for complete date/time information Monitor SAM.gov for any BAA amendment(s)

Eligibility Issues

All interested/qualified sources may respond subject to the parameters outlined in

BAA

Foreign participants/resources may participate to the extent allowed by applicable Security Regulations, Export Control Laws, Non-Disclosure Agreements, etc.

FFRDCs and Government entities:

- Are not prohibited by the BAA from proposing

- Are, however, subject to applicable direct competition limitations

- Are, however, required to demonstrate eligibility (sponsor letter)

The burden to prove eligibility for all such team members rests with the proposer

All elements of a proposal (tech and cost, prime and subs – even FFRDC team members) must be included in the prime’s submission

Real and/or Perceived Conflicts of Interest:

- Identify any conflict/s

- If any are identified, a mitigation plan must be included

Abstracts (1 of 2)

Abstracts are strongly encouraged:

1. They minimize unnecessary effort in proposal preparation and review

2. They reduce the potential expense of preparing an out of scope proposal

The abstract provides a synopsis of the proposed project (tech and budget)

Government will reply by letter with one of two possible responses:

1. Encourage full proposal, and may provide feedback

2. Discourage full proposal, and will provide feedback

DARPA will not communicate further (verbally or in writing)

Regardless of DARPA’s response to an abstract, proposers may submit a full proposal

DARPA will review all full proposals submitted without regard to abstract recommendation/feedback

Distribution Statement A. Approved for Public Release; Distribution Unlimited. 8

Abstracts must include the following components:

• Cover Sheet

• Innovative Claims

• Technical Approach

• Deliverables

• Cost and Schedule

Submit UNCLASS submissions to the DARPA BAA Website (https://baa.darpa.mil) per the instructions in Section IV.C.2, “Abstract Submission Information,” of the BAA.

Abstracts (2 of 2)

Max of 5 pages

The total page limit does not include the cover sheet (required) or a submission letter (optional) https://baa.darpa.mil/

Full Proposal Ground Rules

KEY POINTS:

Two Technical Challenges: TC1 and TC2 Both technical challenges must be addressed in the proposal

All three Phases must be proposed (Base and two priced Options)

An organization/company/individual can be on multiple proposals

Submit unclassified proposals ONLY to the DARPA BAA Website (https://baa.darpa.mil)

Click “Finalize Full Proposal” button (otherwise you have not submitted)

Do not submit classified proposals/information to the DARPA BAA Website

If unsure, please follow the instructions in the BAA for inquiring

Propose to the program (goals, objectives, metrics, schedule, deliverables) the BAA has defined, not to the program you desire https://baa.darpa.mil/

Volume 1: Technical/Management Proposal

– Be mindful of the page limitations (30 pages)

– Be sure to respond to all 11 of the required “Detailed Proposal Information” items

• Technical Approach – is the centerpiece of the technical proposal

• Statement of Work – Organize by Phase/Option, then by Tasks. Define all tasks (what you are doing, not how you are doing it) and deliverables (data, software, and material items, as applicable).

– Pay attention to key technical elements in the “Funding Opportunity Description” that must be addressed in all proposals

Volume 2: Cost Proposal

– No page limitations

– DARPA Standard Cost Proposal Spreadsheet (required for all instrument types)

– Fully detailed cost build-ups/estimates (Prime & Subcontractors)(All instrument types)

• Summary Cost Build-up: By phase and performer fiscal year

• Detailed Cost Build-up: By phase, technical task, and month

– Subcontractor proposals are required (to include SOW)

– No Rough Order of Magnitudes (ROMs)

– Certificate of Current Cost/Pricing Data will be required for any procurement contract award meeting the prescribed threshold (i.e., the adequate price competition exemption does not apply to BAAs)

Full Proposal Preparation

Volume 2: Cost Proposal

– DARPA Standard Cost Proposal Spreadsheet The Government requires that proposers use the provided MS ExcelTM DARPA Standard Cost Proposal Spreadsheet in the development of their cost proposals. A customized cost proposal spreadsheet may be an attachment to this solicitation. If not, the spreadsheet can be found on the DARPA website at http://www.darpa.mil/work-with-us/contract-management (under “Resources” on the right-hand side of the webpage). All tabs and tables in the cost proposal spreadsheet should be developed in an editable format with calculation formulas intact to allow traceability of the cost proposal. This cost proposal spreadsheet should be used by the prime organization and all subcontractors. In addition to using the cost proposal spreadsheet, the cost proposal still must include all other items required in this announcement that are not covered by the editable spreadsheet. Subcontractor cost proposal spreadsheets may be submitted directly to the Government by the proposed subcontractor via e-mail to the address in Part I of this solicitation. Using the provided cost proposal spreadsheet will assist the Government in a rapid analysis of your proposed costs and, if your proposal is selected for a potential award, speed up the negotiation and award execution process.

Use the single TA spreadsheet Do not make changes that are specifically prohibited by the instructions Questions are welcomed. Please direct them to costproposal@darpa.mil

Distribution Statement A. Approved for Public Release; Distribution Unlimited.

Full Proposal Preparation, cont’d http://www.darpa.mil/work-with-us/contract-management

Data Rights

Government desires as few restrictions as possible

– A minimum of Government Purpose Rights is the expectation

If asserting less than Unlimited Rights (e.g., Restrictions):

– Provide and justify basis of assertions using the prescribed format

– Explain how each item will be used to support the proposed research project

– Explain how the Government will be able to reach its program goals (including technology transition)

The proposer (prime) must submit a Data Rights Cert covering the entire team (prime and subcontractors), as applicable Provide a Data Rights Cert no matter the instrument type being proposed This information is assessed during evaluations (barriers to transition)

Non-Conforming Proposal Determinations

Failure to submit proposal on time – non-conforming!

– Proposal due date and BAA closing date are the same – so, late is late!

Failure to submit using the correct mechanism – non-conforming!

– Unclassified proposals ONLY to DARPA BAA website

– Classified proposals/information ONLY per “Security Information” section of the BAA

Failure to submit both proposal volumes – non-conforming!

– OT proposals must also include a full cost volume (Cost Realism is an evaluation criterion for all proposals)

– OT proposals must also include a detailed list of payment milestones (Milestone Plan)

Pages beyond the page limitation (tech prop) – additional pages will not be reviewed

ROM/s instead of full subcontract cost proposal/s – non-conforming!

– “I didn’t have time to get the subcontract proposal(s)” will not change the outcome

– “My subcontractor/s would not give me a proposal” will not change the outcome

Missing FFRDC or Government Entity cost proposal – non-conforming!

Communications

Prior to Receipt of Proposals (Solicitation Phase): Follow instructions in

BAA

Typically handled through the FAQ, but see BAA exceptions (e.g., security)

After Receipt of Proposals/Prior to Selections (Scientific Review Phase):

Limited to Contracting Officer or BAA Coordinator (with approval) to address clarifications requested by the review team Proposal cannot be changed in response to clarification requests

After Selection/Prior to Award (Negotiation Phase): Negotiations are conducted by the Contracting Officer PM and/or COR typically tasked with finalizing the SOW (with PI) PM and/or COR typically involved in any technical discussions (i.e., partial selection discussions) Pre-award costs will not be reimbursed unless a pre-award cost agreement is negotiated prior to award

Informal Feedback Sessions (Post Selection): May be requested/provided once the selection(s) are made

– If made on a timely basis (~2 wks after letter), all requests will be accepted

Referenced Links http://www.darpa.mil/work-with-us/contract-management#SolicitationContracting (General DARPA contract management information) (DARPA Standard Cost Proposal Spreadsheet) http://www.darpa.mil/work-with-us/additional-baa (general BAA info pertaining to all instrument types) http://www.darpa.mil/work-with-us/procurementcontracts (info pertaining to contracts) https://acquisitioninnovation.darpa.mil/ (info pertaining to OTs) http://www.darpa.mil/work-with-us/reps-certs (DARPA-specific reps and certs for all instrument types) (Note August 2020 version of 52.204-24)(Similar is required for OTs as well)

Distribution Statement A. Approved for Public Release; Distribution Unlimited.

http://www.darpa.mil/work-with-us/contract-management#SolicitationContracting http://www.darpa.mil/work-with-us/additional-baa http://www.darpa.mil/work-with-us/procurementcontracts https://acquisitioninnovation.darpa.mil/ http://www.darpa.mil/work-with-us/reps-certs

DARPA Microsystems Technology Office

Proposers Day Attendee Contact List

Last Name First Name Company Email Address Agrawal Vineet Infineon Technologies LLC vineet.agrawal@infineon.com Bobda Christophe University of Florida cbobda@ece.ufl.edu Bredehoft Robert Micron Technology rbredehoft@micron.com Cao Yu Arizona State University yu.cao@asu.edu Castro Hernan Micron Technology hacastr@micron.com Chakraborty Prabuddha University of Maine prabuddha@maine.edu Datta Suman Georgia Tech sdatta68@gatech.edu Dirisu Afusat Intrinsix Corp adirisu@intrinsix.com Filipiak Bill Micron Technology wfilipiak@micron.com Gupta Sumeet Purdue University guptask@purdue.edu Hairapetian Armond TeraSignal newport1@yahoo.com Hasler Jennifer Georgia Institute of Technology jennifer.hasler@ece.gatech.edu Jacob Ajey University of Southern California ajey@isi.edu Jacobs-Gedrim Robin Sandia National Laboratories rbjaco@sandia.gov Joshi Siddharth Notre Dame sjoshi2@nd.edu Kaiser Md Abdullah-Al University of Southern California mdabdull@usc.edu Kane Avinash Raytheon avinash.kane@rtx.com Keshavarzi Ali Leading Edge Research akesh@stanford.edu Khan Asif Georgia Tech akhan40@gatech.edu Kim Youngsoo Bradley University ykim@bradley.edu Kulkarni Jaydeep University of Texas at Austin Jaydeep@austin.utexas.edu Law Oscar Kneron oscar.law@kneron.us Lee Benjamin University of Pennsylvania leebcc@seas.upenn.edu Marinella Matthew Arizona State University m@asu.edu Massa Samuel Northrop Grumman Samuel.massa@ngc.com Mertoguno Sukarno Georgia Tech karno@gatech.edu Meyer Grant Lockheed Martin grant.d.meyer@lmco.com Mitchell Douglas Infineon Technologies LLC douglas.mitchell@infineon.com Mukhopadhyay Saibal Georgia Institute of Technology saibal@ece.gatech.edu Narayanan Vijay IBM vijayna@us.ibm.com Ni Kai Rochester Institute of Technology kai.ni@rit.edu PAMARTI SUDHAKAR University of California, Los Angeles spamarti@ee.ucla.edu

*Attendees listed gave permissions via the registration website to be included in this contact list.

DARPA Microsystems Technology Office

Proposers Day Attendee Contact List

Radack Daniel IDA dradack@ida.org Ravichandran Jayakanth University of Southern California j.ravichandran@usc.edu Reilly Caroline Raytheon caroline.reilly@rtx.com Salahuddin Sayeef UC Berkeley sayeef@berkeley.edu Saxena Vishal University of Delaware vsaxena@udel.edu Scott Tim DuPont tim.scott@dupont.com Sebastian Abu IBM ase@zurich.ibm.com Seok Mingoo Columbia University Ms4415@columbia.edu Trivedi Amit University of Illinois at Chicago amitrt@uic.edu Verma Naveen Princeton University nverma@princeton.edu Xia Qiangfei UMass Amherst qxia@umass.edu Yang J. Joshua University of Southern California jjoshuay@usc.edu Yu Shimeng Georgia Institute of Technology shimeng.yu@ece.gatech.edu Zanoni Raymond Collins Aerospace RAYMOND.ZANONI@COLLINS.COM Zhou Xiangrong Trusted Science and Technology sean@trustedst.com Zick Kenneth Northrop Grumman kenneth.zick@ngc.com

*Attendees listed gave permissions via the registration website to be included in this contact list.

Optimum Processing Technology Inside Memory Arrays (OPTIMA)

HR001123S0026

Frequently Asked Questions (FAQs)

Question 1: At what temperature are the performance metrics measured?

Answer 1: The performance metrics is measured at room temperature or 300 K.

Question 2: What is the 8-bit weight and input?

Answer 2: The BAA specifies that TOPS/W in the MAM will be measured for an 8-bit integer multiply–accumulate (MAC) operation with full 8-bit arithmetic accuracy (see the program metrics table on page 9 of the BAA). The full 8-bit arithmetic accuracy is a Blackbox-in Blackbox-out 8-bit accuracy.

Question 3: What are the metrics specifications on the write of the memory?

Answer 3: The proposer can specify write time and endurance to provide additional insight but is not required as part of the metrics.

Question 4: Is the read speed a precision value?

Answer 4: It is an overall value including the MAM read speed.

Question 5: Are there any guidelines on the large data set for use in testing and demonstrating program goals?

Answer 5: The proposer is expected to develop the necessary data sets, algorithms, software, and/or supporting hardware required to test and demonstrate the program metrics, as stated in the BAA page 8.

Question 6: Are there any reliability requirements?

Answer 6: The BAA does not specify.

Question 7: Is there a maximum MCE array?

Answer 7: MAM deliverables need be greater than 256 X 256 MCEs, as stated on page 8 and page 9 of the BAA.

Question 8: After meeting throughput, energy efficiency, and area efficiency, is it important for the read speed to be less than 1ns?

Answer 8: To ensure low latency, the read speed should be less than 1ns.

Question 9: Is there an emphasis for non-volatile memory?

Answer 9: While non-volatile is desirable, the BAA does not require the proposed MCE consists of non-volatile memory.

Question 10: Why is no weight given to online training/programming?

Answer 10: OPTIMA is primarily focused on technology development for inferencing operations with 100 TOPS throughput, 300 TOPS/W power efficiency, and 20 TOPS/mm2 area efficiency.

Question 11: What is the program Controlled Unclassified Information (CUI) requirements?

Answer 11: The proposer is expected to review and propose consistent with the program CUI Guide, which outlines the specific requirements for how CUI must be handled within the program. Refer to Attachment 3: OPTIMA Controlled Unclassified Information (CUI) Guide posted with the OPTIMA solicitation on https://sam.gov.

Question 12: Will there be government IV&V?

Answer 12: Government IV&V is expected as stated on page 9 of the BAA.

https://sam.gov/