HR001121S0042-Amendment-01.pdf

HR001121S0042

Broad Agency Announcement ELectronics for G-band ARrays (ELGAR)

Microsystems Technology Office

HR001121S0042

September 30, 2021

AMENDMENT 1

As amended October 26, 2021

The purpose of this amendment is to correct an error in Table 1, Note 5 and provide further clarification on the

ELGAR program metrics and goals.

Table of Contents

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description A. Background B. Program Description C. Program Structure D. Technical Area E. Schedule/Milestones F. Deliverables G. Government Furnished Equipment/Property/Information H. Intellectual Property

II. Award Information A. General Award Information B. Fundamental Research

III. Eligibility Information A. Eligible Applicants

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

2. Other Applicants B. Organizational Conflicts of Interest C. Cost Sharing/Matching

IV. Application and Submission Information A. Address to Request Application Package B. Content and Form of Application Submission

1. Abstract Format

2. Full Proposal Format

3. Proprietary Information

4. Security Information

a. Program Security Information

b. Controlled Unclassified Information (CUI)

i. CUI Proposal Markings

ii. CUI Submission Requirements

c. Unclassified Submissions

d. Classified Submissions

5. Disclosure of Information and Compliance with Safeguarding Covered Defense

Information Controls

6. Human Subjects Research (HSR)/Animal Use

7. Approved Cost Accounting System Documentation

8. Section 508 of the Rehabilitation Act (29 U.S.C. § 749d)/FAR 39.2

9. Small Business Subcontracting Plan

10. Intellectual Property

a. For Procurement Contracts

b. For All Non-Procurement Contracts

11. Patents

12. System for Award Management (SAM) and Universal Identifier Requirements

13. Funding Restrictions

C. Submission Information

1. Submission Dates and Times

a. Abstract Due Date

b. Full Proposal Date

c. Frequently Asked Questions (FAQ)

2. Abstract Submission Information

3. Proposal Submission Information

a. For Proposers Requesting Technology Investment Agreements

b. For Proposers Requesting Contracts or Other Transaction Agreements

c. Classified Submission Information

4. Other Submission Requirements

V. Application Review Information A. Evaluation Criteria

1. Overall Scientific and Technical Merit

2. Potential Contribution and Relevance to the DARPA Mission

3. Cost Realism

B. Review and Selection Process

1. Review Process

2. Handling of Source Selection Information

3. Federal Awardee Performance and Integrity Information (FAPIIS)

VI. Award Administration Information A. Selection Notices

1. Abstracts

2. Proposals

B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. Solicitation Provisions and Award Clauses, Terms and Conditions

3. Controlled Unclassified Information (CUI) and Controlled Technical Information

(CTI) on Non-DoD Information Systems

4. Representations and Certifications

C. Reporting D. Electronic Systems

1. Wide Area Work Flow (WAWF)

2. i-Edison

3. Vault

4. DARPA Embedded Entrepreneurship Initiative (EEI)

VII. Agency Contacts VIII. Other Information

A. Proposers Day A. Protesting

ATTACHMENT 1: Cost Volume Proposer Checklist ATTACHMENT 2: Proposal Summary Slide Template ATTACHMENT 3: ELGAR Controlled Unclassified Information (CUI) Guide

PART I: OVERVIEW INFORMATION

Federal Agency Name: Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title: ELectronics for G-band ARrays (ELGAR) Announcement Type: Initial Announcement Funding Opportunity Number: HR001121S0042 Catalog of Federal Domestic Assistance Numbers (CFDA): Not applicable Dates: (All times listed herein are Eastern Time) o Posting Date: September 30, 2021 o Proposers Day: October 12, 2021 o Abstract Due Date: October 29, 2021 o FAQ Submission Deadline: November 29, 2021 o Proposal Due Date: December 13, 2021 o Estimated period of performance start: May 2022

Concise description of the funding opportunity: The ELGAR program will develop the integration technologies needed to create compact, high-performance RF electronics, including monolithic microwave/millimeter wave integrated circuits (MMICs) and transmit and receive array front-end test articles, to enable communication and sensing systems at G-band frequencies.

Anticipated Funding Available for Award: Approximately $55M of total funding is anticipated for awards made against this BAA.

Anticipated individual awards: Multiple awards are anticipated.

Anticipated funding type: 6.2 Types of instruments that may be awarded: Procurement contract or other transaction.

Agency contact:

o Dr. Thomas Kazior, Program Manager BAA Coordinator: HR001121S0042@darpa.mil

DARPA/MTO

ATTN: HR001121S0042

675 North Randolph Street Arlington, VA 22203-2114 mailto:name@darpa.mil

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using the procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016 and 2 C.F.R. § 200.203. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing. Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the SAM website, under the Contract Opportunities link, at https://sam.gov/. The following information is for those wishing to respond to the BAA.

The Microsystems Technology Office at DARPA seeks innovative proposals to develop fabrication and integration technologies needed to create compact, high-performance III-V RF electronics, including MMICs and transmit and receive array front-end test articles, to enable communication and sensing systems at G-band frequencies. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

A. Background

Due to the growing, insatiable thirst for information, both commercial and defense communications are driving towards increasingly higher data rates and wider bandwidths of operation. This in turn is driving systems toward higher operating frequencies, which more easily supports larger channel bandwidths. For example, today’s cellular networks (i.e., cellular networks based on 5G, the fifth-generation technology standard) operate at 6 GHz and below with development underway for 5G at millimeter wave frequencies (from 24.25 GHz to 52.60 GHz). 6G is anticipated to push to even higher millimeter wave frequencies in pursuit of even larger channel bandwidths and higher channel capacities.

The upper millimeter-wave band, known as G-band (110 GHz to 300 GHz), represents an attractive, underutilized portion of the EM spectrum for high data rate communications applications. From the achievable communication channel capacity perspective, particularly appealing is the portion of G-band above 200 GHz, where a local minimum in atmospheric absorption (i.e., an atmospheric transmission window) is located. However, adequate RF electronics does not exist today to support operation in this frequency band, particularly for size, weight and power (SWaP) constrained applications. In particular, the efficiency of G-band electronics is poor (i.e., in single digits) and must be addressed to make G-band systems viable.

As has been the case for communications at lower frequencies, phased arrays and massive multiple-input multiple-output (MIMO) operation are the preferred implementation solution for millimeter-wave systems. In an array, the antenna elements and associated transmit and receive electronics are typically spaced on a /2 lattice grid to enable wide angle scanning while minimizing main beam sidelobes. At G-band, the /2 lattice size is between 0.5 mm and 1.4 mm, which places a significant constraint on the allowable physical area into which the RF electronics must fit. At the same time, data rate, range, and sensitivity are directly proportional to the amount of power that can be radiated from the array face. High data rate communication links, therefore require high output power density.

G-band arrays can be implemented using either silicon-based (e.g., CMOS, SiGe) RF integrated circuits (ICs) or III-V compound semiconductor (e.g., GaAs, GaN, InP) MMICs. Each approach has advantages but also limitations.

The dense, planar, multi-layer back end of line (BEOL) interconnects and integration technologies developed for commercial electronics have made possible silicon-based G-band RF ICs that physically fit into the λ/2 lattice. In addition, silicon technology includes compact, low-loss through-substrate vias (TSVs), micro-bump interconnects, and mature integration processes to vertically integrate silicon RF ICs with other array components using low-loss RF interconnects. The silicon RF IC and integration technology have been used to successfully demonstrate phased arrays that operate at G-band.1

On the other hand, silicon-based solutions have limited RF output power and efficiency due to the fundamental gain and breakdown voltage limitations of the silicon-based transistors. For example, from first principles calculations, the maximum achievable efficiency for a 220 GHz G-band Si transistor is ~24%. Since power amplifiers (PAs) are created by combining multiple transistors to increase output power, the transistor efficiency sets a fundamental upper limit to the PA efficiency (~18% at 220 GHz). This theoretical limit is not achievable in practice due to losses associated with PA impedance matching and power combining networks. Consequently, the power-added efficiencies (PAE) of silicon-based G-band PAs have been limited to less than 10% for frequencies greater than 150 GHz (Figure 1).

Through significant investment in programs such as Sub-millimeter Wave Imaging Focal-plane Technology (SWIFT), Terahertz (THz) Electronics, and Nitride Electronic NeXt-Generation Technology (NEXT), DARPA has successfully developed III-V transistor technologies (e.g., InP, GaN) capable of overcoming the gain and breakdown voltage limitations of the silicon-based transistors at G-band. For example, due to the high breakdown field and carrier velocity inherent in III-V materials, III-V transistors that operate at G-band (220 GHz) can theoretically achieve > 39% PAE, setting a fundamental upper limit to the PA efficiency of > 30 % (see Figure 1). Also, III-V multi-finger transistor cells can generate an output power in excess of 40 mW at G-band, so relatively few transistor cells need be combined to achieve considerable PA output power levels. For example, III-V based G-band PAs exceeding 200 mW of output power at 200 GHz have been demonstrated.2

However, while the III-V based transistors have been scaled to support G-band operation, the BEOL interconnects and integration techniques in III-V-based technologies have not been scaled. As a result, the existing III-V fabrication processes, which typically offers only two to

1 M. Elkhouly et al., "D-band Phased-Array TX and RX Front Ends Utilizing Radio-on-Glass Technology," 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2020, pp. 91-94.

2 Z. Griffith, M. Urteaga, P. Rowell, “180-265 GHz, 17-24 dBm Output Power Broadband, High-Gain Power Amplifiers in InP HBT,” 2017 IEEE MTT-S International Microwave Symposium, pp. 973-976, June 2017.

four non-planar on-chip interconnect metal layers, impose a fundamental limitation on the achievable performance of III-V circuits. In particular, the III-V on-chip interconnects are large and inefficient, leading to passive circuits such as impedance matching and power combining networks that are physically large and lossy. In turn, this has resulted in PA MMICs that do not physically fit within the λ/2 G-band array lattice and are severely limited to less than 10% achievable PAE for frequencies greater than 150 GHz. (see Figure 1). For example, in a published ~100 mW III-V G-band PA MMIC, the total area of the interconnects and passive circuits alone far exceeds the available λ/2 G-band lattice area at 220 GHz.2 In other published G-band PAs operating at 220 GHz the measured PAE is limited to considerably less than 10%, even though the output powers achieved by some of those PAs are substantially greater than 100 mW (see Figure 1). In addition to on-chip interconnect limitations, III-V TSVs and vertical off-chip interconnects also are large and unacceptably lossy. Insertion loss of 3 dB or more for a PA-to-antenna connection is typical, meaning that more than half of the PA output power or more will be lost before being transmitted. This loss is primarily due to the impedance mismatch between the on-chip components (i.e., transmission lines), TSVs, and the off-chip interconnects.

This loss severely limits the performance of complex circuits and subsystems such as phased arrays.

Figure 1. Measured PAE (data points) and theoretical (solid lines) PAE limits for G-band PAs based on Si CMOS, SiGe HBTs. GaAs pHEMTs, GaN HEMTs and InP HBTs.

(Buckwalter, private communication, 2021)

As a result, novel integration approaches are needed that will make it possible to combine the superior BEOL and interconnect features of silicon-based technologies with the superior RF performance of the III-V compound semiconductor transistors in order to realize compact, efficient, G-band MMICs and array front-ends. As a part of this initiative, DARPA is interested in novel heterogeneous integration approaches that result in transmit and receive circuit compactness needed to fit all array element electronics within the λ/2 G-band lattice spacing and enable a revolutionary increase in power density and power efficiency of MMICs and phased arrays at G-band.

B. Program Description

The ELGAR program seeks to develop integration technologies needed to create compact, high-performance III-V RF electronics to enable communication and sensing systems at G-band frequencies. These integration technologies include dense, silicon-like, on-chip BEOL and low-loss chip-to-chip interconnects. Once developed, the integration technologies will be leveraged to implement demonstration and validation circuits and test articles including compact, high-efficiency G-band Power Amplifier (PA) MMICs and transmit and receive array front-end test articles that operate at 220 GHz. DARPA anticipates that the most challenging performance aspects of these MMICs and array test articles will be achieving 30% PA PAE, and > 34 W/cm2 transmit array power density and 24% transmit array efficiency at the 220 GHz operating frequency (see Figure 2). The MMICs, array front-end test articles, and interconnects will be constrained to a λ/2 lattice spacing. The array test articles must be able to transmit and receive, at a minimum, circularly polarized signals.

As shown in Figure 2, currently achievable G-band power amplifier performance falls short of the ELGAR goals. While MMIC power or power density can be increased by combining more transistor cells, the power density increase will come at the expense of even lower efficiency.

Figure 2. ELGAR array front-end test article 220 GHz power density and efficiency goals compared to published G-band III-V MMICs and Si RFICs from 180 GHz to 240 GHz. Higher array output power density requires higher MMIC and array efficiency due to thermal management constraints.

To achieve these program objectives, ELGAR must overcome two (2) technical challenges:

1) Achieving efficient, compact G-band MMICs with high output power density ELGAR seeks to develop on-chip integration technologies that will simultaneously enable MMIC compaction (to increase power density), reduction in loss (to increase PAE), and minimization of mechanical stress (from compact multi-layer interconnects) while maintaining the superior RF performance of III-V transistors. Approaches may include but are not limited to:

III-V-compatible, Si-like Cu damascene or similar planar multi-layer metal interconnects Advanced ultra-low-k interlayer dielectrics such as porous oxides, air cavities or similar materials/structures to minimize capacitance Novel, low-loss, compact impedance matching and combining networks enabled by the availability of more interconnect layers Robust, on-chip capacitors (e.g., MIM caps with high-k dielectrics) with reduced footprint for use in high density on-chip bypass capacitors Novel approaches for compacting or reducing the footprint of and loss in multi-finger III-V transistor cells (Note: Development of new III-V device epitaxial layer structures or intrinsic transistor structures is out-of-scope.)

Novel approaches for routing of bias, RF and ground lines while maintaining signal integrity and isolation in compact MMICs

2) Achieving low-loss off-chip interconnects between adjacent G-band array components.

ELGAR seeks to develop off-chip integration technologies to create compact, efficient, array front-end test articles. This may include but is not limited to:

Approaches to heterogeneously integrate III-V MMICs with non-III-V materials such as antennas and Si ICs Approaches to minimize the size and loss of lateral and vertical DC and RF component-to-component interconnects while maintaining signal integrity High-aspect-ratio III-V TSVs Optimization of RF interconnect and TSV impedance (e.g., TSV diameter/pitch) and impedance match to transmission lines to minimize loss Approaches that support chip-to-chip integration with micro-bumps Approaches that support vertical 3D chip stacking

While innovation in thermal management solutions is not within the scope of the ELGAR program, the array integration approach must also take into consideration thermal dissipation of the PA. Since the output power density of the ELGAR PA and transmit array front-end test articles is higher than state of the art (SoA) due to the compact PA size, proposers are expected to develop ELGAR integration solutions that will maintain safe PA and array operating temperatures (with conventional air-cooling solutions) for reliable operation.

C. Program Structure

ELGAR is a 48-month, three-phase program focused on developing integration technologies to compact and reduce loss of on-chip and off-chip RF interconnects. Phase 1 (Base) will be 18 months, whereas Phases 2 (Option 1) and 3 (Option 2) will be 15 months each. Information on anticipated progress per program phase for each technical challenge is provided in section D. It is expected that fewer performers will be funded to participate in Phase 2 and Phase 3 of the program. Options may be exercised, at the Government’s sole discretion, based on technical progress measured against the metrics and milestones defined in the BAA and funding availability.

D. Technical Area

The ELGAR program has one technical area which will focus addressing the two major technical challenges. Performers must address both technical challenges and meet all metrics in one proposal.

1. Technical Challenge 1 – Achieving efficient, compact G-band MMICs with high output power density

To overcome Technical Challenge 1, proposers are expected to develop compact, low-loss on-chip interconnects that will enable G-band III-V PA MMICs that fit in the G-band lattice, are highly efficient, and have high output power density. Performance metrics are specified in Table

1. To address this technical challenge, the performers will be expected to demonstrate progress as follows:

In Phase 1 (Base), performers are expected to develop compact transistor cells, Si-like multi-layer interconnects and passive components and approaches. Performers will design and fabricate a compact PA and low noise amplifier (LNA). Successful completion of Phase 1 will be demonstration of a multi-stage PA that 1) fits in the /2 lattice, 2) meets the Phase 1 metrics, 3) provides a path to achieving the Phase 2 and 3 MMIC performance and size goals, and 4) is compatible with the low-loss integration with other array components. It is expected that performers will develop and validate models for the transistor cells. RF interconnects and passive components.

In Phase 2 (Option 1), performers are expected to optimize the transistor cells, Si-like multi-layer interconnects and passive components for compactness, robustness (operation under high field and high currents), and to minimize loss. Performers will design and fabricate a compact LNA and a compact, high efficiency PA. Successful completion of Phase 2 will be demonstration of a high efficiency PA that 1) fits in the /2 lattice, 2) meets the Phase 2 metrics,

3) provides a path to achieving the Phase 3 MMIC performance and size goals, and 4) is compatible with low-loss integration with other array components. It is expected that performers will refine their models.

In Phase 3 (Option 2), performers are expected to further optimize the transistor cells, Si-like multi-layer interconnects and passive components for compactness, robustness, to minimize loss and to support high power density operation. Performers will design and fabricate a compact LNA and a compact high-power, high efficiency PA. Successful completion of Phase 3 will be demonstration of a high-efficiency, high-power PA that 1) fits in the /2 lattice, 2) meets the Phase 3 metrics, and 3) can be integrated into the G-band array front end. It is expected that performers will finalize their models.

2. Technical Challenge 2 – Achieving low-loss off-chip interconnects between adjacent G-band array components

To overcome Technical Challenge 2, proposers are expected to develop low-loss off-chip interconnects to integrate the PA MMICs developed under Technical Challenge 1 into a 16 element transmit array front-end test article to achieve high overall transmit array power efficiency. In addition, Technical Challenge 2 will use the low-loss off-chip interconnects to develop a 16 element receive array front-end test article with low noise figure. Performance metrics are specified in Table 1. To address this technical challenge, the performers will be expected to demonstrate progress as follows:

In Phase 1 (Base), performers are expected to design and fabricate low-loss off-chip interconnect test structures. Successful completion of Phase 1 will be demonstration of a compact low-loss off-chip interconnect test structures that 1) meets the Phase 1 metrics, 2) provides a path to achieving the Phase 2 and 3 array front-end test article performance and size goals, and 3) is compatible with the compact, G-band III-V MMICs. It is expected that performers will develop validated models for TSVs and RF interconnects.

In Phase 2 (Option 1), performers are expected to optimize the TSVs and off-chip interconnects for compactness, robustness (operation under high field and high currents), and to minimize loss.

Performers will design and integrate transmit and receive array front-end test articles. Successful completion of Phase 2 will be demonstration of compact low-loss off-chip interconnects on the Phase 2 MMICs and the low loss integration of the compact MMICs with the antenna layer and surrogate beamformer layer to create transmit and receive array font-end test articles that 1) meet the Phase 2 metrics and 2) provides a path to achieving the Phase 3 array performance and size goals. It is expected that performers will refine their off-chip interconnect models.

In Phase 3 (Option 2), performers are expected to further optimize the TSVs and off-chip interconnects for compactness, robustness, to minimize loss and to support high power density operation. Performers will design and integrate transmit and receive array front-end test articles.

Successful completion of Phase 3 will be demonstration of the transmit and receive array front-end test articles that meets the Phase 3 metrics. It is expected that performers will finalize their off-chip interconnect models.

Table 1. ELGAR Metrics

(1) All metrics measured at 220 GHz CW with a 10% bandwidth. Transmit and receive array front-end test articles must be 2D, contain a minimum of 16 elements, be on a /2 pitch at 220 GHz, and be able to transmit and receive circularly polarized signals. In Phase 2 the array test articles will have a threshold of circular polarization with an objective of dual linear polarization to transmit and receive circularly polarized signals. In Phase 3 the array test articles will have a threshold of dual linear polarization to transmit and receive circularly polarized signals. DARPA does not anticipate that the ELGAR program will result in significant innovation in the area of antennas. PAs, LNAs, and all off-chip interconnects and antenna elements must fit within the /2 lattice.

(2) Si-like multi-layer BEOL used to fabricate compact PAs must not degrade gain or efficiency of III-V transistors when compared with III-V transistors fabricated with traditional III-V BEOL.

(3) CW saturated output power for multi-stage amplifier; minimum of 15 dB gain.

(4) PA output power and PAE measured simultaneously; array power density and efficiency measured simultaneously.

(5) Off-chip interconnects must include a minimum of 2 layers (e.g. MMIC and antenna layers), a III-V layer, and III-V TSV. Insertion loss is measured from bottom of lower chip to top of upper chip.

(6) Array test articles to consist of antenna layer and III-V PA or LNA MMICs integrated with a surrogate beamforming IC. Array architecture to be of analog active type with PA or LNA at each radiator. Transmit array output power and efficiency metrics include antenna loss. Receive array noise figure metric includes antenna loss. The surrogate beamforming IC is used for evaluation of the array test article power density, efficiency, and noise figure metrics. The surrogate beamformer IC power dissipation is not part of transmit array efficiency calculation. The receive array test article noise figure goal does not include noise contribution from the surrogate beamformer IC. DARPA does not anticipate that the array test articles will be capable of beam steering (i.e., the boresight beam is expected to be static). Array test article components to be integrated with low-loss interconnects between adjacent array functions, such as from output of PA to antenna element or from antenna element to input of LNA and from MMICs to surrogate beamforming IC.

(7) LNA: minimum of 15 dB gain.

E. Schedule/Milestones

The ELGAR program structure is shown in Figure 3. ELGAR is a 48-month program with an anticipated start in May 2022. Program kickoff and quarterly review sessions or technical interchange meetings are mandatory and represent an opportunity to interact with the Government on planned work, specifics of the technical approach, and any technical or programmatic items of concern.

The performers will construct a research program with milestones to meet or exceed the metrics outlined in the metrics table. This should include milestones for:

Program kickoff meeting to be held at program start Preliminary and Critical Design Reviews (PDRs and CDRs) for test structures, MMICs and array front-end test articles Delivery of appropriate test structures, MMIC and array test articles in accordance with the schedule below for independent verification and validation by the government

All hardware deliverables must include test data showing that the milestone/metric has been achieved. It is expected that proposers will define test structures including compact multi-finger transistor cells, on-chip and off-chip interconnect test structures, passive components, with associated interim performance goals such as interconnect loss, and present these test structure designs and test results at periodic review sessions.

Demonstration of the 16-element array front-end test articles will include low-loss integration of the transmit (PA) and receive (LNA) MMICs with the antenna and a surrogate beamforming chip. The purpose of the surrogate beamforming chip is to demonstrate the integration technology and to allow RF test of the transmit and receive array front-end test articles metrics.

While beam steering capability in the array test articles is not required (i.e., the boresight beam is expected to be static), the integration approach must be compatible with beam steering. While the MMIC to antenna interconnect must be a low-loss 220 GHz interconnect, the surrogate beamformer to MMIC interconnects can be proposer-defined and must minimize loss as well as provide DC bias to the MMICs.

Figure 3. ELGAR program structure.

F. Deliverables

All performers shall deliver a detailed spend plan at program kickoff and execution of subsequent option awards, quarterly technical reports, monthly technical status updates, and monthly financial reports including updated expenditures. Performers shall prepare and submit briefing materials and participate in quarterly progress reviews, either via teleconference or at the performer’s site at the discretion of DARPA. All performers shall participate in and support program-wide reviews held at least annually and scheduled at the Program Manager’s discretion.

Performers are expected to deliver critical design review (CDR) packages including details of design, modeling, and simulation of all test structures, MMICs (PAs and LNAs), and transmit and receive array front-end test articles.

Performers will deliver a minimum of four (4) of each of compact multi-finger transistor cells, on-chip and off-chip interconnect test structures, MMICs (PAs and LNAs), and transmit and receive array front-end test articles in accordance with the schedule above for independent verification and validation (IV&V) by government SMEs. To ensure consistency in characterization, the performer, in consultation and collaboration with the government IV&V team, will design and fabricate appropriate on-chip and off-chip interconnect test structures, multi-finger transistor cells, MMICs and array test articles and generate a test methodology and test plan. This includes appropriate on-wafer test structures. End of Phase deliverables should be received by the government no less than six (6) weeks before end of phase to allow time for IV&V and so that performers moving to the next phase will be continuously funded.

G. Government Furnished Equipment/Property/Information

No Government Furnished Equipment, Property, or Information will be provided for the effort solicited in this BAA.

H. Intellectual Property

Any use of proposer-defined intellectual property (patents, proprietary information, etc.) should be clearly marked as such within the proposal. Include all proprietary claims to the results, prototypes, intellectual property, or systems supporting the effort and/or necessary for the use of the research, results and/or prototype. If there are no proprietary claims, this should be stated.

For forms to be completed regarding intellectual property, see Section IV.B.10.

II. Award Information

A. General Award Information

Multiple awards are anticipated. The amount of resources made available under this BAA will depend on the quality of the proposals received and the availability of funds.

The Government reserves the right to select for negotiation all, some, one, or none of the proposals received in response to this solicitation, and to make awards without discussions with proposers. The Government also reserves the right to conduct discussions if it is later determined to be necessary. If warranted, portions of resulting awards may be segregated into pre-priced options. Additionally, DARPA reserves the right to accept proposals in their entirety or to select only portions of proposals for award. In the event that DARPA desires to award only portions of a proposal, negotiations may be opened with that proposer. The Government reserves the right to fund proposals in phases with options for continued work at the end of one or more of the phases, as applicable.

Awards under this BAA will be made to proposers on the basis of the evaluation criteria listed below (see section labeled “Application Review Information,” Sec. V.), and program balance to provide overall value to the Government. The Government reserves the right to request any additional, necessary documentation once it makes the award instrument determination. Such additional information may include but is not limited to Representations and Certifications (see Section VI.B.4., “Representations and Certifications”). The Government reserves the right to remove proposers from award consideration should the parties fail to reach agreement on award terms, conditions and cost/price within a reasonable time or the proposer fails to timely provide requested additional information. Proposals identified for negotiation may result in a procurement contract or other transaction, depending upon the nature of the work proposed, the required degree of interaction between parties, whether or not the research is classified as Fundamental Research, and other factors.

Proposers looking for innovative, commercial-like contractual arrangements are encouraged to consider requesting Other Transactions. To understand the flexibility and options associated with Other Transactions, consult http://www.darpa.mil/work-with-us/contract-management#OtherTransactions.

In accordance with 10 U.S.C. § 2371b(f), the Government may award a follow-on production contract or Other Transaction (OT) for any OT awarded under this solicitation if: (1) that participant in the OT, or a recognized successor in interest to the OT, successfully completed the entire prototype project provided for in the OT, as modified; and (2) the OT provides for the http://www.darpa.mil/work-with-us/contract-management#OtherTransactions http://www.darpa.mil/work-with-us/contract-management#OtherTransactions award of a follow-on production contract or OT to the participant, or a recognized successor in interest to the OT.

In all cases, the Government contracting officer shall have sole discretion to select award instrument type, regardless of instrument type proposed, and to negotiate all instrument terms and conditions with selectees. DARPA will apply publication or other restrictions, as necessary, if it determines that the research resulting from the proposed effort will present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Any award resulting from such a determination will include a requirement for DARPA permission before publishing any information or results on the program. For more information on publication restrictions, see the section below on Fundamental Research.

B. Fundamental Research

It is DoD policy that the publication of products of fundamental research will remain unrestricted to the maximum extent possible. National Security Decision Directive (NSDD) 189 defines fundamental research as follows:

‘Fundamental research’ means basic and applied research in science and engineering, the results of which ordinarily are published and shared broadly within the scientific community, as distinguished from proprietary research and from industrial development, design, production, and product utilization, the results of which ordinarily are restricted for proprietary or national security reasons.

As of the date of publication of this solicitation, the Government expects that program goals as described herein may be met by proposed efforts for fundamental research and non-fundamental research. Some proposed research may present a high likelihood of disclosing performance characteristics of military systems or manufacturing technologies that are unique and critical to defense. Based on the anticipated type of proposer (e.g., university or industry) and the nature of the solicited work, the Government expects that some awards will include restrictions on the resultant research that will require the awardee to seek DARPA permission before publishing any information or results relative to the program.

Proposers should indicate in their proposal whether they believe the scope of the research included in their proposal is fundamental or not. While proposers should clearly explain the intended results of their research, the Government shall have sole discretion to determine whether the proposed research shall be considered fundamental and to select the award instrument type. Appropriate language will be included in resultant awards for non-fundamental research to prescribe publication requirements and other restrictions, as appropriate. This language can be found at http://www.darpa.mil/work-with-us/additional-baa.

For certain research projects, it may be possible that although the research to be performed by a potential awardee is non-fundamental research, its proposed subawardee’s effort may be fundamental research. It is also possible that the research performed by a potential awardee is fundamental research while its proposed subawardee’s effort may be non-fundamental research.

In all cases, it is the potential awardee’s responsibility to explain in its proposal which proposed efforts are fundamental research and why the proposed efforts should be considered fundamental research.

http://www.darpa.mil/work-with-us/additional-baa

III. Eligibility Information

A. Eligible Applicants

All responsible sources capable of satisfying the Government's needs may submit a proposal that shall be considered by DARPA.

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

a) FFRDCs

FFRDCs are subject to applicable direct competition limitations and cannot propose to this solicitation in any capacity unless they meet the following conditions. (1) FFRDCs must clearly demonstrate that the proposed work is not otherwise available from the private sector. (2) FFRDCs must provide a letter, on official letterhead from their sponsoring organization, that (a) cites the specific authority establishing their eligibility to propose to Government solicitations and compete with industry, and (b) certifies the FFRDC’s compliance with the associated FFRDC sponsor agreement’s terms and conditions. These conditions are a requirement for FFRDCs proposing to be awardees or subawardees.

b) Government Entities

Government Entities (e.g., Government/National laboratories, military educational institutions, etc.) are subject to applicable direct competition limitations. Government Entities must clearly demonstrate that the work is not otherwise available from the private sector and provide written documentation citing the specific statutory authority and contractual authority, if relevant, establishing their ability to propose to Government solicitations and compete with industry. This information is required for Government Entities proposing to be awardees or subawardees.

c) Authority and Eligibility

At the present time, DARPA does not consider 15 U.S.C. § 3710a to be sufficient legal authority to show eligibility. While 10 U.S.C.§ 2539b may be the appropriate statutory starting point for some entities, specific supporting regulatory guidance, together with evidence of agency approval, will still be required to fully establish eligibility. DARPA will consider FFRDC and Government Entity eligibility submissions on a case-by-case basis; however, the burden to prove eligibility for all team members rests solely with the proposer.

2. Other Applicants

Non-U.S. organizations and/or individuals may participate to the extent that such participants comply with any necessary nondisclosure agreements, security regulations, export control laws, and other governing statutes applicable under the circumstances.

B. Organizational Conflicts of Interest

FAR 9.5 Requirements In accordance with FAR 9.5, proposers are required to identify and disclose all facts relevant to potential OCIs involving the proposer’s organization and any proposed team member (subawardee, consultant). Under this Section, the proposer is responsible for providing this disclosure with each proposal submitted to the solicitation. The disclosure must include the proposer’s, and as applicable, proposed team member’s OCI mitigation plan. The OCI mitigation plan must include a description of the actions the proposer has taken, or intends to take, to prevent the existence of conflicting roles that might bias the proposer’s judgment and to prevent the proposer from having unfair competitive advantage. The OCI mitigation plan will specifically discuss the disclosed OCI in the context of each of the OCI limitations outlined in FAR 9.505-1 through FAR 9.505-4.

Agency Supplemental OCI Policy In addition, DARPA has a supplemental OCI policy that prohibits contractors/performers from concurrently providing Scientific Engineering Technical Assistance (SETA), Advisory and Assistance Services (A&AS) or similar support services and being a technical performer.

Therefore, as part of the FAR 9.5 disclosure requirement above, a proposer must affirm whether the proposer or any proposed team member (subawardee, consultant) is providing SETA, A&AS, or similar support to any DARPA office(s) under: (a) a current award or subaward; or (b) a past award or subaward that ended within one calendar year prior to the proposal’s submission date.

If SETA, A&AS, or similar support is being or was provided to any DARPA office(s), the proposal must include:

The name of the DARPA office receiving the support;

The prime contract number;

Identification of proposed team member (subawardee, consultant) providing the support; and An OCI mitigation plan in accordance with FAR 9.5.

Government Procedures In accordance with FAR 9.503, 9.504 and 9.506, the Government will evaluate OCI mitigation plans to avoid, neutralize or mitigate potential OCI issues before award and to determine whether it is in the Government’s interest to grant a waiver. The Government will only evaluate OCI mitigation plans for proposals that are determined selectable under the solicitation evaluation criteria and funding availability.

The Government may require proposers to provide additional information to assist the Government in evaluating the proposer’s OCI mitigation plan.

If the Government determines that a proposer failed to fully disclose an OCI; or failed to provide the affirmation of DARPA support as described above; or failed to reasonably provide additional information requested by the Government to assist in evaluating the proposer’s OCI mitigation plan, the Government may reject the proposal and withdraw it from consideration for award.

C. Cost Sharing/Matching

Cost sharing is not required; however, it will be carefully considered where there is an applicable statutory condition relating to the selected funding instrument. Cost sharing is encouraged where there is a reasonable probability of a potential commercial application related to the proposed research and development effort.

For more information on potential cost sharing requirements for Other Transactions for Prototype, see http://www.darpa.mil/work-with-us/contract-management and https://acquisitioninnovation.darpa.mil.

IV. Application and Submission Information

PROPOSERS ARE CAUTIONED THAT EVALUATION RATINGS MAY BE LOWERED

AND/OR PROPOSALS REJECTED IF PROPOSAL PREPARATION (PROPOSAL FORMAT,

CONTENT, ETC.) AND/OR SUBMITTAL INSTRUCTIONS ARE NOT FOLLOWED.

A. Address to Request Application Package

This announcement, any attachments, and any references to external websites herein constitute the total solicitation. If proposers cannot access the referenced material posted in the announcement found at www.darpa.mil, contact the administrative contact listed herein.

B. Content and Form of Application Submission

All submissions, including abstracts and proposals must be written in English with type not smaller than 12 point font. Smaller font may be used for figures, tables, and charts. Copies of all documents submitted must be clearly labeled with the DARPA BAA number, proposer organization, and proposal title/proposal short title.

1. Abstract Format

Proposers are strongly encouraged to submit an abstract in advance of a full proposal. Abstracts should follow the format described below in this section. The cover sheet should be clearly marked “ABSTRACT” and the total length of Section II should not exceed 4 pages.

Section I. Administrative

A. Cover sheet to include:

(1) BAA number (HR001121S0042);

(2) Lead Organization submitting abstract;

(3) Type of organization, selected among the following categories:

Large Organization, Small Disadvantaged Organization, Other Small Organization, HBCU, MI, Other Educational, Other Nonprofit;

(4) Proposer’s internal reference number (if any);

(5) Other team members (if applicable) and type of organization for each;

(6) Proposal title;

(7) Technical point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(8) Administrative point of contact to include:

http://www.darpa.mil/work-with-us/contract-management https://acquisitioninnovation.darpa.mil/ http://www.darpa.mil/

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(9) Total funds requested from DARPA, and the amount of cost share (if any); AND

(10) Date proposal abstract was submitted.

(Note: An official transmittal letter is not required when submitting a Proposal Abstract.)

Section II. Abstract Details

A. Innovative Claims Summary of innovative claims for the proposed research. This section is the centerpiece of the abstract and should succinctly describe the uniqueness and benefits of the proposed approach relative to the current state-of-art alternate approaches.

B. Technical Approach Technical rationale, technical approach, and constructive plan for accomplishment of technical goals in support of innovative claims and deliverable production.

C. Deliverables Deliverables associated with the proposed research and the plans and capability to accomplish technology transition and commercialization.

D. Cost and Schedule Provide a cost estimate for resources (e.g. labor, materials) and any subcontractors over the proposed timeline of the project, broken down by Government fiscal year.

2. Full Proposal Format

All full proposals must be in the format given below. Proposals shall consist of two volumes:

Volume I – Technical and Management Proposal (3 sections), and Volume II – Cost Proposal (4 sections). The submission of other supporting materials along with the proposals is strongly discouraged and will not be considered for review. Section II of Volume I, Technical and Management Proposal, shall not exceed 25 pages. The page limitation for full proposals includes all figures, tables, and charts. There is no page limit for Volume II, Cost Proposal.

A summary slide of the proposed effort, in PowerPoint format, should be submitted with the proposal. A template slide is provided as Attachment 2 to the BAA. Submit this PowerPoint file in addition to Volumes I and II of your full proposal. This summary slide does not count towards the total page count.

a. Volume I, Technical and Management Proposal

Section I. Administrative

A. Cover sheet to include:

(1) BAA number (HR001121S0042);

(2) Lead Organization submitting proposal;

(3) Type of organization, selected among the following categories:

Large Organization, Small Disadvantaged Organization, Other Small Organization, HBCU, MI, Other Educational, Other Nonprofit;

(4) Proposer’s internal reference number (if any);

(5) Other team members (if applicable) and type of organization for each;

(6) Proposal title;

(7) Technical point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(8) Administrative point of contact to include:

Salutation, last name, first name, street address, city, state, zip code (+4), telephone, fax (if available), electronic mail;

(9) Total funds requested from DARPA, and the amount of cost share (if any); AND

(10) Date proposal was submitted.

B. Official transmittal letter.

The transmittal letter should identify the BAA number, the proposal by name, and the proposal reference number (if any), and should be signed by an individual who is authorized to submit proposals to the Government.

Section II. Detailed Proposal Information

A. Executive Summary Summarize the technical approach, anticipated performance, and expected outcomes of the proposed effort. The executive summary should be concise and to the point. Tables, graphs, and diagrams can be used as supplemental material along with narrative to convey the information.

B. Technical Approach This section is the centerpiece of the proposal and should succinctly summarize the innovative claims for the proposed research and clearly describe the proposed approach without using any jargon. This section should demonstrate that the proposer has a clear understanding of the state-of-the-art and should provide sufficient justification for the feasibility of the proposed approach(es). This section should include a detailed technical rationale, technical approach, and constructive plan for accomplishment of technical goals in support of innovative claims and deliverable creation. The proposal must provide a detailed analysis of how the proposed approach will meet the DARPA metrics and goals, with particular emphasis on describing the approach to meeting the MMIC and array front-end test article efficiency metrics and size goals.

The Technical Approach must:

Clearly state how the Technical Approach will address all of the Technical Challenges stated in the Program Description including the assumptions and rationale of the proposed on-chip and off-chip interconnect technology

Provide detailed description of the proposed MMIC and array front-end test article architecture and compaction/integration approach including modeling, simulation, and/or…