HR001120S0008-Amendment-01.pdf

HR001120S0008

Broad Agency Announcement Lasers for Universal Microscale Optical Systems (LUMOS)

Microsystems Technology Office

HR001120S0008

November 18, 2019

Amendment 1 As amended on November 26, 2019

FOREWORD

In June 2017, DARPA announced the Electronics Resurgence Initiative (ERI) as a bold response to several critical emerging trends. Among them, the cost and complexity of advanced microelectronics design and manufacture has increased rapidly, challenging Gordon Moore’s economic premise that future machines would require lower costs and shorter turnaround times.

For the first time, the defense community faces few or no options for accessing leading-edge electronics, the result of cost-driven foundry consolidation. Meanwhile, non-market foreign forces are working to shift the electronics innovation engine overseas, challenging U.S.

economic and security advantages. In addition, the nation is gaining a new appreciation for electronics security—a longtime defense concern—following publicized challenges to our digital backbone in sectors as diverse as automotive, cybersecurity, and voting. ERI envisioned a unified national response marked by research collaborations between DARPA, the defense community, academia, and the commercial sector.

There is significant historical precedent to suggest the viability of this approach; each wave of modern electronics development has benefitted from the combination of defense-funded academic research and commercial sector investment. In the 1980s, when geometric scaling started to make low-volume integrated circuit fabrication unaffordable, DARPA’s investment in the Metal Oxide Silicon Implementation Service (MOSIS) opened the door to rapid, low-cost chip manufacture, laying the foundation for the nation’s world-leading fabless design industry. In the 1990’s, a combination of defense, academic, and commercial partners pioneered 193 nm lithography, which became the industry-critical fabrication process. Then, as Dennard scaling ended in the 2000’s, the semiconductor industry adopted Fin Field Effect Transistors (FinFETs), another DARPA-funded innovation that drove to low power computing and led to the era of 3D devices.

The nation now stands ready to innovate a 4th wave of electronics progress. The state of the industry indicates that the 4th wave will be defined by three-dimensional heterogeneous integration. Through integration, innovators will add new materials and devices to the silicon foundation and enable intelligence and specialized functions precisely designed to meet the diversifying needs of the commercial and defense sectors. 3D heterogeneous integration will also demand new architectures and design tools, developed to manage the complexity of working in three dimensions while enabling rapid system upgrades and integrating security as a primary design concern. These areas—3D heterogeneous integration, new materials and devices, specialized functions, and design and security—have been central to ERI since its inception and will continue to guide the initiative as it enters its third year.

The 4th wave of electronics progress, however, is neither inevitable nor inevitably beneficial to the United States. As a community, the collective challenge faced by DARPA and its ERI partners will be to ensure that benefits differentially accrue to the U.S. commercial and defense base, which is aggressively investing in continued progress. To meet our national security needs, 4th wave technologies must enable more capable systems that process data locally, extract actionable information, and make decisions at “the edge”. To address new security concerns, 4th wave technologies must integrate security considerations into microsystem design in a way that is both effective and easy to implement. To address the rapid rise of devices operating at the edge, the glut of information those devices will collect, and the growing cyber-driven threats those devices will encounter, 4th wave technologies must find ready adoption by the commercial and defense sectors. New and existing ERI programs will therefore increasingly address the challenge of transitioning 4th wave technologies to the domestic sectors that need them.

Together with the ongoing ERI programs, the program addressed in this Broad Agency Announcement (BAA) will continue to provide a foundational contribution both to U.S. national security and to the needs and ambitions of the domestic commercial sector. DARPA seeks to receive proposals from entities that can help to achieve this goal. For reference, an updated list of ERI programs, solicitations, and events is available via https://www.darpa.mil/work-with-us/electronics-resurgence-initiative.

https://www.darpa.mil/work-with-us/electronics-resurgence-initiative https://www.darpa.mil/work-with-us/electronics-resurgence-initiative

Table of Contents

FOREWORD

PART I: OVERVIEW INFORMATION

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description A. Background B. Program Description C. Program Structure D. Technical Areas Details

1. Technical Area 1 (TA1) – Scaling Complexity with Gain

2. Technical Area 2 (TA2) – High Power Gain

3. Technical Area 3 (TA3) – Broad Spectrum Gain

E. Schedule/Milestones

1. Technical Area 1 Schedule and Milestones

2. Technical Area 2 Schedule and Milestones

3. Technical Area 3 Schedule and Milestones

F. Deliverables G. Government Furnished Equipment/Property/Information H. Intellectual Property

II. Award Information A. General Award Information B. Fundamental Research

III. Eligibility Information A. Eligible Applicants

1. Federally Funded Research and Development Centers (FFRDCs) and Government Entities

B. Organizational Conflicts of Interest C. Cost Sharing/Matching D. Associate Contractor Agreement Clause E. Other Eligibility Criteria

1. Collaborative efforts IV. Application and Submission Information

A. Address to Request Application Package B. Content and Form of Application Submission

1. Abstract Format

2. Full Proposal Format

3. Proprietary Information

4. Security Information

a. Program Security Information

b. Unclassified Submissions

c. Classified Submissions

5. Disclosure of Information and Compliance with Safeguarding Covered Defense

Information Controls

6. Human Subjects Research (HSR)/Animal Use

7. Approved Cost Accounting System Documentation

8. Section 508 of the Rehabilitation Act (29 U.S.C. § 749d)/FAR 39.2

9. Small Business Subcontracting Plan

10. Intellectual Property

a. For Procurement Contracts

b. For All Non-Procurement Contracts

11. Patents

12. System for Award Management (SAM) and Universal Identifier Requirements

13. Funding Restrictions

C. Submission Information

1. Submission Dates and Times

a. Abstract Due Date

b. Full Proposal Date

c. Frequently Asked Questions (FAQ)

2. Abstract Submission Information

3. Proposal Submission Information

a. For Proposers Requesting Cooperative Agreements:

b. For Proposers Requesting Contracts or Other Transaction Agreements

c. Classified Submission Information

4. Other Submission Requirements

V. Application Review Information A. Evaluation Criteria

1. Overall Scientific and Technical Merit

2. Potential Contribution and Relevance to the DARPA Mission

3. Cost Realism

B. Review and Selection Process

1. Review Process

2. Handling of Source Selection Information

3. Federal Awardee Performance and Integrity Information (FAPIIS)

VI. Award Administration Information A. Selection Notices

1. Abstracts

2. Proposals

B. Administrative and National Policy Requirements

1. Meeting and Travel Requirements

2. FAR and DFARS Clauses

3. Controlled Unclassified Information (CUI) on Non-DoD Information Systems

4. Representations and Certifications

5. Terms and Conditions

C. Reporting D. Electronic Systems

1. Wide Area Work Flow (WAWF)

2. i-Edison

3. TFIMS

VII. Agency Contacts VIII. Other Information

A. Proposers Day

B. Protesting

ATTACHMENT 1: Cost Volume Proposer Checklist ATTACHMENT 2: Proposal Summary Slide Template

PART I: OVERVIEW INFORMATION

Federal Agency Name: Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO)

Funding Opportunity Title: Lasers for Universal Microscale Optical Systems

(LUMOS)

Announcement Type: Initial Announcement Funding Opportunity Number: HR001120S0008 Catalog of Federal Domestic Assistance Numbers (CFDA): 12.910 Research and

Technology Development Dates: (All times listed herein are Eastern Time) o Posting Date: November 18, 2019 o Proposers Day: November 20, 2019 o Abstract Due Date: December 11, 2019 at 1:00 PM o FAQ Submission Deadline: January 24, 2020 at 1:00 PM o Proposal Due Date: February 7, 2020 at 1:00 PM o Estimated period of performance start: July 1, 2020

Concise description of the funding opportunity: The DARPA Microsystems Technology Office is soliciting innovative research proposals to develop heterogeneous photonic integrated circuit platforms that incorporate on-chip optical gain for disruptive optical microsystems.

Anticipated Funding Available for Award: Approximately $70M of total funding is anticipated for awards made against this BAA, with a distribution of:

o $40M in Technical Area 1 (TA1) o $15M in Technical Area 2 (TA2) o $15M in Technical Area 3 (TA3)

Anticipated individual awards: Multiple awards are anticipated in each Technical Area.

Anticipated funding type: 6.2 Types of instruments that may be awarded: Procurement contract, cooperative agreement or other transaction.

Agency contact:

o Dr. Gordon Keeler, Program Manager BAA Coordinator: HR001120S0008@darpa.mil

DARPA/MTO

ATTN: HR001120S0008

675 North Randolph Street Arlington, VA 22203-2114 mailto:name@darpa.mil

PART II: FULL TEXT OF ANNOUNCEMENT

I. Funding Opportunity Description

The Defense Advanced Research Projects Agency (DARPA) often selects its research efforts through the Broad Agency Announcement (BAA) process. This BAA is being issued, and any resultant selection will be made, using the procedures under Federal Acquisition Regulation (FAR) 6.102(d)(2) and 35.016 and 2 C.F.R. § 200.203. Any negotiations and/or awards will use procedures under FAR 15.4, Contract Pricing. Proposals received as a result of this BAA shall be evaluated in accordance with evaluation criteria specified herein through a scientific review process.

DARPA BAAs are posted on the Beta SAM website, under the Contract Opportunities (FBO) link, at https://beta.sam.gov/, and, as applicable, the Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to this BAA.

The DARPA Microsystems Technology Office is soliciting innovative research proposals to develop heterogeneous photonic integrated circuit platforms that incorporate on-chip optical gain for disruptive optical microsystems. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice.

A. Background

Lasers have made a tremendous impact upon our world; they are essential to diverse fields such as optical communications, remote sensing, manufacturing, and medicine. Although the semiconductor laser was first demonstrated almost 60 years ago, the importance of diode lasers has ensured that innovation in laser technology continues at a rapid pace even today.

Semiconductor fabrication techniques developed by the microelectronics industry have enabled microscopic diode lasers and the miniaturization of almost every optical component imaginable.

Integrated photonics, which combines many such elements onto a single chip, has transformed the way we engineer optical systems and represents the fastest growing field of photonics technology. This photonic integration creates not only dramatic advantages in size, weight, power, and cost, but also provides opportunity for large gains in system performance, new functionality, and design flexibility.

Photonic integrated circuits (PICs) take several forms and are typically defined by the fundamental material used to create the integrated device platform. Inherent characteristics of the base materials lend strengths and weaknesses to each photonics approach. Compound semiconductors offer the important benefit of intrinsic optical gain and can be used to create efficient diode lasers and optical amplifiers of various designs. However, when used to build “active” integrated platforms, compound semiconductors suffer challenges that include limited manufacturing maturity, low component density due to weak confinement, and high propagation losses. These drawbacks have been largely avoided through “passive” silicon photonics platforms that emerged in the early 2000s. Such technologies offer low-loss, high-density photonic integration in accessible foundry environments and strongly leverage advances in electronics manufacturing. The selection of available materials has expanded rapidly to include https://beta.sam.gov/ http://www.grants.gov/ not only silicon, but germanium, silica, and silicon nitride, while thin-film lithium niobate and numerous alternative materials show promise to enable key performance advantages.

Nevertheless, the absence of intrinsic optical gain remains a critical limitation for optical microsystems built with such passive PICs.

Lacking availability of a complete integration solution, optical systems must employ components from different technology platforms today, combining diode lasers, integrated passive photonics, and optical fibers through various precision assembly techniques. This approach presents several problems beyond the obvious issues of non-ideal size, weight, and power (SWaP). The limited flexibility of such packaging approaches hampers performance and reduces the design innovation advantages of foundry-sourced photonics. Moreover, custom packaging is typically most effective only for high-volume applications that can tolerate the considerable non-recurring development costs, while specialty users who demand higher performance such as lower noise, higher power, or operation in different spectral bands are forced to employ benchtop or separately-packaged discrete products. The lack of an integrated platform with complete functionality prevents greater photonics deployment and impact throughout many commercial sectors as well as across the Department of Defense (DoD).

Intimate heterogeneous integration represents a compelling path to combine best-in-class materials for universal photonics platforms that incorporate efficient optical gain, high-speed modulation and detection, and low-loss passive functionality on a single substrate. The past decade has seen extensive research on new materials that improve the performance of integrated photonics, as well as the development of promising heterogeneous integration techniques that can combine various materials during the fabrication process. However, there remains a large gap between today’s capabilities and the mature platforms needed to address most DoD-relevant applications.

B. Program Description

The objective of LUMOS is to bring efficient on-chip optical gain to highly-capable integrated photonics platforms and enable complete photonics functionality on a single substrate for disruptive optical microsystems. LUMOS platforms will integrate lasers and amplifiers with high-performance modulators, waveguides, and detectors for diverse use cases, including digital and analog communications, navigation and timing, long-range sensing, microwave signal generation and processing, and quantum sensing and computing. Such uses demand a diversity of material combinations on photonics platforms tailored to address specific application areas.

LUMOS will develop transformative PIC capabilities through heterogeneous integration to achieve integrated photonics scalability along three key directions: complexity, power, and spectrum.

First, LUMOS seeks to dramatically scale the complexity and performance of very-large-scale integration (VLSI) photonic circuits through the development of an active platform that supports the integration of thousands of optical components on a single silicon chip. The fabrication of photonic circuits with >10,000 elements is possible today in high-yield foundry environments, but high optical losses limit the practical benefits of this scalability. LUMOS will add flexible, high-density gain blocks that enable on-chip lasers and amplifiers for complexity scaling, overcoming on-chip losses through gain. Second, LUMOS seeks to transform high-power integrated photonics capabilities through the co-integration of low-noise, Watt-class lasers and amplifiers with fast analog components. Such a platform is expected to require intimate integration of gain with low-loss optical materials capable of high saturation power levels, in combination with materials that support fast radio frequency (RF) modulation and detection for high dynamic range applications. Finally, LUMOS seeks to create unprecedented capabilities for emerging visible and near-infrared applications through the development of a broadband visible and near-infrared photonics platform. Maximum utility would be achieved by a complete set of advanced components, including modulators, detectors, and narrow linewidth light sources, all capable of supporting operation across a wide spectral regime. These goals may be attained through the intimate combination of high-transparency substrates, direct emission materials at non-telecom wavelengths, and nonlinear nanophotonic devices that enable greater spectral access than individual gain materials can provide.

The LUMOS program will initially demonstrate on-chip gain integration of high-performance lasers and amplifiers. Next, LUMOS will demonstrate complete active PIC platforms tailored to meet specific application needs, driving improvements of both on-chip gain elements and supporting photonic components. Ultimately, LUMOS will deliver single-chip photonics demonstrators for each platform, targeting DoD-relevant concepts that are intended both to showcase platform capabilities and illustrate the compelling performance gains that can be achieved beyond current solutions. In order to meet these goals, LUMOS is soliciting innovative research proposals in three main Technical Areas (TAs):

Technical Area 1 (TA1) – Scaling Complexity with Gain This technical area will integrate dense, flexible optical gain in a silicon photonics foundry to achieve revolutionary VLSI photonic circuit technology. LUMOS TA1 will capitalize on the maturity of scalable passive photonics platforms, high precision foundry fabrication, and emerging technologies for gain integration to create complete photonic circuits with thousands of elements. This TA will establish an active silicon photonics platform in an 8" or 12" foundry that allows intimate integration of custom lasers and optical amplifiers with state-of-the-art active and passive component functionality. LUMOS TA1 will provide this capability to PIC designer teams (identified by the Government in later LUMOS phases) through multiple project wafer runs (MPWs) with preliminary process design kits (PDKs) developed during the TA1 activity. It is expected that the technologies created under TA1 will enable enduring dual-use access to active silicon photonics for both the defense and commercial user base.

Technical Area 2 (TA2) – High Power Gain This technical area will integrate optical gain with low-loss materials that enable RF operation beyond 100 GHz to create high-power, high-speed photonics platforms. The development of low-noise Watt-class lasers and amplifiers integrated with broadband active and passive components will meet a number of critical defense applications, including high dynamic range microwave signal processing and long-range optical communication needs. Technologies developed in TA2 are expected to address moderate-volume, defense-specific applications and commercial needs.

Technical Area 3 (TA3) – Broad Spectrum Gain This technical area will develop visible and near-infrared photonics platforms with integrated light sources and full component functionality that support new classes of applications. In particular, platform metrics target the need to address spectral signatures from various atomic and molecular species for critical sensing, timing, and quantum information applications.

LUMOS TA3 seeks revolutionary breakthroughs in nanophotonics, nonlinear materials, and integrated laser architectures to enable a complete platform that supports operation from 400 nm to 900 nm, with ultra-narrow linewidth, high-performance lasers available to designers across the entire spectral regime.

C. Program Structure

LUMOS will be a 48-month program divided into three phases with goals summarized below:

Phase 1 (base) – 18 months: Develop materials, demonstrate gain integration, characterize performance of individual components Phase 2 (option) – 18 months: Scale active and passive device performance, combine components for complete PIC platforms Phase 3 (option) – 12 months: Improve manufacturability and support photonics design teams (TA1); Develop system demonstrations highlighting the capabilities of each LUMOS platform (TA2, TA3)

DARPA anticipates funding a variety of technical approaches within the LUMOS program. It is expected that fewer performers will be funded to participate in Phases 2 and 3 of the program.

Options may be exercised, at the Government’s sole discretion, based on technical progress measured against the metrics and milestones defined in this BAA and funding availability.

D. Technical Areas Details

LUMOS seeks proposals in three main Technical Areas. Entities may submit to more than one Technical Area, and multiple proposals per organization are permitted. Each proposal must address only a single TA and include all phases.

1. Technical Area 1 (TA1) – Scaling Complexity with Gain

Rationale and Vision Advanced microelectronics manufacturing processes, coupled with commercial data center market drivers, have helped to establish silicon photonics as the premier platform for PIC innovation. Foundries have lowered the access barriers to state-of-the-art manufacturing, offering flexible PDKs to enable innovative designers and routinely providing MPWs for low-cost prototyping. Largely mirroring the ecosystem of CMOS electronics, silicon photonics research and development has become increasingly segmented: designers are empowered by sophisticated simulation software, capable IP blocks, and automated design tools; however, they are also largely removed from fabrication process development, and their designs are limited by foundry capabilities.

The goal of TA1 is to greatly enhance foundry capabilities by developing flexible, high-density optical gain functionality for state-of-the-art silicon photonics and to make the capability accessible to foundry users. LUMOS has a broad vision of establishing optical gain as an integral part of the silicon photonics toolbox, providing greater design freedom for photonics designers and enabling the creation of new markets.

Intriguing concepts for high-complexity PICs, from compact single chip sensors to photonic accelerators for signal processing and non-von Neumann computing, have been described and prototyped with silicon photonics. The rapid pace of technology development and straightforward manufacturing of silicon photonics seems to promise a future where VLSI photonics solutions are ubiquitous. However, the lack of on-chip gain quickly breaks down any resemblance to the scalability of CMOS electronics, which benefits from the implicit gain residing in every transistor. The development of flexible optical gain within a foundry process will allow customization of on-chip lasers and amplifiers, putting innumerable new concepts within reach by clever design.

Performance Targets LUMOS TA1 emphasizes complexity scaling by demanding high component counts for both passive photonics components and newly-developed gain elements (i.e., 10,000+ total components and 1,000+ active elements per reticle). Design flexibility is also critical. Proposers to TA1 should describe their path to an active photonics platform that allows designers to develop custom laser structures using variable gain blocks, placed in adjustable locations, and accommodating a variety of shapes and sizes including rings, curves, and tapers. Such innovations could also feasibly enable alternative functionality, including for advanced modulators and nonlinear optical components.

While it is challenging to quantify the flexibility of various optical gain integration approaches, LUMOS exemplifies flexibility as gain block density. Optical gain blocks are the fundamental elements used to create derivative laser and amplifier components and assumed to operate at traditional telecom wavelengths (i.e., in the O- or C-band). Gain blocks are defined as individually-addressable, electrically-driven light emitters capable of optical amplification and intimately coupled to a passive waveguide mode. Operation of gain blocks may be demonstrated through a combination of on-chip testing and characterization with additional components. Table 1 describes target metrics.

Potential approaches to TA1 could include, but are not necessarily limited to, hetero-epitaxial growth of compound semiconductors on silicon, use of defect-tolerant gain regions, and micro-transfer printing of chiplets. Incremental improvements to existing approaches, including assembly-like integration of pre-fabricated laser die, precision optical alignment of processed chips on interposers, or inflexible point solutions, are unlikely to meet program metrics and are inconsistent with the single-chip microsystems sought by LUMOS.

Beyond the demonstration of fundamental gain blocks that meet scalability goals, LUMOS presents demanding performance targets for lasers and amplifiers created within the foundry process. While designers will ultimately have the ability to customize the performance of such devices, TA1 technical progress will be verified by the demonstration of exemplary lasers and amplifiers whose target performance is specified in Table 1.

Platform Details To achieve complete PIC functionality, LUMOS requires gain blocks, lasers, and amplifiers to be integrated within a silicon photonics platform. The development of components within this platform lies outside the scope of the LUMOS TA1, but performers shall describe their photonics capability in the proposal, which shall include a full complement of standard non-gain elements, including passive waveguides, splitters, chip couplers, phase and amplitude modulators, and integrated detectors, all demonstrating performance consistent with state of the art (SoA).

Additionally, the LUMOS TA1 platform must include silicon nitride waveguides meeting the loss metrics prescribed in Table 1. Low-loss passive structures are important for complexity scaling, and although optical dispersion engineering methods are not explicitly called for in this BAA, such waveguides support emerging nonlinear nanophotonic devices such as optical frequency combs. The ability to address this field is of interest to the government, and alternative materials to silicon nitride may be proposed if they meet program metrics.

As in all LUMOS Technical Areas, the integration of optical gain will necessitate strategies for optical isolation that protects lasers from on-chip reflections, so proposers should provide an analysis of how their lasers will function in the context of a larger PIC and explain how isolation will be addressed. Proposals should provide in-depth discussions of possible technical approaches, including structures of potential device solutions, modeling and simulated performance, and critical measurements or process development tasks.

Technology Access A separate solicitation to select teams of photonics designers who will exercise the active photonics capabilities developed in TA1 can be anticipated at a future date. (See “Future Technical Area – Foundry Users,” below.) LUMOS TA1 performers should expect to interact with these design teams through Associate Contractor Agreements (ACAs) and to provide foundry access as part of their effort through preliminary PDKs and MPWs. Design teams will provide valuable feedback to the foundry and will be tasked to contribute innovative component-and system-level layouts for compelling applications that are aggregated and fabricated through MPW runs.

Preliminary active PDK development is a key requirement of TA1. DARPA recognizes that the pace of Phase 1 and Phase 2 technical development may not permit the high level of process stability and component characterization typical of commercial PDKs, so TA1 proposals should define the anticipated form and content of PDK versions 1 and 2 and how PDK access will be provided to potential users. It is expected that PDK version 3, finalized at the conclusion of the program, will be consistent with a commercially-available foundry offering.

Multi-project wafer runs are another key requirements of TA1. Performers shall provide three (3) MPWs over the course of the LUMOS program, with completion dates identified by the proposer but scheduled to provide a regular cadence consistent with ongoing design/fabrication/test cycles. Specific requirements of the MPW are outlined as Deliverables in Table 4.

As an element of Electronics Resurgence Initiative, LUMOS TA1 seeks to enable U.S. national security impact and support domestic manufacturing capabilities that strengthen DoD access to differentiating technologies. Proposers should document a plan describing the path to sustainable on-shore dual-use offerings after the completion of the DARPA LUMOS program.

Technologies and capabilities developed under TA1 funding have clear commercial applications, and performer cost share is highly encouraged.

Phases and Metrics Phase 1 – In the initial 18-month Phase 1, performers will develop on-chip gain that is incorporated with an 8" or 12" silicon photonics foundry platform and established through materials integration processes. Performance will be measured through complete internal short-loops that demonstrate functioning lasers, amplifiers, and low loss waveguides. As part of this phase, teams are also expected to establish a preliminary process development kit (PDK) that includes active and passive components for use by PIC design teams selected through an anticipated future solicitation (see Future Technical Area notes below).

Phase 2 (Option) – In the 18-month Phase 2, performers will demonstrate a density of 1,000 gain blocks and 10,000 photonic components per reticle, demonstrate high performance lasers and amplifiers, complete two MPW shuttle runs, and establish an updated PDK. The first MPW run is expected to include active components with performance similar to Phase 1 gain, amplifier, and laser targets, while the second MPW run is expected to provide active components with improved performance.

Phase 3 (Option) – In the 12-month Phase 3, performers will complete a third MPW run with active and passive component performance on par with Phase 2 metrics. Phase 3 focuses on yield improvement, release of a final PDK, and optimization of the platform for manufacturability.

Teams are expected to improve laser lifetime beyond 100,000 hours and demonstrate laser operation at temperatures above 120°C.

Table 1. Technical Area 1 (TA1): Scaling Complexity with Gain – Program Metrics

TA1 metric Description Phase 1 Phase 2 Phase 3

Active platform (1) Active MPWs - 2 1 Active PDK release 1 1 1 Gain block density (per reticle) 100 1,000 1,000 Passive component density (per reticle) 1,000 10,000 10,000

Amplifier (2) Saturation power 10 dBm 16 dBm - Gain 20 dB 30 dB - Wallplug efficiency 5% 10% - Noise figure 10 dB 6 dB -

Laser (3) Optical power 0 dBm 13 dBm 16 dBm Wallplug efficiency 10% 25% 40% Maximum operating temperature, Tmax > 60°C > 90°C > 120°C Lifetime (hours at Tmax) > 1,000 > 1,000 > 100,000

Passive waveguide (4) SiN waveguide loss 0.2 dB/cm 0.05 dB/cm - Resonator quality factor, Q 1 M 10 M -

(1) Foundry capability shall be accessible to designers through a complete PDK, with MPW offerings fabricated on ≥ 8" wafers.

Active PDK release shall include amplifier and laser components and shall permit tailoring of integrated gain block characteristics to enable additional, customized active components. Passive components shall be included in the PDK. Passive elements include all non-gain components, including waveguides, splitters, chip couplers, phase and amplitude modulators, and integrated detectors, all demonstrating performance consistent with SoA.

Gain blocks are defined as individually-addressable, electrically-driven light emitters that demonstrate optical amplification into a passive waveguide mode. Optical gain spectrum shall operate across a 30 nm span, defined by full-width half-maximum of photoluminescence spectrum or similar metrology, within the range of 1250 nm to 1600 nm as specified by proposers. Operation of gain blocks may be demonstrated through a combination of on-chip testing and characterization with external components.

The gain block density metric may be met by demonstrating a proportional number of gain blocks on at least one quarter of the reticle (e.g. 250 gain blocks in Phase 2), with the remainder of the reticle devoted to test structures and/or MPW designs as identified by the proposer. The government considers an approximately 2.5 cm x 2.5 cm repeated wafer area to represent a reticle. Significant departures from this concept should be noted in proposals.

(2) Amplifier power levels are measured on-chip in passive waveguide. Small-signal gain assumes -30 dBm input power.

(3) Laser shall operate with a single mode and >30 dB side-mode suppression ratio. Optical power is specified on chip. Accelerated lifetime testing is permissible provided sufficient evidence is provided to support reliability assertions.

Wallplug efficiency should include all critical power-consuming elements required for laser operation, including I-V drive power, control power (if needed), cooling power (if needed), coupling loss into waveguide, and other optical loss elements.

(4) Alternative materials to SiN may be used for the passive waveguide, provided the optical loss metric can be met. Justification for the use of alternative materials should be provided in the proposal.

Future Technical Area – Foundry Users

(This information is provided for reference only. DO NOT propose to this section.)

DARPA anticipates soliciting proposals for innovative PIC concepts through a solicitation to be announced at a later date. Such an effort is expected to align with the start of TA1 Phase 2, but is dependent on successful development of the technologies described above and the availability of funds.

Selected PIC design teams would contribute innovative component- and system-level layouts to TA1 performers using preliminary PDK releases. Designs would be aggregated by TA1 performers and fabricated through MPW runs. Fabricated die would be provided to design teams as government-furnished property (GFP) to facilitate component characterization and system demonstration tasks.

2. Technical Area 2 (TA2) – High Power Gain

Rationale and Vision Integrated microwave photonics offers many of the same compelling SWaP reduction advantages as in other technology domains and, moreover, holds the promise of intimate integration of high-speed CMOS electronics with complex photonic circuits. However, existing photonic platforms are not capable of fully capturing these benefits. Passive-based platforms such as silicon photonics often employ free carrier effects for optical modulation, but these mechanisms are slow and inefficient in comparison to electro-optic effects native to other materials, and, in combination with two-photon absorption, limit the achievable propagating power in microphotonic components. Active platforms such as indium phosphide photonics offer direct light emission, amplification, and modulation, but feature substantial propagation loss.

Such impediments are particularly restrictive to the performance of microwave photonic systems where high optical power is usually needed to maintain dynamic range, but also affect alternative high-power applications, including light detection and ranging (LIDAR), free-space optical communications, directed energy, and other long-range systems that accumulate dramatic losses over distance.

LUMOS TA2 seeks to circumvent the inherent power and speed limitations of existing photonics platforms through heterogeneous integration, leading to specialty photonics platforms for high-speed, high-power defense applications. The defining characteristic of TA2 is the pairing of high-power sources for light generation and amplification with high-power-handling, low-loss, broadband components for light manipulation and detection.

Performance Targets The target laser and amplifier performance metrics are specified in Table 2. The metrics table also identifies characteristics of the complete active platform, which refers to the full suite of components necessary for the creation of general-purpose, single-chip PICs. The development of comprehensive platforms that simultaneously facilitate broad application domains is a principal goal of the LUMOS program. To that end, TA2 requires all active and passive components to produce and/or support high-bandwidth radio-frequency modulation at high optical power and with low insertion and propagation loss, and proposals should discuss the general end-use capabilities produced by the active platform.

Proposals must identify a compelling single-chip optical microsystem concept to be demonstrated during Phase 3, as detailed below. A quantitative analysis of the specific application should be presented. While metrics of individual supporting components are not specified, it is expected that teams will need to develop modulators with low Vπ and insertion loss, along with high saturation power photodetectors in order to produce sufficient linearity and signal gain performance for links or other photonic circuit architectures. Proposers should identify all additional required optical component development and include the performance metrics for Phase 1, Phase 2, and Phase 3 required to meet performer-defined application needs.

Given the high-power aspect of TA2, proposals should include plans for thermal management and describe how these plans affect the packaging required to operate the Phase 2 and Phase 3 functional PIC.

As in all LUMOS Technical Areas, the integration of optical gain will necessitate strategies for optical isolation that protects lasers from on-chip reflections, so proposers should provide an analysis of how their lasers will function in the context of a larger PIC and explain how isolation will be addressed. Proposals should provide in-depth discussions of possible technical approaches, including structures of potential device solutions, modeling and simulated performance, and critical measurements or process development tasks.

Potential approaches to TA2 could include, but are not necessarily limited to, thin-film lithium niobate, thin-film III-V semiconductors, thin-film nitride compounds, die bonding of gain chips to low-loss dielectric films, and laser power combining. Incremental improvements to existing approaches, including assembly-like integration of pre-fabricated laser die, precision optical alignment of processed chips on interposers, or inflexible point solutions, are inconsistent with the single-chip microsystems sought by LUMOS.

Phases and Metrics Phase 1 – In the initial 18-month Phase 1, performers will demonstrate electrically-driven gain integrated on low-loss, high-power platforms to show the feasibility of the proposed approach and to validate component performance. In addition to lasers and amplifiers meeting the metrics described in Table 2, teams will be required to demonstrate active platform components, including modulators and detectors, with high-speed functionality. Characterization of lasers, amplifiers, and active platform components may be performed using different PICs in this phase, but all integration processes must be demonstrated to verify that single-chip component integration can be achieved in subsequent phases. In addition to quantitative measurements meeting the Phase 1 metrics, teams are required to show a clear path to the Phase 2 metrics through design, modeling, and simulation.

Phase 2 (Option) – In the 18-month Phase 2, performers will demonstrate high performance lasers with >500 mW output power and amplifiers with saturation power levels exceeding 2 W.

This phase will also require improvement of modulator and detector bandwidth, while verifying the power handling capacity of all supporting components on the platform. Performance of the platform components, lasers, and amplifiers must all be demonstrated on the same photonic integrated circuit to show proof of platform scaling and a path to meeting the Phase 3 targets.

Phase 3 (Option) – In the 12-month Phase 3, teams will further optimize laser performance and will leverage Phase 2 active platform components to demonstrate a performer-defined application that illustrates the platform capability. The PIC used for this demonstration is expected to include >100 integrated photonic components and use a total on-chip optical power of more than 1 W (summed across all components). The system demonstration must include all optical components integrated on a single LUMOS TA2 chip, but benchtop electronics are permitted. Proposals are expected to identify the system demonstration, specify the improvement provided by the LUMOS platform, and provide multiple Phase 3 system and component level performance metrics related to the demonstration. Note that Table 2 metrics reflect minimum performance; proposers may elect to exceed any component metric or continue to advance component performance throughout Phase 3 in order to support a compelling system demonstration. The proposed demonstration should be a compelling DoD-relevant application that showcases capability significantly beyond that achievable by today’s multi-chip systems.

Demonstration thrust areas DARPA considers of particular interest include, but are not limited to, RF/microwave/millimeter-wave signal processing and generation, free-space optical communications, and standoff sensing.

Technologies developed in Phase 3 of TA2 could be subject to Controlled Unclassified Information (CUI) regulation if certain combinations of capabilities are realized. Proposers should refer Section VI.B.3 and, if relevant, discuss how data and hardware will be safeguarded.

If applicable, a CUI guide may be included in awards against HR001120S0008.

Additional TA2 metrics are detailed in Table 2.

Table 2. Technical Area 2 (TA2): High Power Gain – Program Metrics

TA2 metric Description Phase 1 Phase 2 Phase 3

Laser (1) Output power 20 dBm 27 dBm 30 dBm Linewidth 1 MHz 10 kHz 1 kHz Wallplug efficiency 10% 20% 40% Relative intensity noise -145 dBc/Hz -160 dBc/Hz -175 dBc/Hz

Amplifier (2) Saturation power 20 dBm 33 dBm - Gain 20 dB 20 dB - Wallplug efficiency 5% 10% - Noise figure 10 dB 6 dB -

Active platform (3) RF bandwidth 50 GHz 80 GHz 110 GHz Waveguide loss 1 dB/cm 0.5 dB/cm 0.2 dB/cm

System demo (4) Total component count - - > 100 Total optical power - - > 1 W

(1) Laser shall be electrically-driven and operate in a single mode with >30 dB side-mode suppression ratio. Optical power is specified on chip.

Wallplug efficiency should include all critical power-consuming elements required for laser operation, including I-V drive power, control power (if needed), cooling power (if needed), coupling loss into waveguide, and other optical loss elements.

(2) Amplifier power levels are measured on-chip in passive waveguide. Small-signal gain assumes -30 dBm input power.

(3) Active platform shall include a full complement of passive waveguides, splitters, chip couplers, phase and amplitude modulators, and integrated detectors, all demonstrating performance consistent with state-of-the-art. 3-dB RF bandwidth applies to both phase modulators and integrated detectors, which shall be compatible with operation at the laser output power level specified for each phase. Waveguide loss is measured at laser output power level.

(4) System demo shall be a compelling user-defined application that leverages the unique platform capabilities of on-chip, high-power gain, and a high-bandwidth integrated platform, consistent with domains of interest defined in the BAA.

Component count includes all integrated active and passive elements. Total optical power includes the contribution from all on-chip lasers and amplifiers.

3. Technical Area 3 (TA3) – Broad Spectrum Gain

Rationale and Vision The development of integrated photonic platforms has historically focused on operation at wavelengths around 1300 nm or 1550 nm, driven by markets predominantly addressing fiber-based communications. Such photonics platforms are not directly applicable to visible and near-infrared applications, where the transparency of waveguide materials limits supported wavelengths. Emerging architectures show that photonics can enable breakthrough capabilities for strategic positioning, navigation, and timing (PNT), classical and quantum sensing, and visible light communications, but we remain hindered in SWaP and performance by the lack of available integrated photonics solutions. Optical microsystem prototypes operating in this regime must employ either tunable benchtop lasers, or pursue miniaturization of single-point solutions, resulting in systems with a poor path to deployment.

An example class of systems that showcase the need for integrated photonics at visible/near-IR wavelengths are high-performance PNT devices based on trapped atoms. On-going investment through the DARPA Atomic-Photonic Integration (A-PhI) program is significantly lowering the barrier to portable, high-performance timing solutions through development of a PIC-based trapped-atom clock, but will require miniaturization of lasers with over 6 different wavelengths for functions such as cooling and trapping, prior to development of a fully portable package. In addition to spanning a wide spectral range, each laser has unique and demanding linewidth and output power requirements. The specific wavelengths required are a function of the chosen atom and can vary drastically based on the final architecture choice, exemplifying the need to create a photonics platform for wavelength by design integrated photonics. This system illustrates just one of many emerging architectures, including new quantum and multi-spectral sensing solutions, which require access to wavelengths across the visible spectrum.

The goal of LUMOS TA3 is to create a fully functional specialty PIC platform, with supporting active and passive components, for single-chip photonic solutions in the 400 nm – 900 nm spectral regime. The defining characteristic of TA3 will be the creation of low-linewidth lasers in combination with active components (lasers, modulators, detectors) capable of spanning the full spectrum, on a single substrate. Teams will be expected to develop supporting passive components (low-loss waveguides, splitters, couplers) on the same platform for complete functionality. Gain materials, integration techniques, and fabrication processes developed in this TA are expected to support the full spectrum without recurring customization to ensure creation of a platform supporting “wavelength by design.” While each individual component does not need to span the full spectral bandwidth, a photonics designer should be able to design a component to operate successfully at each wavelength within this spectrum through mask layout alone.

Performance Targets Target laser, platform, and system metrics are defined in Table 3. After development of the components and platform in early phases, teams are expected to leverage this new capability for a performer-defined application. This single-chip optical microsystem concept shall be demonstrated during Phase 3, as detailed below. A quantitative analysis of the specific application should be presented. Proposers should identify any additional required optical component development and include the performance metrics for Phase 1, Phase 2, and Phase 3 required to meet performer-defined application needs.

As in all LUMOS Technical Areas, the integration of optical gain will necessitate strategies for optical isolation that protects lasers from on-chip reflections, so proposers should provide an analysis of how their lasers will function in the context of a larger PIC and explain how isolation will be addressed. Proposals should provide in-depth discussions of possible technical approaches, including structures of potential device solutions, modeling and simulated performance, and critical measurements or process development tasks.

Potential approaches to TA3 could include but are not necessarily limited to: heterogeneous integration of nonlinear nanophotonics in combination with direct emission gain material, engineering of semiconductor gain regions in combination with techniques to broaden gain bandwidth, and integration of low-loss materials and new optical cavity designs suitable for low linewidth lasers.

Phases and Metrics Phase 1 – In the initial 18-month Phase 1, performers will demonstrate electrically-injected lasers with the ability to access the full spectrum from 400 nm to 900 nm. A series of application-relevant wavelengths across the required spectral regime, to be defined by the Government at program kick-off, will need to be demonstrated for successful completion of Phase 1. Proposers should be prepared to demonstrate optical sources at any arbitrary wavelength(s) within the 400 nm to 900 nm range. In addition to lasers meeting the metrics described in Table 3, teams will be required to demonstrate platform components, including passive waveguides with low loss from 400 nm to 900nm.