Attachment_1-_Statement_of_Objectives_(SOO).pdf

STATEMENT OF OBJECTIVES

28 September 2018

Space Electronic Technology (SET) Advanced Memory for Space Applications

Purpose/Background

Radiation Hardened (RH) memory is currently employed throughout the military and space communities in everything from image processing to data storage applications. Existing RH memories lag behind advanced commercial memories in density, performance and power consumption by at least 5 technology generations (e.g., RH at 90nm, commercial at 22nm).

Modern RH density limitations require hundreds to thousands of memory chips to provide sufficient memory capacity to ensure sufficient memory for processing and imaging needs.

These large numbers of Integrated Circuits (ICs) result in large area and power consuming elements throughout the system.

The United States Air Force (USAF) is seeking proposals from offerors to improve the density, performance and power consumption of future space-system memory by adapting (e.g., hardening) advanced state-of- the-art (SOA) technologies. Significant reductions in size, weight, power, and cost (SWaP-C) will result in dramatic capability improvements for many defense systems. Proposals shall identify the innovative solutions SOA advancements that enable large SWAP-C improvements in for non-volatile (NV) memor y or volatile (V) memory for use in a variety of defense space applications including processing, imaging, and storage. In addition, proposals should provide strategic radiation hardened NV and/or V solutions that satisfy the needs of future Space and Missile Command (SMC) defense space missions.

Scope/performance objectives

Offerors shall address all areas call forth in the SOO.

Approaches are sought for memory technology(s) that meet a minimum capacity of 512Mbit per device for NV and 1Gbit per device for V, utilize a high bandwidth interface such as DDR3 or DDR4, and are capable of QML qualification. A technology of choice shall be identified at the onset of the project, having taken into consideration onshore Trusted design and design tools, manufacture, and test, intellectual property access, supplier sourcing, potential for high-reliability and high-yield, high data retention , and attainability of >300kRad(Si) total ionizing dose immunity. Additional requirements include a high degree (>80 LET) of latchup immunity, Single Event Upset (SEU) (<1e-10 error/bit-day), Single Event Functional Interrupt (SEFI) immunity and >1e8 rad/s dose rate immunity into the product performance trade space.

RH Memory Specifications

Parameter Threshold Objective

Density 512 Mbit NV or 1 Gbit V per device 1 Gbit NV and 2 Gbit V per device Core Voltages <1.5V 1.2V Interface DDR3 DDR4 Radiation (total dose) 300 krad(Si) 1000 krad(Si) Radiation (dose rate) >1e8 rad/s >1e9 rad/s Single Event Upset (SEU) <1e-10 error/bit-day <1e-12 error/bit-day Single Event Functional

Interrupt (SEFI) Immune Immune

Single Event Latchup (SEL) Immune Immune

The effort will develop test chips and methodologies to verify and characterize device performance provide a qualification plan, to QML qualify the resultant product and demonstrate expertise and capability for marketing and product support. Proposals shall address the design, layout, and fabrication (including the need for trusted electronics foundries) of the proposed concept; provide a space qualification plan; discuss their RH design approach; and identify long-term sourcing strategy for intellectual property, Respondents must provide a plan or design that demonstrates the ability to build at or below the 90nm node level that specifically details RH electronics design, fabrication, packaging and test to include: design and layout of advanced monolithic memory architectures (NV or V), the flight qualification of microelectronics for defense space applications, RH microelectronic design (e.g., mitigate total ionizing dose effects, single event effects and dose rate effects), and detailed approach for memory bandwidth considerations, input/output, and system bus schemes. Respondents must also exhibit a clear capability for advancing RH monolithic memory devices to Giga-bit (Gbit) capacity threshold levels at low power utilization.

It is planned that the enhancement contribution for the SET Advanced Memory for Space BAA effort will investigate enhancements related to fault tolerance over and above the radiation hardness threshold levels requested above which will occur in option 2. This will include:

1) Error Detection and Correction with possible enabled option at boot/configuration time at a trade of speed and power

2) Error logging and reporting for both correctable and not correctable errors

3) Ability to map out failing/failed bits/words under computer or software control

4) Built in scrubbing/refresh for memory technologies that normally might not incorporate this capability on chip