09137-Salient_Characteristics_for_PATS-70A_Teradyne.docx

Salient Characteristics for PATS-70A Scope and Arb Cards The following brand name or equivalent items are to be procured for the PATS-70A production effort:

The vendor items in the table above, along with other vendor items, have been integrated together into a system which is environmentally qualified by testing to meet the MIL-PRF-28800F Class 2. This system has also been Electro-Magnet Interference (EMI) qualified by testing to meet MIL-STD-461E. Any equivalent items submitted will need to be integrated into the system and have met these same criteria or standards of testing.

Differential Oscilloscope Card Salient Characteristics The salient characteristics for software, hardware and construction of the Differential Oscilloscope Card are:

· Software Specifications:

· Extensive software development and integration has been completed and developmentally and operationally tested. The qualifying vendor item must be able to load and run the following firmware because of the software Application Programming Interface (API) calls being initiated.

· Firmware PN: 7.01

· Minimum Qualifying Design Materials/Specifications:

· Size:

· Single Slot 3U PXI

· Weight:

· 12.3 Oz.

· Operating Temperature:

· 0 °C to 50 °C Ambient

· Storage Temperature:

· -40 °C to +75 °C

· Relative Humidity:

· 10 to 90% Non-condensing up to +40 °C

· Sample Rate:

· 20 KS/s to 400 MS/s, Non-Interleaved Real Time

· 800 MS/s to 40 GS/s, Equivalent Time

· Non-Interleaved Acquisition:

· 2 Channels @ up to 400 MS/s Real Time

· Acquisition Re-Arm Time: ≤ 5 µS

· Total Memory Options: 256 MiSamples

· Maximum Record Length:

· Non-Interleaved:

· 128 MiSamples

· Interleaved:

· 256 MiSamples

· Maximum Waveform Size:

· Normal or Fast Acquisition Mode: 128 MiSamples

· All Other Modes: 512 KiSamples

· Maximum Segments:

· 32 KiWaveforms @ ≤ 4 KiSamples

· Input Channels:

· Quantity: 2

· Connectors: SMA, Two Per Channel

· Maximum Input (50Ω, Single-Ended): ± 20V (DC + Peak AC)

· Maximum Input (1M Ω, Single-Ended): ±200V [DC + Peak AC (<100KHz)]

· Vertical Digitizer Resolution: 14 Bits (0.006% of Full Scale), up to 32 Bits with averaging

· Horizontal Sweep Time Range: 12.5 ns to 100 S (1.25 ns/div to 10 s/div)

· Inputs:

· Analog Bandwidth:

· 50 Ω: DC to 250 MHz Typical, 200 MHz Minimum

· 1MΩ: DC to 200 MHz Typical, 150 MHz Minimum

· Analog Bandwidth, Probe Z6103 Passive X10: DC to 300 MHz Typical, 250 MHz Minimum

· Rise Time: 1.15 ns

· Slew Rate: 2 KV/µs

· Impedance:

· Single-Ended: 1MΩ ± 1% Accuracy or 50 Ω ± 2% Accuracy

· Differential: 2MΩ ± 1% Accuracy or 100 Ω ± 2% Accuracy

· Input Termination (50 Ω):

· Center Tap: 50 Ω Pair Tied to Common-Mode Ground

· Open Circuit: 100 Ω Differential, Floating Common-Mode

· Input Bias:

· 50 Ω: ≤ ± 10µA

· 1MΩ: ≤ ± 1 nA

· DC Gain Accuracy: < ±0.25% Full Scale Range

· DC Offset Accuracy (+25 °C): < ± (0.15% Full Scale Range + 0.13% Offset + 1.5 mV)

· DC Offset Drift (per °C): < ±(0.0032% Full Scale Range)

· Input VSWR (50 Ω): ≤ 1.3:1, DC to 200 MHz

· Coupling: DC

· Analog Filter:

· 20 MHz or bypass

· Filter stopband rejection: Approx. 3dB @ 20 MHz

· Probe Attenuation: 0.9 to 1000:1

· Channel to Channel Isolation:

· DC to 100 MHz: ≥ 60 dB

· 100 MHz to 250 MHz: ≥ 50 dB

· Horizontal:

· Sweep Time Resolution: 10 ns to 10 ms Dependent on sweep points and sample rate

· Horizontal Position:

· Pre-Trigger: 0 to 100% of Acquisition Window

· Post-Trigger: 0 to 10,000 * Gate Resolution

· Skew Adjust:

· ±10 µs Channel-to-Channel skew adjustment

· 1 sample interval resolution

· ±1 Sample interval accuracy

· Timebase Reference: 10 MHz

· Timebase Reference Source: Internal TCXO, External Input, Backplane (PXI)

· Internal TCXO Timebase: ±2.5 PPM Accuracy

· Timebase Output: External Output

· External Input (Front Panel)

· Functionality: Trigger Input, Timebase reference input, external arm

· Absolute Maximum Input (No Damage): ≤ ± 5V (DC + Peak AC), CAT I

· Input Trigger Level Adjustment: -2 V to + 2 V, 0.5 mV Resolution, ≤ 20 mV Accuracy, 20 mV Overdrive (Input Hysteresis)

· Input Bandwidth (-3 dB): ≥ 250 MHz

· Input Impedance: 1 MΩ || 30 pF or 50 Ω, ≤ ± 2% Accuracy

· Connector (PXI): SMB

· External Output (Front Panel)

· Functionality: Trigger Output, timebase reference output, event output, programmable clock output, programmable pulse output, constant level, and probe compensation output

· Output Event Source: Arm Event, trigger A event, trigger B event, trigger complete event, capture complete event, operation complete event, master summary status event, limit test successful event

· Polarity: High or low truth

· Programmable event pulse width: 50 ns to 163 ms

· Programmable clock: Period: 26.667 ns to 100 seconds, 50% duty cycle

· Programmable Pulse:

· Pulse Repetition Interval: 26.667 ns to 100 seconds

· Pulse Width: 26.667 ns

· Probe Compensation: 10 KHz clock which can be used to compensate probes

· Limit test successful: Event pulse after each capture upon limit or mask test success

· Output Level: TTL Compatible into ≥200 Ω, ≥±24 mA output drive

· Output enable: Tri-State output capability

· Connector (PXI): SMB

· Backplane Triggers

· Functionality: Multi-Instrument Synchronization trigger, event output signals

· Triggers: TTL Trigger 0-7

· Direction: Input or output

· Source: Arm event, trigger A event, trigger B event, trigger complete event, capture complete event, operation complete event, master summary status event, constant level

· Polarity: High or low truth

· Programmable event pulse width: 50 ns to 163 ms Arbitrary Signal Generator Card Salient Characteristics The salient characteristics for software, hardware and construction of the Arbitrary Signal Generator Card are:

· Software Specifications:

· Extensive software development and integration has been completed and developmentally and operationally tested. The qualifying vendor item must be able to load and run the following firmware because of the software Application Programming Interface (API) calls being initiated.

· Firmware PN: 2.03

· Minimum Qualifying Design Materials/Specifications:

· Size:

· Single Slot 3U PXI

· Channels:

· 2 Analog Outputs

· Connectors:

· BNC Output/SMB Trigger

· Analog Bandwidth:

· DC to 10 MHz (± 0.1 dB Passband Flatness)

· DC to 25 MHz (-1 dB Bandwidth)

· DC to 50 MHz (-3 dB Bandwidth)

· Lowpass Filters:

· 50 MHz, 5-Pole Bessel

· 10 MHz, 5-Pole Bessel

· 1 MHz, 5-Pole Bessel

· 100 KHz, 5-Pole Bessel

· Slew Rate:

· > 2 KV/µs into 50 Ohm (50 MHz Filter)

· Rise/Fall Time:

· < 7 ns for 10 V step into 50 Ohm (50 MHz Filter)

· Range Adjust:

· Into 50 Ohm: 15 mVPP to 14 VPP

· Into 1M Ohm: 30 mVPP to 28 VPP

· Range Independently adjustable for each output channel

· Full-Scale Range Adjustment preserves Function Generator 14 Bit DAC resolution and Dynamic Range

· DC Offset Adjust:

· Into 50 Ohm: < or = ± 7V

· Into 1M Ohm: < or = ± 14V

· Output Voltage Limit:

· Into 50 Ohm: |Vamp + VOffs| < or = 7 V

· Into 1M Ohm: |Vamp + VOffs| < or = 14 V

· (VAmp = Range/2, VOffs = DC Offset)

· Output Current Limit:

· ± 140 mA Recommended Operating Maximum

· ±350 mA Short Circuit Maximum

· Range Resolution:

· 0.5 mVPP

· Specification shown for high-impedance load

· Divide specifications by 2 for 50 Ohm load

· Range Accuracy (at calibration temperature ± 5 °C ambient):

· < ± (0.5% of range + 10 mVPP)

· Specification shown for high impedance load

· Divide specification by 2 for 50 Ohm load

· Calibration temperature is typically 25 °C ambient

· Range Drift:

· 1.5 <± mVPP per °C

· Specification shown for high impedance load

· Divide specifications by 2 for 50 Ohm load

· Output Impedance:

· 50 Ohms typical

· DAC Specifications:

· DAC Resolution: 14 Bits (0.0061% of full-scale range)

· Waveform Length: 4 samples to 32 Misamples per channel

· DAC Clock: DAC Sample clocks generated by direct Digital synthesizers. All channels have independent or common DAC sample clocks

· DAC Clock Rate: 200 Samples/s to 200 MSamples/s

· DAC Clock Resolution: < 0.01 PPM or > 8 digits (i.e. 0.116 Hz from 20 MS/s to 200 MS/s)

· DAC Clock Sweep: Swept DAC Clock Rate: Linear or Log Sweep

· DAC Clock Output: External Output: 100 Hz to 100 MHz common clock source

· DAC Clock Jitter: < 20 ps

· Channel-to-Channel Skew: < 500 ps (50 MHz Filter)

· Channel to Channel Isolation: > or = 60 dB

· RMS Noise (with DAC Clock above filter cutoff): ≤ 1mV into 50 Ohm (50 MHz Filter)